1 /* 2 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef __MSM_DRV_H__ 20 #define __MSM_DRV_H__ 21 22 #include <linux/kernel.h> 23 #include <linux/clk.h> 24 #include <linux/cpufreq.h> 25 #include <linux/module.h> 26 #include <linux/component.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/slab.h> 31 #include <linux/list.h> 32 #include <linux/iommu.h> 33 #include <linux/types.h> 34 #include <linux/of_graph.h> 35 #include <linux/of_device.h> 36 #include <asm/sizes.h> 37 #include <linux/kthread.h> 38 39 #include <drm/drmP.h> 40 #include <drm/drm_atomic.h> 41 #include <drm/drm_atomic_helper.h> 42 #include <drm/drm_crtc_helper.h> 43 #include <drm/drm_plane_helper.h> 44 #include <drm/drm_fb_helper.h> 45 #include <drm/msm_drm.h> 46 #include <drm/drm_gem.h> 47 48 struct msm_kms; 49 struct msm_gpu; 50 struct msm_mmu; 51 struct msm_mdss; 52 struct msm_rd_state; 53 struct msm_perf_state; 54 struct msm_gem_submit; 55 struct msm_fence_context; 56 struct msm_gem_address_space; 57 struct msm_gem_vma; 58 59 #define MAX_CRTCS 8 60 #define MAX_PLANES 20 61 #define MAX_ENCODERS 8 62 #define MAX_BRIDGES 8 63 #define MAX_CONNECTORS 8 64 65 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 66 67 struct msm_file_private { 68 rwlock_t queuelock; 69 struct list_head submitqueues; 70 int queueid; 71 }; 72 73 enum msm_mdp_plane_property { 74 PLANE_PROP_ZPOS, 75 PLANE_PROP_ALPHA, 76 PLANE_PROP_PREMULTIPLIED, 77 PLANE_PROP_MAX_NUM 78 }; 79 80 struct msm_vblank_ctrl { 81 struct kthread_work work; 82 struct list_head event_list; 83 spinlock_t lock; 84 }; 85 86 #define MSM_GPU_MAX_RINGS 4 87 #define MAX_H_TILES_PER_DISPLAY 2 88 89 /** 90 * enum msm_display_caps - features/capabilities supported by displays 91 * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported 92 * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported 93 * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported 94 * @MSM_DISPLAY_CAP_EDID: EDID supported 95 */ 96 enum msm_display_caps { 97 MSM_DISPLAY_CAP_VID_MODE = BIT(0), 98 MSM_DISPLAY_CAP_CMD_MODE = BIT(1), 99 MSM_DISPLAY_CAP_HOT_PLUG = BIT(2), 100 MSM_DISPLAY_CAP_EDID = BIT(3), 101 }; 102 103 /** 104 * enum msm_event_wait - type of HW events to wait for 105 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW 106 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel 107 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters) 108 */ 109 enum msm_event_wait { 110 MSM_ENC_COMMIT_DONE = 0, 111 MSM_ENC_TX_COMPLETE, 112 MSM_ENC_VBLANK, 113 }; 114 115 /** 116 * struct msm_display_topology - defines a display topology pipeline 117 * @num_lm: number of layer mixers used 118 * @num_enc: number of compression encoder blocks used 119 * @num_intf: number of interfaces the panel is mounted on 120 */ 121 struct msm_display_topology { 122 u32 num_lm; 123 u32 num_enc; 124 u32 num_intf; 125 }; 126 127 /** 128 * struct msm_display_info - defines display properties 129 * @intf_type: DRM_MODE_CONNECTOR_ display type 130 * @capabilities: Bitmask of display flags 131 * @num_of_h_tiles: Number of horizontal tiles in case of split interface 132 * @h_tile_instance: Controller instance used per tile. Number of elements is 133 * based on num_of_h_tiles 134 * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is 135 * used instead of panel TE in cmd mode panels 136 */ 137 struct msm_display_info { 138 int intf_type; 139 uint32_t capabilities; 140 uint32_t num_of_h_tiles; 141 uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; 142 bool is_te_using_watchdog_timer; 143 }; 144 145 /* Commit/Event thread specific structure */ 146 struct msm_drm_thread { 147 struct drm_device *dev; 148 struct task_struct *thread; 149 unsigned int crtc_id; 150 struct kthread_worker worker; 151 }; 152 153 struct msm_drm_private { 154 155 struct drm_device *dev; 156 157 struct msm_kms *kms; 158 159 /* subordinate devices, if present: */ 160 struct platform_device *gpu_pdev; 161 162 /* top level MDSS wrapper device (for MDP5/DPU only) */ 163 struct msm_mdss *mdss; 164 165 /* possibly this should be in the kms component, but it is 166 * shared by both mdp4 and mdp5.. 167 */ 168 struct hdmi *hdmi; 169 170 /* eDP is for mdp5 only, but kms has not been created 171 * when edp_bind() and edp_init() are called. Here is the only 172 * place to keep the edp instance. 173 */ 174 struct msm_edp *edp; 175 176 /* DSI is shared by mdp4 and mdp5 */ 177 struct msm_dsi *dsi[2]; 178 179 /* when we have more than one 'msm_gpu' these need to be an array: */ 180 struct msm_gpu *gpu; 181 struct msm_file_private *lastctx; 182 183 struct drm_fb_helper *fbdev; 184 185 struct msm_rd_state *rd; /* debugfs to dump all submits */ 186 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 187 struct msm_perf_state *perf; 188 189 /* list of GEM objects: */ 190 struct list_head inactive_list; 191 192 struct workqueue_struct *wq; 193 194 unsigned int num_planes; 195 struct drm_plane *planes[MAX_PLANES]; 196 197 unsigned int num_crtcs; 198 struct drm_crtc *crtcs[MAX_CRTCS]; 199 200 struct msm_drm_thread disp_thread[MAX_CRTCS]; 201 struct msm_drm_thread event_thread[MAX_CRTCS]; 202 203 unsigned int num_encoders; 204 struct drm_encoder *encoders[MAX_ENCODERS]; 205 206 unsigned int num_bridges; 207 struct drm_bridge *bridges[MAX_BRIDGES]; 208 209 unsigned int num_connectors; 210 struct drm_connector *connectors[MAX_CONNECTORS]; 211 212 /* Properties */ 213 struct drm_property *plane_property[PLANE_PROP_MAX_NUM]; 214 215 /* VRAM carveout, used when no IOMMU: */ 216 struct { 217 unsigned long size; 218 dma_addr_t paddr; 219 /* NOTE: mm managed at the page level, size is in # of pages 220 * and position mm_node->start is in # of pages: 221 */ 222 struct drm_mm mm; 223 spinlock_t lock; /* Protects drm_mm node allocation/removal */ 224 } vram; 225 226 struct notifier_block vmap_notifier; 227 struct shrinker shrinker; 228 229 struct msm_vblank_ctrl vblank_ctrl; 230 struct drm_atomic_state *pm_state; 231 }; 232 233 struct msm_format { 234 uint32_t pixel_format; 235 }; 236 237 int msm_atomic_prepare_fb(struct drm_plane *plane, 238 struct drm_plane_state *new_state); 239 void msm_atomic_commit_tail(struct drm_atomic_state *state); 240 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 241 void msm_atomic_state_clear(struct drm_atomic_state *state); 242 void msm_atomic_state_free(struct drm_atomic_state *state); 243 244 void msm_gem_unmap_vma(struct msm_gem_address_space *aspace, 245 struct msm_gem_vma *vma, struct sg_table *sgt); 246 int msm_gem_map_vma(struct msm_gem_address_space *aspace, 247 struct msm_gem_vma *vma, struct sg_table *sgt, int npages); 248 249 void msm_gem_address_space_put(struct msm_gem_address_space *aspace); 250 251 struct msm_gem_address_space * 252 msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain, 253 const char *name); 254 255 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 256 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 257 258 void msm_gem_submit_free(struct msm_gem_submit *submit); 259 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 260 struct drm_file *file); 261 262 void msm_gem_shrinker_init(struct drm_device *dev); 263 void msm_gem_shrinker_cleanup(struct drm_device *dev); 264 265 int msm_gem_mmap_obj(struct drm_gem_object *obj, 266 struct vm_area_struct *vma); 267 int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma); 268 vm_fault_t msm_gem_fault(struct vm_fault *vmf); 269 uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); 270 int msm_gem_get_iova(struct drm_gem_object *obj, 271 struct msm_gem_address_space *aspace, uint64_t *iova); 272 uint64_t msm_gem_iova(struct drm_gem_object *obj, 273 struct msm_gem_address_space *aspace); 274 struct page **msm_gem_get_pages(struct drm_gem_object *obj); 275 void msm_gem_put_pages(struct drm_gem_object *obj); 276 void msm_gem_put_iova(struct drm_gem_object *obj, 277 struct msm_gem_address_space *aspace); 278 int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, 279 struct drm_mode_create_dumb *args); 280 int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, 281 uint32_t handle, uint64_t *offset); 282 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 283 void *msm_gem_prime_vmap(struct drm_gem_object *obj); 284 void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 285 int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 286 struct reservation_object *msm_gem_prime_res_obj(struct drm_gem_object *obj); 287 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 288 struct dma_buf_attachment *attach, struct sg_table *sg); 289 int msm_gem_prime_pin(struct drm_gem_object *obj); 290 void msm_gem_prime_unpin(struct drm_gem_object *obj); 291 void *msm_gem_get_vaddr(struct drm_gem_object *obj); 292 void *msm_gem_get_vaddr_active(struct drm_gem_object *obj); 293 void msm_gem_put_vaddr(struct drm_gem_object *obj); 294 int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv); 295 int msm_gem_sync_object(struct drm_gem_object *obj, 296 struct msm_fence_context *fctx, bool exclusive); 297 void msm_gem_move_to_active(struct drm_gem_object *obj, 298 struct msm_gpu *gpu, bool exclusive, struct dma_fence *fence); 299 void msm_gem_move_to_inactive(struct drm_gem_object *obj); 300 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout); 301 int msm_gem_cpu_fini(struct drm_gem_object *obj); 302 void msm_gem_free_object(struct drm_gem_object *obj); 303 int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, 304 uint32_t size, uint32_t flags, uint32_t *handle); 305 struct drm_gem_object *msm_gem_new(struct drm_device *dev, 306 uint32_t size, uint32_t flags); 307 struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev, 308 uint32_t size, uint32_t flags); 309 void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size, 310 uint32_t flags, struct msm_gem_address_space *aspace, 311 struct drm_gem_object **bo, uint64_t *iova); 312 void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size, 313 uint32_t flags, struct msm_gem_address_space *aspace, 314 struct drm_gem_object **bo, uint64_t *iova); 315 struct drm_gem_object *msm_gem_import(struct drm_device *dev, 316 struct dma_buf *dmabuf, struct sg_table *sgt); 317 318 int msm_framebuffer_prepare(struct drm_framebuffer *fb, 319 struct msm_gem_address_space *aspace); 320 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, 321 struct msm_gem_address_space *aspace); 322 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, 323 struct msm_gem_address_space *aspace, int plane); 324 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 325 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 326 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 327 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 328 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 329 int w, int h, int p, uint32_t format); 330 331 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); 332 void msm_fbdev_free(struct drm_device *dev); 333 334 struct hdmi; 335 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 336 struct drm_encoder *encoder); 337 void __init msm_hdmi_register(void); 338 void __exit msm_hdmi_unregister(void); 339 340 struct msm_edp; 341 void __init msm_edp_register(void); 342 void __exit msm_edp_unregister(void); 343 int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev, 344 struct drm_encoder *encoder); 345 346 struct msm_dsi; 347 #ifdef CONFIG_DRM_MSM_DSI 348 void __init msm_dsi_register(void); 349 void __exit msm_dsi_unregister(void); 350 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 351 struct drm_encoder *encoder); 352 #else 353 static inline void __init msm_dsi_register(void) 354 { 355 } 356 static inline void __exit msm_dsi_unregister(void) 357 { 358 } 359 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 360 struct drm_device *dev, 361 struct drm_encoder *encoder) 362 { 363 return -EINVAL; 364 } 365 #endif 366 367 void __init msm_mdp_register(void); 368 void __exit msm_mdp_unregister(void); 369 void __init msm_dpu_register(void); 370 void __exit msm_dpu_unregister(void); 371 372 #ifdef CONFIG_DEBUG_FS 373 void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); 374 void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); 375 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 376 int msm_debugfs_late_init(struct drm_device *dev); 377 int msm_rd_debugfs_init(struct drm_minor *minor); 378 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 379 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 380 const char *fmt, ...); 381 int msm_perf_debugfs_init(struct drm_minor *minor); 382 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 383 #else 384 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 385 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 386 const char *fmt, ...) {} 387 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 388 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 389 #endif 390 391 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 392 int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk); 393 394 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 395 const char *name); 396 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, 397 const char *dbgname); 398 void msm_writel(u32 data, void __iomem *addr); 399 u32 msm_readl(const void __iomem *addr); 400 401 struct msm_gpu_submitqueue; 402 int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx); 403 struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx, 404 u32 id); 405 int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, 406 u32 prio, u32 flags, u32 *id); 407 int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id); 408 void msm_submitqueue_close(struct msm_file_private *ctx); 409 410 void msm_submitqueue_destroy(struct kref *kref); 411 412 413 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 414 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 415 416 static inline int align_pitch(int width, int bpp) 417 { 418 int bytespp = (bpp + 7) / 8; 419 /* adreno needs pitch aligned to 32 pixels: */ 420 return bytespp * ALIGN(width, 32); 421 } 422 423 /* for the generated headers: */ 424 #define INVALID_IDX(idx) ({BUG(); 0;}) 425 #define fui(x) ({BUG(); 0;}) 426 #define util_float_to_half(x) ({BUG(); 0;}) 427 428 429 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 430 431 /* for conditionally setting boolean flag(s): */ 432 #define COND(bool, val) ((bool) ? (val) : 0) 433 434 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 435 { 436 ktime_t now = ktime_get(); 437 unsigned long remaining_jiffies; 438 439 if (ktime_compare(*timeout, now) < 0) { 440 remaining_jiffies = 0; 441 } else { 442 ktime_t rem = ktime_sub(*timeout, now); 443 struct timespec ts = ktime_to_timespec(rem); 444 remaining_jiffies = timespec_to_jiffies(&ts); 445 } 446 447 return remaining_jiffies; 448 } 449 450 #endif /* __MSM_DRV_H__ */ 451