1 /* 2 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef __MSM_DRV_H__ 20 #define __MSM_DRV_H__ 21 22 #include <linux/kernel.h> 23 #include <linux/clk.h> 24 #include <linux/cpufreq.h> 25 #include <linux/module.h> 26 #include <linux/component.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/slab.h> 31 #include <linux/list.h> 32 #include <linux/iommu.h> 33 #include <linux/types.h> 34 #include <linux/of_graph.h> 35 #include <linux/of_device.h> 36 #include <asm/sizes.h> 37 #include <linux/kthread.h> 38 39 #include <drm/drmP.h> 40 #include <drm/drm_atomic.h> 41 #include <drm/drm_atomic_helper.h> 42 #include <drm/drm_plane_helper.h> 43 #include <drm/drm_probe_helper.h> 44 #include <drm/drm_fb_helper.h> 45 #include <drm/msm_drm.h> 46 #include <drm/drm_gem.h> 47 48 struct msm_kms; 49 struct msm_gpu; 50 struct msm_mmu; 51 struct msm_mdss; 52 struct msm_rd_state; 53 struct msm_perf_state; 54 struct msm_gem_submit; 55 struct msm_fence_context; 56 struct msm_gem_address_space; 57 struct msm_gem_vma; 58 59 #define MAX_CRTCS 8 60 #define MAX_PLANES 20 61 #define MAX_ENCODERS 8 62 #define MAX_BRIDGES 8 63 #define MAX_CONNECTORS 8 64 65 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 66 67 struct msm_file_private { 68 rwlock_t queuelock; 69 struct list_head submitqueues; 70 int queueid; 71 }; 72 73 enum msm_mdp_plane_property { 74 PLANE_PROP_ZPOS, 75 PLANE_PROP_ALPHA, 76 PLANE_PROP_PREMULTIPLIED, 77 PLANE_PROP_MAX_NUM 78 }; 79 80 #define MSM_GPU_MAX_RINGS 4 81 #define MAX_H_TILES_PER_DISPLAY 2 82 83 /** 84 * enum msm_display_caps - features/capabilities supported by displays 85 * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported 86 * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported 87 * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported 88 * @MSM_DISPLAY_CAP_EDID: EDID supported 89 */ 90 enum msm_display_caps { 91 MSM_DISPLAY_CAP_VID_MODE = BIT(0), 92 MSM_DISPLAY_CAP_CMD_MODE = BIT(1), 93 MSM_DISPLAY_CAP_HOT_PLUG = BIT(2), 94 MSM_DISPLAY_CAP_EDID = BIT(3), 95 }; 96 97 /** 98 * enum msm_event_wait - type of HW events to wait for 99 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW 100 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel 101 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters) 102 */ 103 enum msm_event_wait { 104 MSM_ENC_COMMIT_DONE = 0, 105 MSM_ENC_TX_COMPLETE, 106 MSM_ENC_VBLANK, 107 }; 108 109 /** 110 * struct msm_display_topology - defines a display topology pipeline 111 * @num_lm: number of layer mixers used 112 * @num_enc: number of compression encoder blocks used 113 * @num_intf: number of interfaces the panel is mounted on 114 */ 115 struct msm_display_topology { 116 u32 num_lm; 117 u32 num_enc; 118 u32 num_intf; 119 }; 120 121 /** 122 * struct msm_display_info - defines display properties 123 * @intf_type: DRM_MODE_ENCODER_ type 124 * @capabilities: Bitmask of display flags 125 * @num_of_h_tiles: Number of horizontal tiles in case of split interface 126 * @h_tile_instance: Controller instance used per tile. Number of elements is 127 * based on num_of_h_tiles 128 * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is 129 * used instead of panel TE in cmd mode panels 130 */ 131 struct msm_display_info { 132 int intf_type; 133 uint32_t capabilities; 134 uint32_t num_of_h_tiles; 135 uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; 136 bool is_te_using_watchdog_timer; 137 }; 138 139 /* Commit/Event thread specific structure */ 140 struct msm_drm_thread { 141 struct drm_device *dev; 142 struct task_struct *thread; 143 unsigned int crtc_id; 144 struct kthread_worker worker; 145 }; 146 147 struct msm_drm_private { 148 149 struct drm_device *dev; 150 151 struct msm_kms *kms; 152 153 /* subordinate devices, if present: */ 154 struct platform_device *gpu_pdev; 155 156 /* top level MDSS wrapper device (for MDP5/DPU only) */ 157 struct msm_mdss *mdss; 158 159 /* possibly this should be in the kms component, but it is 160 * shared by both mdp4 and mdp5.. 161 */ 162 struct hdmi *hdmi; 163 164 /* eDP is for mdp5 only, but kms has not been created 165 * when edp_bind() and edp_init() are called. Here is the only 166 * place to keep the edp instance. 167 */ 168 struct msm_edp *edp; 169 170 /* DSI is shared by mdp4 and mdp5 */ 171 struct msm_dsi *dsi[2]; 172 173 /* when we have more than one 'msm_gpu' these need to be an array: */ 174 struct msm_gpu *gpu; 175 struct msm_file_private *lastctx; 176 /* gpu is only set on open(), but we need this info earlier */ 177 bool is_a2xx; 178 179 struct drm_fb_helper *fbdev; 180 181 struct msm_rd_state *rd; /* debugfs to dump all submits */ 182 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 183 struct msm_perf_state *perf; 184 185 /* list of GEM objects: */ 186 struct list_head inactive_list; 187 188 struct workqueue_struct *wq; 189 190 unsigned int num_planes; 191 struct drm_plane *planes[MAX_PLANES]; 192 193 unsigned int num_crtcs; 194 struct drm_crtc *crtcs[MAX_CRTCS]; 195 196 struct msm_drm_thread event_thread[MAX_CRTCS]; 197 198 unsigned int num_encoders; 199 struct drm_encoder *encoders[MAX_ENCODERS]; 200 201 unsigned int num_bridges; 202 struct drm_bridge *bridges[MAX_BRIDGES]; 203 204 unsigned int num_connectors; 205 struct drm_connector *connectors[MAX_CONNECTORS]; 206 207 /* Properties */ 208 struct drm_property *plane_property[PLANE_PROP_MAX_NUM]; 209 210 /* VRAM carveout, used when no IOMMU: */ 211 struct { 212 unsigned long size; 213 dma_addr_t paddr; 214 /* NOTE: mm managed at the page level, size is in # of pages 215 * and position mm_node->start is in # of pages: 216 */ 217 struct drm_mm mm; 218 spinlock_t lock; /* Protects drm_mm node allocation/removal */ 219 } vram; 220 221 struct notifier_block vmap_notifier; 222 struct shrinker shrinker; 223 224 struct drm_atomic_state *pm_state; 225 }; 226 227 struct msm_format { 228 uint32_t pixel_format; 229 }; 230 231 int msm_atomic_prepare_fb(struct drm_plane *plane, 232 struct drm_plane_state *new_state); 233 void msm_atomic_commit_tail(struct drm_atomic_state *state); 234 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 235 void msm_atomic_state_clear(struct drm_atomic_state *state); 236 void msm_atomic_state_free(struct drm_atomic_state *state); 237 238 int msm_gem_init_vma(struct msm_gem_address_space *aspace, 239 struct msm_gem_vma *vma, int npages); 240 void msm_gem_purge_vma(struct msm_gem_address_space *aspace, 241 struct msm_gem_vma *vma); 242 void msm_gem_unmap_vma(struct msm_gem_address_space *aspace, 243 struct msm_gem_vma *vma); 244 int msm_gem_map_vma(struct msm_gem_address_space *aspace, 245 struct msm_gem_vma *vma, int prot, 246 struct sg_table *sgt, int npages); 247 void msm_gem_close_vma(struct msm_gem_address_space *aspace, 248 struct msm_gem_vma *vma); 249 250 void msm_gem_address_space_put(struct msm_gem_address_space *aspace); 251 252 struct msm_gem_address_space * 253 msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain, 254 const char *name); 255 256 struct msm_gem_address_space * 257 msm_gem_address_space_create_a2xx(struct device *dev, struct msm_gpu *gpu, 258 const char *name, uint64_t va_start, uint64_t va_end); 259 260 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 261 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 262 263 bool msm_use_mmu(struct drm_device *dev); 264 265 void msm_gem_submit_free(struct msm_gem_submit *submit); 266 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 267 struct drm_file *file); 268 269 void msm_gem_shrinker_init(struct drm_device *dev); 270 void msm_gem_shrinker_cleanup(struct drm_device *dev); 271 272 int msm_gem_mmap_obj(struct drm_gem_object *obj, 273 struct vm_area_struct *vma); 274 int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma); 275 vm_fault_t msm_gem_fault(struct vm_fault *vmf); 276 uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); 277 int msm_gem_get_iova(struct drm_gem_object *obj, 278 struct msm_gem_address_space *aspace, uint64_t *iova); 279 int msm_gem_get_and_pin_iova(struct drm_gem_object *obj, 280 struct msm_gem_address_space *aspace, uint64_t *iova); 281 uint64_t msm_gem_iova(struct drm_gem_object *obj, 282 struct msm_gem_address_space *aspace); 283 void msm_gem_unpin_iova(struct drm_gem_object *obj, 284 struct msm_gem_address_space *aspace); 285 struct page **msm_gem_get_pages(struct drm_gem_object *obj); 286 void msm_gem_put_pages(struct drm_gem_object *obj); 287 int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, 288 struct drm_mode_create_dumb *args); 289 int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, 290 uint32_t handle, uint64_t *offset); 291 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 292 void *msm_gem_prime_vmap(struct drm_gem_object *obj); 293 void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 294 int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 295 struct reservation_object *msm_gem_prime_res_obj(struct drm_gem_object *obj); 296 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 297 struct dma_buf_attachment *attach, struct sg_table *sg); 298 int msm_gem_prime_pin(struct drm_gem_object *obj); 299 void msm_gem_prime_unpin(struct drm_gem_object *obj); 300 void *msm_gem_get_vaddr(struct drm_gem_object *obj); 301 void *msm_gem_get_vaddr_active(struct drm_gem_object *obj); 302 void msm_gem_put_vaddr(struct drm_gem_object *obj); 303 int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv); 304 int msm_gem_sync_object(struct drm_gem_object *obj, 305 struct msm_fence_context *fctx, bool exclusive); 306 void msm_gem_move_to_active(struct drm_gem_object *obj, 307 struct msm_gpu *gpu, bool exclusive, struct dma_fence *fence); 308 void msm_gem_move_to_inactive(struct drm_gem_object *obj); 309 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout); 310 int msm_gem_cpu_fini(struct drm_gem_object *obj); 311 void msm_gem_free_object(struct drm_gem_object *obj); 312 int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, 313 uint32_t size, uint32_t flags, uint32_t *handle, char *name); 314 struct drm_gem_object *msm_gem_new(struct drm_device *dev, 315 uint32_t size, uint32_t flags); 316 struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev, 317 uint32_t size, uint32_t flags); 318 void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size, 319 uint32_t flags, struct msm_gem_address_space *aspace, 320 struct drm_gem_object **bo, uint64_t *iova); 321 void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size, 322 uint32_t flags, struct msm_gem_address_space *aspace, 323 struct drm_gem_object **bo, uint64_t *iova); 324 void msm_gem_kernel_put(struct drm_gem_object *bo, 325 struct msm_gem_address_space *aspace, bool locked); 326 struct drm_gem_object *msm_gem_import(struct drm_device *dev, 327 struct dma_buf *dmabuf, struct sg_table *sgt); 328 329 __printf(2, 3) 330 void msm_gem_object_set_name(struct drm_gem_object *bo, const char *fmt, ...); 331 332 int msm_framebuffer_prepare(struct drm_framebuffer *fb, 333 struct msm_gem_address_space *aspace); 334 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, 335 struct msm_gem_address_space *aspace); 336 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, 337 struct msm_gem_address_space *aspace, int plane); 338 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 339 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 340 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 341 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 342 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 343 int w, int h, int p, uint32_t format); 344 345 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); 346 void msm_fbdev_free(struct drm_device *dev); 347 348 struct hdmi; 349 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 350 struct drm_encoder *encoder); 351 void __init msm_hdmi_register(void); 352 void __exit msm_hdmi_unregister(void); 353 354 struct msm_edp; 355 void __init msm_edp_register(void); 356 void __exit msm_edp_unregister(void); 357 int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev, 358 struct drm_encoder *encoder); 359 360 struct msm_dsi; 361 #ifdef CONFIG_DRM_MSM_DSI 362 void __init msm_dsi_register(void); 363 void __exit msm_dsi_unregister(void); 364 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 365 struct drm_encoder *encoder); 366 #else 367 static inline void __init msm_dsi_register(void) 368 { 369 } 370 static inline void __exit msm_dsi_unregister(void) 371 { 372 } 373 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 374 struct drm_device *dev, 375 struct drm_encoder *encoder) 376 { 377 return -EINVAL; 378 } 379 #endif 380 381 void __init msm_mdp_register(void); 382 void __exit msm_mdp_unregister(void); 383 void __init msm_dpu_register(void); 384 void __exit msm_dpu_unregister(void); 385 386 #ifdef CONFIG_DEBUG_FS 387 void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); 388 void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); 389 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 390 int msm_debugfs_late_init(struct drm_device *dev); 391 int msm_rd_debugfs_init(struct drm_minor *minor); 392 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 393 __printf(3, 4) 394 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 395 const char *fmt, ...); 396 int msm_perf_debugfs_init(struct drm_minor *minor); 397 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 398 #else 399 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 400 __printf(3, 4) 401 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 402 const char *fmt, ...) {} 403 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 404 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 405 #endif 406 407 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 408 int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk); 409 410 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 411 const char *name); 412 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, 413 const char *dbgname); 414 void msm_writel(u32 data, void __iomem *addr); 415 u32 msm_readl(const void __iomem *addr); 416 417 struct msm_gpu_submitqueue; 418 int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx); 419 struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx, 420 u32 id); 421 int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, 422 u32 prio, u32 flags, u32 *id); 423 int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id); 424 void msm_submitqueue_close(struct msm_file_private *ctx); 425 426 void msm_submitqueue_destroy(struct kref *kref); 427 428 429 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 430 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 431 432 static inline int align_pitch(int width, int bpp) 433 { 434 int bytespp = (bpp + 7) / 8; 435 /* adreno needs pitch aligned to 32 pixels: */ 436 return bytespp * ALIGN(width, 32); 437 } 438 439 /* for the generated headers: */ 440 #define INVALID_IDX(idx) ({BUG(); 0;}) 441 #define fui(x) ({BUG(); 0;}) 442 #define util_float_to_half(x) ({BUG(); 0;}) 443 444 445 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 446 447 /* for conditionally setting boolean flag(s): */ 448 #define COND(bool, val) ((bool) ? (val) : 0) 449 450 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 451 { 452 ktime_t now = ktime_get(); 453 unsigned long remaining_jiffies; 454 455 if (ktime_compare(*timeout, now) < 0) { 456 remaining_jiffies = 0; 457 } else { 458 ktime_t rem = ktime_sub(*timeout, now); 459 struct timespec ts = ktime_to_timespec(rem); 460 remaining_jiffies = timespec_to_jiffies(&ts); 461 } 462 463 return remaining_jiffies; 464 } 465 466 #endif /* __MSM_DRV_H__ */ 467