1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #ifndef __MSM_DRV_H__ 9 #define __MSM_DRV_H__ 10 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/cpufreq.h> 14 #include <linux/module.h> 15 #include <linux/component.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/slab.h> 20 #include <linux/list.h> 21 #include <linux/iommu.h> 22 #include <linux/types.h> 23 #include <linux/of_graph.h> 24 #include <linux/of_device.h> 25 #include <linux/sizes.h> 26 #include <linux/kthread.h> 27 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_plane_helper.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_fb_helper.h> 33 #include <drm/msm_drm.h> 34 #include <drm/drm_gem.h> 35 36 struct msm_kms; 37 struct msm_gpu; 38 struct msm_mmu; 39 struct msm_mdss; 40 struct msm_rd_state; 41 struct msm_perf_state; 42 struct msm_gem_submit; 43 struct msm_fence_context; 44 struct msm_gem_address_space; 45 struct msm_gem_vma; 46 struct msm_disp_state; 47 48 #define MAX_CRTCS 8 49 #define MAX_PLANES 20 50 #define MAX_ENCODERS 8 51 #define MAX_BRIDGES 8 52 #define MAX_CONNECTORS 8 53 54 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 55 56 struct msm_file_private { 57 rwlock_t queuelock; 58 struct list_head submitqueues; 59 int queueid; 60 struct msm_gem_address_space *aspace; 61 struct kref ref; 62 }; 63 64 enum msm_mdp_plane_property { 65 PLANE_PROP_ZPOS, 66 PLANE_PROP_ALPHA, 67 PLANE_PROP_PREMULTIPLIED, 68 PLANE_PROP_MAX_NUM 69 }; 70 71 #define MSM_GPU_MAX_RINGS 4 72 #define MAX_H_TILES_PER_DISPLAY 2 73 74 /** 75 * enum msm_display_caps - features/capabilities supported by displays 76 * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported 77 * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported 78 * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported 79 * @MSM_DISPLAY_CAP_EDID: EDID supported 80 */ 81 enum msm_display_caps { 82 MSM_DISPLAY_CAP_VID_MODE = BIT(0), 83 MSM_DISPLAY_CAP_CMD_MODE = BIT(1), 84 MSM_DISPLAY_CAP_HOT_PLUG = BIT(2), 85 MSM_DISPLAY_CAP_EDID = BIT(3), 86 }; 87 88 /** 89 * enum msm_event_wait - type of HW events to wait for 90 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW 91 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel 92 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters) 93 */ 94 enum msm_event_wait { 95 MSM_ENC_COMMIT_DONE = 0, 96 MSM_ENC_TX_COMPLETE, 97 MSM_ENC_VBLANK, 98 }; 99 100 /** 101 * struct msm_display_topology - defines a display topology pipeline 102 * @num_lm: number of layer mixers used 103 * @num_enc: number of compression encoder blocks used 104 * @num_intf: number of interfaces the panel is mounted on 105 */ 106 struct msm_display_topology { 107 u32 num_lm; 108 u32 num_enc; 109 u32 num_intf; 110 u32 num_dspp; 111 }; 112 113 /** 114 * struct msm_display_info - defines display properties 115 * @intf_type: DRM_MODE_ENCODER_ type 116 * @capabilities: Bitmask of display flags 117 * @num_of_h_tiles: Number of horizontal tiles in case of split interface 118 * @h_tile_instance: Controller instance used per tile. Number of elements is 119 * based on num_of_h_tiles 120 * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is 121 * used instead of panel TE in cmd mode panels 122 */ 123 struct msm_display_info { 124 int intf_type; 125 uint32_t capabilities; 126 uint32_t num_of_h_tiles; 127 uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; 128 bool is_te_using_watchdog_timer; 129 }; 130 131 /* Commit/Event thread specific structure */ 132 struct msm_drm_thread { 133 struct drm_device *dev; 134 unsigned int crtc_id; 135 struct kthread_worker *worker; 136 }; 137 138 struct msm_drm_private { 139 140 struct drm_device *dev; 141 142 struct msm_kms *kms; 143 144 /* subordinate devices, if present: */ 145 struct platform_device *gpu_pdev; 146 147 /* top level MDSS wrapper device (for MDP5/DPU only) */ 148 struct msm_mdss *mdss; 149 150 /* possibly this should be in the kms component, but it is 151 * shared by both mdp4 and mdp5.. 152 */ 153 struct hdmi *hdmi; 154 155 /* eDP is for mdp5 only, but kms has not been created 156 * when edp_bind() and edp_init() are called. Here is the only 157 * place to keep the edp instance. 158 */ 159 struct msm_edp *edp; 160 161 /* DSI is shared by mdp4 and mdp5 */ 162 struct msm_dsi *dsi[2]; 163 164 struct msm_dp *dp; 165 166 /* when we have more than one 'msm_gpu' these need to be an array: */ 167 struct msm_gpu *gpu; 168 struct msm_file_private *lastctx; 169 /* gpu is only set on open(), but we need this info earlier */ 170 bool is_a2xx; 171 bool has_cached_coherent; 172 173 struct drm_fb_helper *fbdev; 174 175 struct msm_rd_state *rd; /* debugfs to dump all submits */ 176 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 177 struct msm_perf_state *perf; 178 179 /** 180 * List of all GEM objects (mainly for debugfs, protected by obj_lock 181 * (acquire before per GEM object lock) 182 */ 183 struct list_head objects; 184 struct mutex obj_lock; 185 186 /** 187 * LRUs of inactive GEM objects. Every bo is either in one of the 188 * inactive lists (depending on whether or not it is shrinkable) or 189 * gpu->active_list (for the gpu it is active on[1]), or transiently 190 * on a temporary list as the shrinker is running. 191 * 192 * Note that inactive_willneed also contains pinned and vmap'd bos, 193 * but the number of pinned-but-not-active objects is small (scanout 194 * buffers, ringbuffer, etc). 195 * 196 * These lists are protected by mm_lock (which should be acquired 197 * before per GEM object lock). One should *not* hold mm_lock in 198 * get_pages()/vmap()/etc paths, as they can trigger the shrinker. 199 * 200 * [1] if someone ever added support for the old 2d cores, there could be 201 * more than one gpu object 202 */ 203 struct list_head inactive_willneed; /* inactive + potentially unpin/evictable */ 204 struct list_head inactive_dontneed; /* inactive + shrinkable */ 205 struct list_head inactive_unpinned; /* inactive + purged or unpinned */ 206 long shrinkable_count; /* write access under mm_lock */ 207 long evictable_count; /* write access under mm_lock */ 208 struct mutex mm_lock; 209 210 struct workqueue_struct *wq; 211 212 unsigned int num_planes; 213 struct drm_plane *planes[MAX_PLANES]; 214 215 unsigned int num_crtcs; 216 struct drm_crtc *crtcs[MAX_CRTCS]; 217 218 struct msm_drm_thread event_thread[MAX_CRTCS]; 219 220 unsigned int num_encoders; 221 struct drm_encoder *encoders[MAX_ENCODERS]; 222 223 unsigned int num_bridges; 224 struct drm_bridge *bridges[MAX_BRIDGES]; 225 226 unsigned int num_connectors; 227 struct drm_connector *connectors[MAX_CONNECTORS]; 228 229 /* Properties */ 230 struct drm_property *plane_property[PLANE_PROP_MAX_NUM]; 231 232 /* VRAM carveout, used when no IOMMU: */ 233 struct { 234 unsigned long size; 235 dma_addr_t paddr; 236 /* NOTE: mm managed at the page level, size is in # of pages 237 * and position mm_node->start is in # of pages: 238 */ 239 struct drm_mm mm; 240 spinlock_t lock; /* Protects drm_mm node allocation/removal */ 241 } vram; 242 243 struct notifier_block vmap_notifier; 244 struct shrinker shrinker; 245 246 struct drm_atomic_state *pm_state; 247 248 /* For hang detection, in ms */ 249 unsigned int hangcheck_period; 250 }; 251 252 struct msm_format { 253 uint32_t pixel_format; 254 }; 255 256 struct msm_pending_timer; 257 258 int msm_atomic_prepare_fb(struct drm_plane *plane, 259 struct drm_plane_state *new_state); 260 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer, 261 struct msm_kms *kms, int crtc_idx); 262 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer); 263 void msm_atomic_commit_tail(struct drm_atomic_state *state); 264 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 265 void msm_atomic_state_clear(struct drm_atomic_state *state); 266 void msm_atomic_state_free(struct drm_atomic_state *state); 267 268 int msm_crtc_enable_vblank(struct drm_crtc *crtc); 269 void msm_crtc_disable_vblank(struct drm_crtc *crtc); 270 271 int msm_gem_init_vma(struct msm_gem_address_space *aspace, 272 struct msm_gem_vma *vma, int npages, 273 u64 range_start, u64 range_end); 274 void msm_gem_purge_vma(struct msm_gem_address_space *aspace, 275 struct msm_gem_vma *vma); 276 void msm_gem_unmap_vma(struct msm_gem_address_space *aspace, 277 struct msm_gem_vma *vma); 278 int msm_gem_map_vma(struct msm_gem_address_space *aspace, 279 struct msm_gem_vma *vma, int prot, 280 struct sg_table *sgt, int npages); 281 void msm_gem_close_vma(struct msm_gem_address_space *aspace, 282 struct msm_gem_vma *vma); 283 284 285 struct msm_gem_address_space * 286 msm_gem_address_space_get(struct msm_gem_address_space *aspace); 287 288 void msm_gem_address_space_put(struct msm_gem_address_space *aspace); 289 290 struct msm_gem_address_space * 291 msm_gem_address_space_create(struct msm_mmu *mmu, const char *name, 292 u64 va_start, u64 size); 293 294 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 295 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 296 297 bool msm_use_mmu(struct drm_device *dev); 298 299 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 300 struct drm_file *file); 301 302 #ifdef CONFIG_DEBUG_FS 303 unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan); 304 #endif 305 306 void msm_gem_shrinker_init(struct drm_device *dev); 307 void msm_gem_shrinker_cleanup(struct drm_device *dev); 308 309 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 310 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map); 311 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map); 312 int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 313 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 314 struct dma_buf_attachment *attach, struct sg_table *sg); 315 int msm_gem_prime_pin(struct drm_gem_object *obj); 316 void msm_gem_prime_unpin(struct drm_gem_object *obj); 317 318 int msm_framebuffer_prepare(struct drm_framebuffer *fb, 319 struct msm_gem_address_space *aspace); 320 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, 321 struct msm_gem_address_space *aspace); 322 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, 323 struct msm_gem_address_space *aspace, int plane); 324 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 325 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 326 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 327 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 328 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 329 int w, int h, int p, uint32_t format); 330 331 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); 332 void msm_fbdev_free(struct drm_device *dev); 333 334 struct hdmi; 335 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 336 struct drm_encoder *encoder); 337 void __init msm_hdmi_register(void); 338 void __exit msm_hdmi_unregister(void); 339 340 struct msm_edp; 341 void __init msm_edp_register(void); 342 void __exit msm_edp_unregister(void); 343 int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev, 344 struct drm_encoder *encoder); 345 346 struct msm_dsi; 347 #ifdef CONFIG_DRM_MSM_DSI 348 void __init msm_dsi_register(void); 349 void __exit msm_dsi_unregister(void); 350 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 351 struct drm_encoder *encoder); 352 void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi); 353 354 #else 355 static inline void __init msm_dsi_register(void) 356 { 357 } 358 static inline void __exit msm_dsi_unregister(void) 359 { 360 } 361 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 362 struct drm_device *dev, 363 struct drm_encoder *encoder) 364 { 365 return -EINVAL; 366 } 367 static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) 368 { 369 } 370 371 #endif 372 373 #ifdef CONFIG_DRM_MSM_DP 374 int __init msm_dp_register(void); 375 void __exit msm_dp_unregister(void); 376 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, 377 struct drm_encoder *encoder); 378 int msm_dp_display_enable(struct msm_dp *dp, struct drm_encoder *encoder); 379 int msm_dp_display_disable(struct msm_dp *dp, struct drm_encoder *encoder); 380 int msm_dp_display_pre_disable(struct msm_dp *dp, struct drm_encoder *encoder); 381 void msm_dp_display_mode_set(struct msm_dp *dp, struct drm_encoder *encoder, 382 struct drm_display_mode *mode, 383 struct drm_display_mode *adjusted_mode); 384 void msm_dp_irq_postinstall(struct msm_dp *dp_display); 385 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); 386 387 void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor); 388 389 #else 390 static inline int __init msm_dp_register(void) 391 { 392 return -EINVAL; 393 } 394 static inline void __exit msm_dp_unregister(void) 395 { 396 } 397 static inline int msm_dp_modeset_init(struct msm_dp *dp_display, 398 struct drm_device *dev, 399 struct drm_encoder *encoder) 400 { 401 return -EINVAL; 402 } 403 static inline int msm_dp_display_enable(struct msm_dp *dp, 404 struct drm_encoder *encoder) 405 { 406 return -EINVAL; 407 } 408 static inline int msm_dp_display_disable(struct msm_dp *dp, 409 struct drm_encoder *encoder) 410 { 411 return -EINVAL; 412 } 413 static inline int msm_dp_display_pre_disable(struct msm_dp *dp, 414 struct drm_encoder *encoder) 415 { 416 return -EINVAL; 417 } 418 static inline void msm_dp_display_mode_set(struct msm_dp *dp, 419 struct drm_encoder *encoder, 420 struct drm_display_mode *mode, 421 struct drm_display_mode *adjusted_mode) 422 { 423 } 424 425 static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display) 426 { 427 } 428 429 static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) 430 { 431 } 432 433 static inline void msm_dp_debugfs_init(struct msm_dp *dp_display, 434 struct drm_minor *minor) 435 { 436 } 437 438 #endif 439 440 void __init msm_mdp_register(void); 441 void __exit msm_mdp_unregister(void); 442 void __init msm_dpu_register(void); 443 void __exit msm_dpu_unregister(void); 444 445 #ifdef CONFIG_DEBUG_FS 446 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 447 int msm_debugfs_late_init(struct drm_device *dev); 448 int msm_rd_debugfs_init(struct drm_minor *minor); 449 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 450 __printf(3, 4) 451 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 452 const char *fmt, ...); 453 int msm_perf_debugfs_init(struct drm_minor *minor); 454 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 455 #else 456 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 457 __printf(3, 4) 458 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, 459 struct msm_gem_submit *submit, 460 const char *fmt, ...) {} 461 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 462 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 463 #endif 464 465 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 466 467 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 468 const char *name); 469 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, 470 const char *dbgname); 471 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, 472 const char *dbgname, phys_addr_t *size); 473 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name, 474 const char *dbgname); 475 void msm_writel(u32 data, void __iomem *addr); 476 u32 msm_readl(const void __iomem *addr); 477 void msm_rmw(void __iomem *addr, u32 mask, u32 or); 478 479 struct msm_gpu_submitqueue; 480 int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx); 481 struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx, 482 u32 id); 483 int msm_submitqueue_create(struct drm_device *drm, 484 struct msm_file_private *ctx, 485 u32 prio, u32 flags, u32 *id); 486 int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx, 487 struct drm_msm_submitqueue_query *args); 488 int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id); 489 void msm_submitqueue_close(struct msm_file_private *ctx); 490 491 void msm_submitqueue_destroy(struct kref *kref); 492 493 static inline void __msm_file_private_destroy(struct kref *kref) 494 { 495 struct msm_file_private *ctx = container_of(kref, 496 struct msm_file_private, ref); 497 498 msm_gem_address_space_put(ctx->aspace); 499 kfree(ctx); 500 } 501 502 static inline void msm_file_private_put(struct msm_file_private *ctx) 503 { 504 kref_put(&ctx->ref, __msm_file_private_destroy); 505 } 506 507 static inline struct msm_file_private *msm_file_private_get( 508 struct msm_file_private *ctx) 509 { 510 kref_get(&ctx->ref); 511 return ctx; 512 } 513 514 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 515 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 516 517 static inline int align_pitch(int width, int bpp) 518 { 519 int bytespp = (bpp + 7) / 8; 520 /* adreno needs pitch aligned to 32 pixels: */ 521 return bytespp * ALIGN(width, 32); 522 } 523 524 /* for the generated headers: */ 525 #define INVALID_IDX(idx) ({BUG(); 0;}) 526 #define fui(x) ({BUG(); 0;}) 527 #define _mesa_float_to_half(x) ({BUG(); 0;}) 528 529 530 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 531 532 /* for conditionally setting boolean flag(s): */ 533 #define COND(bool, val) ((bool) ? (val) : 0) 534 535 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 536 { 537 ktime_t now = ktime_get(); 538 unsigned long remaining_jiffies; 539 540 if (ktime_compare(*timeout, now) < 0) { 541 remaining_jiffies = 0; 542 } else { 543 ktime_t rem = ktime_sub(*timeout, now); 544 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ); 545 } 546 547 return remaining_jiffies; 548 } 549 550 #endif /* __MSM_DRV_H__ */ 551