1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #ifndef __MSM_DRV_H__ 9 #define __MSM_DRV_H__ 10 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/cpufreq.h> 14 #include <linux/module.h> 15 #include <linux/component.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/slab.h> 20 #include <linux/list.h> 21 #include <linux/iommu.h> 22 #include <linux/types.h> 23 #include <linux/of_graph.h> 24 #include <linux/of_device.h> 25 #include <linux/sizes.h> 26 #include <linux/kthread.h> 27 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_plane_helper.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_fb_helper.h> 33 #include <drm/msm_drm.h> 34 #include <drm/drm_gem.h> 35 36 struct msm_kms; 37 struct msm_gpu; 38 struct msm_mmu; 39 struct msm_mdss; 40 struct msm_rd_state; 41 struct msm_perf_state; 42 struct msm_gem_submit; 43 struct msm_fence_context; 44 struct msm_gem_address_space; 45 struct msm_gem_vma; 46 47 #define MAX_CRTCS 8 48 #define MAX_PLANES 20 49 #define MAX_ENCODERS 8 50 #define MAX_BRIDGES 8 51 #define MAX_CONNECTORS 8 52 53 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 54 55 struct msm_file_private { 56 rwlock_t queuelock; 57 struct list_head submitqueues; 58 int queueid; 59 struct msm_gem_address_space *aspace; 60 }; 61 62 enum msm_mdp_plane_property { 63 PLANE_PROP_ZPOS, 64 PLANE_PROP_ALPHA, 65 PLANE_PROP_PREMULTIPLIED, 66 PLANE_PROP_MAX_NUM 67 }; 68 69 #define MSM_GPU_MAX_RINGS 4 70 #define MAX_H_TILES_PER_DISPLAY 2 71 72 /** 73 * enum msm_display_caps - features/capabilities supported by displays 74 * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported 75 * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported 76 * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported 77 * @MSM_DISPLAY_CAP_EDID: EDID supported 78 */ 79 enum msm_display_caps { 80 MSM_DISPLAY_CAP_VID_MODE = BIT(0), 81 MSM_DISPLAY_CAP_CMD_MODE = BIT(1), 82 MSM_DISPLAY_CAP_HOT_PLUG = BIT(2), 83 MSM_DISPLAY_CAP_EDID = BIT(3), 84 }; 85 86 /** 87 * enum msm_event_wait - type of HW events to wait for 88 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW 89 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel 90 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters) 91 */ 92 enum msm_event_wait { 93 MSM_ENC_COMMIT_DONE = 0, 94 MSM_ENC_TX_COMPLETE, 95 MSM_ENC_VBLANK, 96 }; 97 98 /** 99 * struct msm_display_topology - defines a display topology pipeline 100 * @num_lm: number of layer mixers used 101 * @num_enc: number of compression encoder blocks used 102 * @num_intf: number of interfaces the panel is mounted on 103 */ 104 struct msm_display_topology { 105 u32 num_lm; 106 u32 num_enc; 107 u32 num_intf; 108 }; 109 110 /** 111 * struct msm_display_info - defines display properties 112 * @intf_type: DRM_MODE_ENCODER_ type 113 * @capabilities: Bitmask of display flags 114 * @num_of_h_tiles: Number of horizontal tiles in case of split interface 115 * @h_tile_instance: Controller instance used per tile. Number of elements is 116 * based on num_of_h_tiles 117 * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is 118 * used instead of panel TE in cmd mode panels 119 */ 120 struct msm_display_info { 121 int intf_type; 122 uint32_t capabilities; 123 uint32_t num_of_h_tiles; 124 uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; 125 bool is_te_using_watchdog_timer; 126 }; 127 128 /* Commit/Event thread specific structure */ 129 struct msm_drm_thread { 130 struct drm_device *dev; 131 struct task_struct *thread; 132 unsigned int crtc_id; 133 struct kthread_worker worker; 134 }; 135 136 struct msm_drm_private { 137 138 struct drm_device *dev; 139 140 struct msm_kms *kms; 141 142 /* subordinate devices, if present: */ 143 struct platform_device *gpu_pdev; 144 145 /* top level MDSS wrapper device (for MDP5/DPU only) */ 146 struct msm_mdss *mdss; 147 148 /* possibly this should be in the kms component, but it is 149 * shared by both mdp4 and mdp5.. 150 */ 151 struct hdmi *hdmi; 152 153 /* eDP is for mdp5 only, but kms has not been created 154 * when edp_bind() and edp_init() are called. Here is the only 155 * place to keep the edp instance. 156 */ 157 struct msm_edp *edp; 158 159 /* DSI is shared by mdp4 and mdp5 */ 160 struct msm_dsi *dsi[2]; 161 162 /* when we have more than one 'msm_gpu' these need to be an array: */ 163 struct msm_gpu *gpu; 164 struct msm_file_private *lastctx; 165 /* gpu is only set on open(), but we need this info earlier */ 166 bool is_a2xx; 167 168 struct drm_fb_helper *fbdev; 169 170 struct msm_rd_state *rd; /* debugfs to dump all submits */ 171 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 172 struct msm_perf_state *perf; 173 174 /* list of GEM objects: */ 175 struct list_head inactive_list; 176 177 /* worker for delayed free of objects: */ 178 struct work_struct free_work; 179 struct llist_head free_list; 180 181 struct workqueue_struct *wq; 182 183 unsigned int num_planes; 184 struct drm_plane *planes[MAX_PLANES]; 185 186 unsigned int num_crtcs; 187 struct drm_crtc *crtcs[MAX_CRTCS]; 188 189 struct msm_drm_thread event_thread[MAX_CRTCS]; 190 191 unsigned int num_encoders; 192 struct drm_encoder *encoders[MAX_ENCODERS]; 193 194 unsigned int num_bridges; 195 struct drm_bridge *bridges[MAX_BRIDGES]; 196 197 unsigned int num_connectors; 198 struct drm_connector *connectors[MAX_CONNECTORS]; 199 200 /* Properties */ 201 struct drm_property *plane_property[PLANE_PROP_MAX_NUM]; 202 203 /* VRAM carveout, used when no IOMMU: */ 204 struct { 205 unsigned long size; 206 dma_addr_t paddr; 207 /* NOTE: mm managed at the page level, size is in # of pages 208 * and position mm_node->start is in # of pages: 209 */ 210 struct drm_mm mm; 211 spinlock_t lock; /* Protects drm_mm node allocation/removal */ 212 } vram; 213 214 struct notifier_block vmap_notifier; 215 struct shrinker shrinker; 216 217 struct drm_atomic_state *pm_state; 218 }; 219 220 struct msm_format { 221 uint32_t pixel_format; 222 }; 223 224 struct msm_pending_timer; 225 226 int msm_atomic_prepare_fb(struct drm_plane *plane, 227 struct drm_plane_state *new_state); 228 void msm_atomic_init_pending_timer(struct msm_pending_timer *timer, 229 struct msm_kms *kms, int crtc_idx); 230 void msm_atomic_commit_tail(struct drm_atomic_state *state); 231 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 232 void msm_atomic_state_clear(struct drm_atomic_state *state); 233 void msm_atomic_state_free(struct drm_atomic_state *state); 234 235 int msm_crtc_enable_vblank(struct drm_crtc *crtc); 236 void msm_crtc_disable_vblank(struct drm_crtc *crtc); 237 238 int msm_gem_init_vma(struct msm_gem_address_space *aspace, 239 struct msm_gem_vma *vma, int npages); 240 void msm_gem_purge_vma(struct msm_gem_address_space *aspace, 241 struct msm_gem_vma *vma); 242 void msm_gem_unmap_vma(struct msm_gem_address_space *aspace, 243 struct msm_gem_vma *vma); 244 int msm_gem_map_vma(struct msm_gem_address_space *aspace, 245 struct msm_gem_vma *vma, int prot, 246 struct sg_table *sgt, int npages); 247 void msm_gem_close_vma(struct msm_gem_address_space *aspace, 248 struct msm_gem_vma *vma); 249 250 void msm_gem_address_space_put(struct msm_gem_address_space *aspace); 251 252 struct msm_gem_address_space * 253 msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain, 254 const char *name); 255 256 struct msm_gem_address_space * 257 msm_gem_address_space_create_a2xx(struct device *dev, struct msm_gpu *gpu, 258 const char *name, uint64_t va_start, uint64_t va_end); 259 260 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 261 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 262 263 bool msm_use_mmu(struct drm_device *dev); 264 265 void msm_gem_submit_free(struct msm_gem_submit *submit); 266 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 267 struct drm_file *file); 268 269 void msm_gem_shrinker_init(struct drm_device *dev); 270 void msm_gem_shrinker_cleanup(struct drm_device *dev); 271 272 int msm_gem_mmap_obj(struct drm_gem_object *obj, 273 struct vm_area_struct *vma); 274 int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma); 275 vm_fault_t msm_gem_fault(struct vm_fault *vmf); 276 uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); 277 int msm_gem_get_iova(struct drm_gem_object *obj, 278 struct msm_gem_address_space *aspace, uint64_t *iova); 279 int msm_gem_get_and_pin_iova(struct drm_gem_object *obj, 280 struct msm_gem_address_space *aspace, uint64_t *iova); 281 uint64_t msm_gem_iova(struct drm_gem_object *obj, 282 struct msm_gem_address_space *aspace); 283 void msm_gem_unpin_iova(struct drm_gem_object *obj, 284 struct msm_gem_address_space *aspace); 285 struct page **msm_gem_get_pages(struct drm_gem_object *obj); 286 void msm_gem_put_pages(struct drm_gem_object *obj); 287 int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, 288 struct drm_mode_create_dumb *args); 289 int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, 290 uint32_t handle, uint64_t *offset); 291 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 292 void *msm_gem_prime_vmap(struct drm_gem_object *obj); 293 void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 294 int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 295 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 296 struct dma_buf_attachment *attach, struct sg_table *sg); 297 int msm_gem_prime_pin(struct drm_gem_object *obj); 298 void msm_gem_prime_unpin(struct drm_gem_object *obj); 299 void *msm_gem_get_vaddr(struct drm_gem_object *obj); 300 void *msm_gem_get_vaddr_active(struct drm_gem_object *obj); 301 void msm_gem_put_vaddr(struct drm_gem_object *obj); 302 int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv); 303 int msm_gem_sync_object(struct drm_gem_object *obj, 304 struct msm_fence_context *fctx, bool exclusive); 305 void msm_gem_move_to_active(struct drm_gem_object *obj, 306 struct msm_gpu *gpu, bool exclusive, struct dma_fence *fence); 307 void msm_gem_move_to_inactive(struct drm_gem_object *obj); 308 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout); 309 int msm_gem_cpu_fini(struct drm_gem_object *obj); 310 void msm_gem_free_object(struct drm_gem_object *obj); 311 int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, 312 uint32_t size, uint32_t flags, uint32_t *handle, char *name); 313 struct drm_gem_object *msm_gem_new(struct drm_device *dev, 314 uint32_t size, uint32_t flags); 315 struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev, 316 uint32_t size, uint32_t flags); 317 void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size, 318 uint32_t flags, struct msm_gem_address_space *aspace, 319 struct drm_gem_object **bo, uint64_t *iova); 320 void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size, 321 uint32_t flags, struct msm_gem_address_space *aspace, 322 struct drm_gem_object **bo, uint64_t *iova); 323 void msm_gem_kernel_put(struct drm_gem_object *bo, 324 struct msm_gem_address_space *aspace, bool locked); 325 struct drm_gem_object *msm_gem_import(struct drm_device *dev, 326 struct dma_buf *dmabuf, struct sg_table *sgt); 327 void msm_gem_free_work(struct work_struct *work); 328 329 __printf(2, 3) 330 void msm_gem_object_set_name(struct drm_gem_object *bo, const char *fmt, ...); 331 332 int msm_framebuffer_prepare(struct drm_framebuffer *fb, 333 struct msm_gem_address_space *aspace); 334 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, 335 struct msm_gem_address_space *aspace); 336 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, 337 struct msm_gem_address_space *aspace, int plane); 338 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 339 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 340 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 341 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 342 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 343 int w, int h, int p, uint32_t format); 344 345 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); 346 void msm_fbdev_free(struct drm_device *dev); 347 348 struct hdmi; 349 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 350 struct drm_encoder *encoder); 351 void __init msm_hdmi_register(void); 352 void __exit msm_hdmi_unregister(void); 353 354 struct msm_edp; 355 void __init msm_edp_register(void); 356 void __exit msm_edp_unregister(void); 357 int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev, 358 struct drm_encoder *encoder); 359 360 struct msm_dsi; 361 #ifdef CONFIG_DRM_MSM_DSI 362 void __init msm_dsi_register(void); 363 void __exit msm_dsi_unregister(void); 364 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 365 struct drm_encoder *encoder); 366 #else 367 static inline void __init msm_dsi_register(void) 368 { 369 } 370 static inline void __exit msm_dsi_unregister(void) 371 { 372 } 373 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 374 struct drm_device *dev, 375 struct drm_encoder *encoder) 376 { 377 return -EINVAL; 378 } 379 #endif 380 381 void __init msm_mdp_register(void); 382 void __exit msm_mdp_unregister(void); 383 void __init msm_dpu_register(void); 384 void __exit msm_dpu_unregister(void); 385 386 #ifdef CONFIG_DEBUG_FS 387 void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); 388 void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); 389 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 390 int msm_debugfs_late_init(struct drm_device *dev); 391 int msm_rd_debugfs_init(struct drm_minor *minor); 392 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 393 __printf(3, 4) 394 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 395 const char *fmt, ...); 396 int msm_perf_debugfs_init(struct drm_minor *minor); 397 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 398 #else 399 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 400 __printf(3, 4) 401 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 402 const char *fmt, ...) {} 403 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 404 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 405 #endif 406 407 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 408 409 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 410 const char *name); 411 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, 412 const char *dbgname); 413 void msm_writel(u32 data, void __iomem *addr); 414 u32 msm_readl(const void __iomem *addr); 415 416 struct msm_gpu_submitqueue; 417 int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx); 418 struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx, 419 u32 id); 420 int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, 421 u32 prio, u32 flags, u32 *id); 422 int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx, 423 struct drm_msm_submitqueue_query *args); 424 int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id); 425 void msm_submitqueue_close(struct msm_file_private *ctx); 426 427 void msm_submitqueue_destroy(struct kref *kref); 428 429 430 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 431 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 432 433 static inline int align_pitch(int width, int bpp) 434 { 435 int bytespp = (bpp + 7) / 8; 436 /* adreno needs pitch aligned to 32 pixels: */ 437 return bytespp * ALIGN(width, 32); 438 } 439 440 /* for the generated headers: */ 441 #define INVALID_IDX(idx) ({BUG(); 0;}) 442 #define fui(x) ({BUG(); 0;}) 443 #define util_float_to_half(x) ({BUG(); 0;}) 444 445 446 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 447 448 /* for conditionally setting boolean flag(s): */ 449 #define COND(bool, val) ((bool) ? (val) : 0) 450 451 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 452 { 453 ktime_t now = ktime_get(); 454 unsigned long remaining_jiffies; 455 456 if (ktime_compare(*timeout, now) < 0) { 457 remaining_jiffies = 0; 458 } else { 459 ktime_t rem = ktime_sub(*timeout, now); 460 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ); 461 } 462 463 return remaining_jiffies; 464 } 465 466 #endif /* __MSM_DRV_H__ */ 467