1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __MSM_DRV_H__ 19 #define __MSM_DRV_H__ 20 21 #include <linux/kernel.h> 22 #include <linux/clk.h> 23 #include <linux/cpufreq.h> 24 #include <linux/module.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/slab.h> 29 #include <linux/list.h> 30 #include <linux/iommu.h> 31 #include <linux/types.h> 32 #include <asm/sizes.h> 33 34 35 #if defined(CONFIG_COMPILE_TEST) && !defined(CONFIG_ARCH_MSM) 36 /* stubs we need for compile-test: */ 37 static inline struct device *msm_iommu_get_ctx(const char *ctx_name) 38 { 39 return NULL; 40 } 41 #endif 42 43 #ifndef CONFIG_OF 44 #include <mach/board.h> 45 #include <mach/socinfo.h> 46 #include <mach/iommu_domains.h> 47 #endif 48 49 #include <drm/drmP.h> 50 #include <drm/drm_crtc_helper.h> 51 #include <drm/drm_fb_helper.h> 52 #include <drm/msm_drm.h> 53 54 struct msm_kms; 55 struct msm_gpu; 56 struct msm_mmu; 57 58 #define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */ 59 60 struct msm_file_private { 61 /* currently we don't do anything useful with this.. but when 62 * per-context address spaces are supported we'd keep track of 63 * the context's page-tables here. 64 */ 65 int dummy; 66 }; 67 68 struct msm_drm_private { 69 70 struct msm_kms *kms; 71 72 /* when we have more than one 'msm_gpu' these need to be an array: */ 73 struct msm_gpu *gpu; 74 struct msm_file_private *lastctx; 75 76 struct drm_fb_helper *fbdev; 77 78 uint32_t next_fence, completed_fence; 79 wait_queue_head_t fence_event; 80 81 /* list of GEM objects: */ 82 struct list_head inactive_list; 83 84 struct workqueue_struct *wq; 85 86 /* callbacks deferred until bo is inactive: */ 87 struct list_head fence_cbs; 88 89 /* registered MMUs: */ 90 unsigned int num_mmus; 91 struct msm_mmu *mmus[NUM_DOMAINS]; 92 93 unsigned int num_planes; 94 struct drm_plane *planes[8]; 95 96 unsigned int num_crtcs; 97 struct drm_crtc *crtcs[8]; 98 99 unsigned int num_encoders; 100 struct drm_encoder *encoders[8]; 101 102 unsigned int num_bridges; 103 struct drm_bridge *bridges[8]; 104 105 unsigned int num_connectors; 106 struct drm_connector *connectors[8]; 107 108 /* VRAM carveout, used when no IOMMU: */ 109 struct { 110 unsigned long size; 111 dma_addr_t paddr; 112 /* NOTE: mm managed at the page level, size is in # of pages 113 * and position mm_node->start is in # of pages: 114 */ 115 struct drm_mm mm; 116 } vram; 117 }; 118 119 struct msm_format { 120 uint32_t pixel_format; 121 }; 122 123 /* callback from wq once fence has passed: */ 124 struct msm_fence_cb { 125 struct work_struct work; 126 uint32_t fence; 127 void (*func)(struct msm_fence_cb *cb); 128 }; 129 130 void __msm_fence_worker(struct work_struct *work); 131 132 #define INIT_FENCE_CB(_cb, _func) do { \ 133 INIT_WORK(&(_cb)->work, __msm_fence_worker); \ 134 (_cb)->func = _func; \ 135 } while (0) 136 137 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 138 139 int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence, 140 struct timespec *timeout); 141 void msm_update_fence(struct drm_device *dev, uint32_t fence); 142 143 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 144 struct drm_file *file); 145 146 int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma); 147 int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 148 uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); 149 int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id, 150 uint32_t *iova); 151 int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova); 152 struct page **msm_gem_get_pages(struct drm_gem_object *obj); 153 void msm_gem_put_pages(struct drm_gem_object *obj); 154 void msm_gem_put_iova(struct drm_gem_object *obj, int id); 155 int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, 156 struct drm_mode_create_dumb *args); 157 int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, 158 uint32_t handle, uint64_t *offset); 159 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 160 void *msm_gem_prime_vmap(struct drm_gem_object *obj); 161 void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 162 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 163 size_t size, struct sg_table *sg); 164 int msm_gem_prime_pin(struct drm_gem_object *obj); 165 void msm_gem_prime_unpin(struct drm_gem_object *obj); 166 void *msm_gem_vaddr_locked(struct drm_gem_object *obj); 167 void *msm_gem_vaddr(struct drm_gem_object *obj); 168 int msm_gem_queue_inactive_cb(struct drm_gem_object *obj, 169 struct msm_fence_cb *cb); 170 void msm_gem_move_to_active(struct drm_gem_object *obj, 171 struct msm_gpu *gpu, bool write, uint32_t fence); 172 void msm_gem_move_to_inactive(struct drm_gem_object *obj); 173 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, 174 struct timespec *timeout); 175 int msm_gem_cpu_fini(struct drm_gem_object *obj); 176 void msm_gem_free_object(struct drm_gem_object *obj); 177 int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, 178 uint32_t size, uint32_t flags, uint32_t *handle); 179 struct drm_gem_object *msm_gem_new(struct drm_device *dev, 180 uint32_t size, uint32_t flags); 181 struct drm_gem_object *msm_gem_import(struct drm_device *dev, 182 uint32_t size, struct sg_table *sgt); 183 184 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 185 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 186 struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, 187 struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); 188 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 189 struct drm_file *file, struct drm_mode_fb_cmd2 *mode_cmd); 190 191 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); 192 193 struct hdmi; 194 struct hdmi *hdmi_init(struct drm_device *dev, struct drm_encoder *encoder); 195 irqreturn_t hdmi_irq(int irq, void *dev_id); 196 void __init hdmi_register(void); 197 void __exit hdmi_unregister(void); 198 199 #ifdef CONFIG_DEBUG_FS 200 void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); 201 void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); 202 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 203 #endif 204 205 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, 206 const char *dbgname); 207 void msm_writel(u32 data, void __iomem *addr); 208 u32 msm_readl(const void __iomem *addr); 209 210 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 211 #define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 212 213 static inline bool fence_completed(struct drm_device *dev, uint32_t fence) 214 { 215 struct msm_drm_private *priv = dev->dev_private; 216 return priv->completed_fence >= fence; 217 } 218 219 static inline int align_pitch(int width, int bpp) 220 { 221 int bytespp = (bpp + 7) / 8; 222 /* adreno needs pitch aligned to 32 pixels: */ 223 return bytespp * ALIGN(width, 32); 224 } 225 226 /* for the generated headers: */ 227 #define INVALID_IDX(idx) ({BUG(); 0;}) 228 #define fui(x) ({BUG(); 0;}) 229 #define util_float_to_half(x) ({BUG(); 0;}) 230 231 232 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 233 234 /* for conditionally setting boolean flag(s): */ 235 #define COND(bool, val) ((bool) ? (val) : 0) 236 237 238 #endif /* __MSM_DRV_H__ */ 239