1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __MSM_DRV_H__ 19 #define __MSM_DRV_H__ 20 21 #include <linux/kernel.h> 22 #include <linux/clk.h> 23 #include <linux/cpufreq.h> 24 #include <linux/module.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/slab.h> 29 #include <linux/list.h> 30 #include <linux/iommu.h> 31 #include <linux/types.h> 32 #include <asm/sizes.h> 33 34 #ifndef CONFIG_OF 35 #include <mach/board.h> 36 #include <mach/socinfo.h> 37 #include <mach/iommu_domains.h> 38 #endif 39 40 #include <drm/drmP.h> 41 #include <drm/drm_crtc_helper.h> 42 #include <drm/drm_fb_helper.h> 43 #include <drm/msm_drm.h> 44 45 struct msm_kms; 46 struct msm_gpu; 47 48 #define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */ 49 50 struct msm_file_private { 51 /* currently we don't do anything useful with this.. but when 52 * per-context address spaces are supported we'd keep track of 53 * the context's page-tables here. 54 */ 55 int dummy; 56 }; 57 58 struct msm_drm_private { 59 60 struct msm_kms *kms; 61 62 /* when we have more than one 'msm_gpu' these need to be an array: */ 63 struct msm_gpu *gpu; 64 struct msm_file_private *lastctx; 65 66 struct drm_fb_helper *fbdev; 67 68 uint32_t next_fence, completed_fence; 69 wait_queue_head_t fence_event; 70 71 /* list of GEM objects: */ 72 struct list_head inactive_list; 73 74 struct workqueue_struct *wq; 75 76 /* callbacks deferred until bo is inactive: */ 77 struct list_head fence_cbs; 78 79 /* registered IOMMU domains: */ 80 unsigned int num_iommus; 81 struct iommu_domain *iommus[NUM_DOMAINS]; 82 83 unsigned int num_planes; 84 struct drm_plane *planes[8]; 85 86 unsigned int num_crtcs; 87 struct drm_crtc *crtcs[8]; 88 89 unsigned int num_encoders; 90 struct drm_encoder *encoders[8]; 91 92 unsigned int num_bridges; 93 struct drm_bridge *bridges[8]; 94 95 unsigned int num_connectors; 96 struct drm_connector *connectors[8]; 97 }; 98 99 struct msm_format { 100 uint32_t pixel_format; 101 }; 102 103 /* callback from wq once fence has passed: */ 104 struct msm_fence_cb { 105 struct work_struct work; 106 uint32_t fence; 107 void (*func)(struct msm_fence_cb *cb); 108 }; 109 110 void __msm_fence_worker(struct work_struct *work); 111 112 #define INIT_FENCE_CB(_cb, _func) do { \ 113 INIT_WORK(&(_cb)->work, __msm_fence_worker); \ 114 (_cb)->func = _func; \ 115 } while (0) 116 117 /* As there are different display controller blocks depending on the 118 * snapdragon version, the kms support is split out and the appropriate 119 * implementation is loaded at runtime. The kms module is responsible 120 * for constructing the appropriate planes/crtcs/encoders/connectors. 121 */ 122 struct msm_kms_funcs { 123 /* hw initialization: */ 124 int (*hw_init)(struct msm_kms *kms); 125 /* irq handling: */ 126 void (*irq_preinstall)(struct msm_kms *kms); 127 int (*irq_postinstall)(struct msm_kms *kms); 128 void (*irq_uninstall)(struct msm_kms *kms); 129 irqreturn_t (*irq)(struct msm_kms *kms); 130 int (*enable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc); 131 void (*disable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc); 132 /* misc: */ 133 const struct msm_format *(*get_format)(struct msm_kms *kms, uint32_t format); 134 long (*round_pixclk)(struct msm_kms *kms, unsigned long rate, 135 struct drm_encoder *encoder); 136 /* cleanup: */ 137 void (*preclose)(struct msm_kms *kms, struct drm_file *file); 138 void (*destroy)(struct msm_kms *kms); 139 }; 140 141 struct msm_kms { 142 const struct msm_kms_funcs *funcs; 143 }; 144 145 struct msm_kms *mdp4_kms_init(struct drm_device *dev); 146 147 int msm_register_iommu(struct drm_device *dev, struct iommu_domain *iommu); 148 int msm_iommu_attach(struct drm_device *dev, struct iommu_domain *iommu, 149 const char **names, int cnt); 150 151 int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence, 152 struct timespec *timeout); 153 void msm_update_fence(struct drm_device *dev, uint32_t fence); 154 155 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 156 struct drm_file *file); 157 158 int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma); 159 int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 160 uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); 161 int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id, 162 uint32_t *iova); 163 int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova); 164 struct page **msm_gem_get_pages(struct drm_gem_object *obj); 165 void msm_gem_put_pages(struct drm_gem_object *obj); 166 void msm_gem_put_iova(struct drm_gem_object *obj, int id); 167 int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, 168 struct drm_mode_create_dumb *args); 169 int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, 170 uint32_t handle, uint64_t *offset); 171 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 172 void *msm_gem_prime_vmap(struct drm_gem_object *obj); 173 void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 174 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 175 size_t size, struct sg_table *sg); 176 int msm_gem_prime_pin(struct drm_gem_object *obj); 177 void msm_gem_prime_unpin(struct drm_gem_object *obj); 178 void *msm_gem_vaddr_locked(struct drm_gem_object *obj); 179 void *msm_gem_vaddr(struct drm_gem_object *obj); 180 int msm_gem_queue_inactive_cb(struct drm_gem_object *obj, 181 struct msm_fence_cb *cb); 182 void msm_gem_move_to_active(struct drm_gem_object *obj, 183 struct msm_gpu *gpu, bool write, uint32_t fence); 184 void msm_gem_move_to_inactive(struct drm_gem_object *obj); 185 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, 186 struct timespec *timeout); 187 int msm_gem_cpu_fini(struct drm_gem_object *obj); 188 void msm_gem_free_object(struct drm_gem_object *obj); 189 int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, 190 uint32_t size, uint32_t flags, uint32_t *handle); 191 struct drm_gem_object *msm_gem_new(struct drm_device *dev, 192 uint32_t size, uint32_t flags); 193 struct drm_gem_object *msm_gem_import(struct drm_device *dev, 194 uint32_t size, struct sg_table *sgt); 195 196 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 197 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 198 struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, 199 struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); 200 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 201 struct drm_file *file, struct drm_mode_fb_cmd2 *mode_cmd); 202 203 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); 204 205 int hdmi_init(struct drm_device *dev, struct drm_encoder *encoder); 206 void __init hdmi_register(void); 207 void __exit hdmi_unregister(void); 208 209 #ifdef CONFIG_DEBUG_FS 210 void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); 211 void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); 212 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 213 #endif 214 215 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, 216 const char *dbgname); 217 void msm_writel(u32 data, void __iomem *addr); 218 u32 msm_readl(const void __iomem *addr); 219 220 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 221 #define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 222 223 static inline bool fence_completed(struct drm_device *dev, uint32_t fence) 224 { 225 struct msm_drm_private *priv = dev->dev_private; 226 return priv->completed_fence >= fence; 227 } 228 229 static inline int align_pitch(int width, int bpp) 230 { 231 int bytespp = (bpp + 7) / 8; 232 /* adreno needs pitch aligned to 32 pixels: */ 233 return bytespp * ALIGN(width, 32); 234 } 235 236 /* for the generated headers: */ 237 #define INVALID_IDX(idx) ({BUG(); 0;}) 238 #define fui(x) ({BUG(); 0;}) 239 #define util_float_to_half(x) ({BUG(); 0;}) 240 241 242 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 243 244 /* for conditionally setting boolean flag(s): */ 245 #define COND(bool, val) ((bool) ? (val) : 0) 246 247 248 #endif /* __MSM_DRV_H__ */ 249