1 /* 2 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef __MSM_DRV_H__ 20 #define __MSM_DRV_H__ 21 22 #include <linux/kernel.h> 23 #include <linux/clk.h> 24 #include <linux/cpufreq.h> 25 #include <linux/module.h> 26 #include <linux/component.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/slab.h> 31 #include <linux/list.h> 32 #include <linux/iommu.h> 33 #include <linux/types.h> 34 #include <linux/of_graph.h> 35 #include <linux/of_device.h> 36 #include <asm/sizes.h> 37 #include <linux/kthread.h> 38 39 #include <drm/drmP.h> 40 #include <drm/drm_atomic.h> 41 #include <drm/drm_atomic_helper.h> 42 #include <drm/drm_crtc_helper.h> 43 #include <drm/drm_plane_helper.h> 44 #include <drm/drm_fb_helper.h> 45 #include <drm/msm_drm.h> 46 #include <drm/drm_gem.h> 47 48 struct msm_kms; 49 struct msm_gpu; 50 struct msm_mmu; 51 struct msm_mdss; 52 struct msm_rd_state; 53 struct msm_perf_state; 54 struct msm_gem_submit; 55 struct msm_fence_context; 56 struct msm_gem_address_space; 57 struct msm_gem_vma; 58 59 #define MAX_CRTCS 8 60 #define MAX_PLANES 20 61 #define MAX_ENCODERS 8 62 #define MAX_BRIDGES 8 63 #define MAX_CONNECTORS 8 64 65 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 66 67 struct msm_file_private { 68 rwlock_t queuelock; 69 struct list_head submitqueues; 70 int queueid; 71 }; 72 73 enum msm_mdp_plane_property { 74 PLANE_PROP_ZPOS, 75 PLANE_PROP_ALPHA, 76 PLANE_PROP_PREMULTIPLIED, 77 PLANE_PROP_MAX_NUM 78 }; 79 80 struct msm_vblank_ctrl { 81 struct kthread_work work; 82 struct list_head event_list; 83 spinlock_t lock; 84 }; 85 86 #define MSM_GPU_MAX_RINGS 4 87 #define MAX_H_TILES_PER_DISPLAY 2 88 89 /** 90 * enum msm_display_caps - features/capabilities supported by displays 91 * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported 92 * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported 93 * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported 94 * @MSM_DISPLAY_CAP_EDID: EDID supported 95 */ 96 enum msm_display_caps { 97 MSM_DISPLAY_CAP_VID_MODE = BIT(0), 98 MSM_DISPLAY_CAP_CMD_MODE = BIT(1), 99 MSM_DISPLAY_CAP_HOT_PLUG = BIT(2), 100 MSM_DISPLAY_CAP_EDID = BIT(3), 101 }; 102 103 /** 104 * enum msm_event_wait - type of HW events to wait for 105 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW 106 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel 107 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters) 108 */ 109 enum msm_event_wait { 110 MSM_ENC_COMMIT_DONE = 0, 111 MSM_ENC_TX_COMPLETE, 112 MSM_ENC_VBLANK, 113 }; 114 115 /** 116 * struct msm_display_topology - defines a display topology pipeline 117 * @num_lm: number of layer mixers used 118 * @num_enc: number of compression encoder blocks used 119 * @num_intf: number of interfaces the panel is mounted on 120 */ 121 struct msm_display_topology { 122 u32 num_lm; 123 u32 num_enc; 124 u32 num_intf; 125 }; 126 127 /** 128 * struct msm_display_info - defines display properties 129 * @intf_type: DRM_MODE_CONNECTOR_ display type 130 * @capabilities: Bitmask of display flags 131 * @num_of_h_tiles: Number of horizontal tiles in case of split interface 132 * @h_tile_instance: Controller instance used per tile. Number of elements is 133 * based on num_of_h_tiles 134 * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is 135 * used instead of panel TE in cmd mode panels 136 */ 137 struct msm_display_info { 138 int intf_type; 139 uint32_t capabilities; 140 uint32_t num_of_h_tiles; 141 uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; 142 bool is_te_using_watchdog_timer; 143 }; 144 145 /* Commit/Event thread specific structure */ 146 struct msm_drm_thread { 147 struct drm_device *dev; 148 struct task_struct *thread; 149 unsigned int crtc_id; 150 struct kthread_worker worker; 151 }; 152 153 struct msm_drm_private { 154 155 struct drm_device *dev; 156 157 struct msm_kms *kms; 158 159 /* subordinate devices, if present: */ 160 struct platform_device *gpu_pdev; 161 162 /* top level MDSS wrapper device (for MDP5/DPU only) */ 163 struct msm_mdss *mdss; 164 165 /* possibly this should be in the kms component, but it is 166 * shared by both mdp4 and mdp5.. 167 */ 168 struct hdmi *hdmi; 169 170 /* eDP is for mdp5 only, but kms has not been created 171 * when edp_bind() and edp_init() are called. Here is the only 172 * place to keep the edp instance. 173 */ 174 struct msm_edp *edp; 175 176 /* DSI is shared by mdp4 and mdp5 */ 177 struct msm_dsi *dsi[2]; 178 179 /* when we have more than one 'msm_gpu' these need to be an array: */ 180 struct msm_gpu *gpu; 181 struct msm_file_private *lastctx; 182 /* gpu is only set on open(), but we need this info earlier */ 183 bool is_a2xx; 184 185 struct drm_fb_helper *fbdev; 186 187 struct msm_rd_state *rd; /* debugfs to dump all submits */ 188 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 189 struct msm_perf_state *perf; 190 191 /* list of GEM objects: */ 192 struct list_head inactive_list; 193 194 struct workqueue_struct *wq; 195 196 unsigned int num_planes; 197 struct drm_plane *planes[MAX_PLANES]; 198 199 unsigned int num_crtcs; 200 struct drm_crtc *crtcs[MAX_CRTCS]; 201 202 struct msm_drm_thread disp_thread[MAX_CRTCS]; 203 struct msm_drm_thread event_thread[MAX_CRTCS]; 204 205 unsigned int num_encoders; 206 struct drm_encoder *encoders[MAX_ENCODERS]; 207 208 unsigned int num_bridges; 209 struct drm_bridge *bridges[MAX_BRIDGES]; 210 211 unsigned int num_connectors; 212 struct drm_connector *connectors[MAX_CONNECTORS]; 213 214 /* Properties */ 215 struct drm_property *plane_property[PLANE_PROP_MAX_NUM]; 216 217 /* VRAM carveout, used when no IOMMU: */ 218 struct { 219 unsigned long size; 220 dma_addr_t paddr; 221 /* NOTE: mm managed at the page level, size is in # of pages 222 * and position mm_node->start is in # of pages: 223 */ 224 struct drm_mm mm; 225 spinlock_t lock; /* Protects drm_mm node allocation/removal */ 226 } vram; 227 228 struct notifier_block vmap_notifier; 229 struct shrinker shrinker; 230 231 struct msm_vblank_ctrl vblank_ctrl; 232 struct drm_atomic_state *pm_state; 233 }; 234 235 struct msm_format { 236 uint32_t pixel_format; 237 }; 238 239 int msm_atomic_prepare_fb(struct drm_plane *plane, 240 struct drm_plane_state *new_state); 241 void msm_atomic_commit_tail(struct drm_atomic_state *state); 242 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 243 void msm_atomic_state_clear(struct drm_atomic_state *state); 244 void msm_atomic_state_free(struct drm_atomic_state *state); 245 246 int msm_gem_init_vma(struct msm_gem_address_space *aspace, 247 struct msm_gem_vma *vma, int npages); 248 void msm_gem_purge_vma(struct msm_gem_address_space *aspace, 249 struct msm_gem_vma *vma); 250 void msm_gem_unmap_vma(struct msm_gem_address_space *aspace, 251 struct msm_gem_vma *vma); 252 int msm_gem_map_vma(struct msm_gem_address_space *aspace, 253 struct msm_gem_vma *vma, int prot, 254 struct sg_table *sgt, int npages); 255 void msm_gem_close_vma(struct msm_gem_address_space *aspace, 256 struct msm_gem_vma *vma); 257 258 void msm_gem_address_space_put(struct msm_gem_address_space *aspace); 259 260 struct msm_gem_address_space * 261 msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain, 262 const char *name); 263 264 struct msm_gem_address_space * 265 msm_gem_address_space_create_a2xx(struct device *dev, struct msm_gpu *gpu, 266 const char *name, uint64_t va_start, uint64_t va_end); 267 268 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 269 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 270 271 bool msm_use_mmu(struct drm_device *dev); 272 273 void msm_gem_submit_free(struct msm_gem_submit *submit); 274 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 275 struct drm_file *file); 276 277 void msm_gem_shrinker_init(struct drm_device *dev); 278 void msm_gem_shrinker_cleanup(struct drm_device *dev); 279 280 int msm_gem_mmap_obj(struct drm_gem_object *obj, 281 struct vm_area_struct *vma); 282 int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma); 283 vm_fault_t msm_gem_fault(struct vm_fault *vmf); 284 uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); 285 int msm_gem_get_iova(struct drm_gem_object *obj, 286 struct msm_gem_address_space *aspace, uint64_t *iova); 287 int msm_gem_get_and_pin_iova(struct drm_gem_object *obj, 288 struct msm_gem_address_space *aspace, uint64_t *iova); 289 uint64_t msm_gem_iova(struct drm_gem_object *obj, 290 struct msm_gem_address_space *aspace); 291 void msm_gem_unpin_iova(struct drm_gem_object *obj, 292 struct msm_gem_address_space *aspace); 293 struct page **msm_gem_get_pages(struct drm_gem_object *obj); 294 void msm_gem_put_pages(struct drm_gem_object *obj); 295 int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, 296 struct drm_mode_create_dumb *args); 297 int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, 298 uint32_t handle, uint64_t *offset); 299 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 300 void *msm_gem_prime_vmap(struct drm_gem_object *obj); 301 void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 302 int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 303 struct reservation_object *msm_gem_prime_res_obj(struct drm_gem_object *obj); 304 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 305 struct dma_buf_attachment *attach, struct sg_table *sg); 306 int msm_gem_prime_pin(struct drm_gem_object *obj); 307 void msm_gem_prime_unpin(struct drm_gem_object *obj); 308 void *msm_gem_get_vaddr(struct drm_gem_object *obj); 309 void *msm_gem_get_vaddr_active(struct drm_gem_object *obj); 310 void msm_gem_put_vaddr(struct drm_gem_object *obj); 311 int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv); 312 int msm_gem_sync_object(struct drm_gem_object *obj, 313 struct msm_fence_context *fctx, bool exclusive); 314 void msm_gem_move_to_active(struct drm_gem_object *obj, 315 struct msm_gpu *gpu, bool exclusive, struct dma_fence *fence); 316 void msm_gem_move_to_inactive(struct drm_gem_object *obj); 317 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout); 318 int msm_gem_cpu_fini(struct drm_gem_object *obj); 319 void msm_gem_free_object(struct drm_gem_object *obj); 320 int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, 321 uint32_t size, uint32_t flags, uint32_t *handle, char *name); 322 struct drm_gem_object *msm_gem_new(struct drm_device *dev, 323 uint32_t size, uint32_t flags); 324 struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev, 325 uint32_t size, uint32_t flags); 326 void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size, 327 uint32_t flags, struct msm_gem_address_space *aspace, 328 struct drm_gem_object **bo, uint64_t *iova); 329 void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size, 330 uint32_t flags, struct msm_gem_address_space *aspace, 331 struct drm_gem_object **bo, uint64_t *iova); 332 void msm_gem_kernel_put(struct drm_gem_object *bo, 333 struct msm_gem_address_space *aspace, bool locked); 334 struct drm_gem_object *msm_gem_import(struct drm_device *dev, 335 struct dma_buf *dmabuf, struct sg_table *sgt); 336 337 __printf(2, 3) 338 void msm_gem_object_set_name(struct drm_gem_object *bo, const char *fmt, ...); 339 340 int msm_framebuffer_prepare(struct drm_framebuffer *fb, 341 struct msm_gem_address_space *aspace); 342 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, 343 struct msm_gem_address_space *aspace); 344 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, 345 struct msm_gem_address_space *aspace, int plane); 346 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 347 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 348 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 349 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 350 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 351 int w, int h, int p, uint32_t format); 352 353 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); 354 void msm_fbdev_free(struct drm_device *dev); 355 356 struct hdmi; 357 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 358 struct drm_encoder *encoder); 359 void __init msm_hdmi_register(void); 360 void __exit msm_hdmi_unregister(void); 361 362 struct msm_edp; 363 void __init msm_edp_register(void); 364 void __exit msm_edp_unregister(void); 365 int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev, 366 struct drm_encoder *encoder); 367 368 struct msm_dsi; 369 #ifdef CONFIG_DRM_MSM_DSI 370 void __init msm_dsi_register(void); 371 void __exit msm_dsi_unregister(void); 372 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 373 struct drm_encoder *encoder); 374 #else 375 static inline void __init msm_dsi_register(void) 376 { 377 } 378 static inline void __exit msm_dsi_unregister(void) 379 { 380 } 381 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 382 struct drm_device *dev, 383 struct drm_encoder *encoder) 384 { 385 return -EINVAL; 386 } 387 #endif 388 389 void __init msm_mdp_register(void); 390 void __exit msm_mdp_unregister(void); 391 void __init msm_dpu_register(void); 392 void __exit msm_dpu_unregister(void); 393 394 #ifdef CONFIG_DEBUG_FS 395 void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); 396 void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); 397 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 398 int msm_debugfs_late_init(struct drm_device *dev); 399 int msm_rd_debugfs_init(struct drm_minor *minor); 400 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 401 __printf(3, 4) 402 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 403 const char *fmt, ...); 404 int msm_perf_debugfs_init(struct drm_minor *minor); 405 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 406 #else 407 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 408 __printf(3, 4) 409 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 410 const char *fmt, ...) {} 411 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 412 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 413 #endif 414 415 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 416 int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk); 417 418 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 419 const char *name); 420 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, 421 const char *dbgname); 422 void msm_writel(u32 data, void __iomem *addr); 423 u32 msm_readl(const void __iomem *addr); 424 425 struct msm_gpu_submitqueue; 426 int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx); 427 struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx, 428 u32 id); 429 int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, 430 u32 prio, u32 flags, u32 *id); 431 int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id); 432 void msm_submitqueue_close(struct msm_file_private *ctx); 433 434 void msm_submitqueue_destroy(struct kref *kref); 435 436 437 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 438 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 439 440 static inline int align_pitch(int width, int bpp) 441 { 442 int bytespp = (bpp + 7) / 8; 443 /* adreno needs pitch aligned to 32 pixels: */ 444 return bytespp * ALIGN(width, 32); 445 } 446 447 /* for the generated headers: */ 448 #define INVALID_IDX(idx) ({BUG(); 0;}) 449 #define fui(x) ({BUG(); 0;}) 450 #define util_float_to_half(x) ({BUG(); 0;}) 451 452 453 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 454 455 /* for conditionally setting boolean flag(s): */ 456 #define COND(bool, val) ((bool) ? (val) : 0) 457 458 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 459 { 460 ktime_t now = ktime_get(); 461 unsigned long remaining_jiffies; 462 463 if (ktime_compare(*timeout, now) < 0) { 464 remaining_jiffies = 0; 465 } else { 466 ktime_t rem = ktime_sub(*timeout, now); 467 struct timespec ts = ktime_to_timespec(rem); 468 remaining_jiffies = timespec_to_jiffies(&ts); 469 } 470 471 return remaining_jiffies; 472 } 473 474 #endif /* __MSM_DRV_H__ */ 475