1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #ifndef __MSM_DRV_H__ 9 #define __MSM_DRV_H__ 10 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/cpufreq.h> 14 #include <linux/devfreq.h> 15 #include <linux/module.h> 16 #include <linux/component.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/slab.h> 21 #include <linux/list.h> 22 #include <linux/iommu.h> 23 #include <linux/types.h> 24 #include <linux/of_graph.h> 25 #include <linux/of_device.h> 26 #include <linux/sizes.h> 27 #include <linux/kthread.h> 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/display/drm_dsc.h> 33 #include <drm/msm_drm.h> 34 #include <drm/drm_gem.h> 35 36 #ifdef CONFIG_FAULT_INJECTION 37 extern struct fault_attr fail_gem_alloc; 38 extern struct fault_attr fail_gem_iova; 39 #else 40 # define should_fail(attr, size) 0 41 #endif 42 43 struct msm_kms; 44 struct msm_gpu; 45 struct msm_mmu; 46 struct msm_mdss; 47 struct msm_rd_state; 48 struct msm_perf_state; 49 struct msm_gem_submit; 50 struct msm_fence_context; 51 struct msm_gem_address_space; 52 struct msm_gem_vma; 53 struct msm_disp_state; 54 55 #define MAX_CRTCS 8 56 #define MAX_BRIDGES 8 57 58 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 59 60 enum msm_dp_controller { 61 MSM_DP_CONTROLLER_0, 62 MSM_DP_CONTROLLER_1, 63 MSM_DP_CONTROLLER_2, 64 MSM_DP_CONTROLLER_3, 65 MSM_DP_CONTROLLER_COUNT, 66 }; 67 68 enum msm_dsi_controller { 69 MSM_DSI_CONTROLLER_0, 70 MSM_DSI_CONTROLLER_1, 71 MSM_DSI_CONTROLLER_COUNT, 72 }; 73 74 #define MSM_GPU_MAX_RINGS 4 75 #define MAX_H_TILES_PER_DISPLAY 2 76 77 /** 78 * struct msm_display_topology - defines a display topology pipeline 79 * @num_lm: number of layer mixers used 80 * @num_intf: number of interfaces the panel is mounted on 81 * @num_dspp: number of dspp blocks used 82 * @num_dsc: number of Display Stream Compression (DSC) blocks used 83 */ 84 struct msm_display_topology { 85 u32 num_lm; 86 u32 num_intf; 87 u32 num_dspp; 88 u32 num_dsc; 89 }; 90 91 /* Commit/Event thread specific structure */ 92 struct msm_drm_thread { 93 struct drm_device *dev; 94 struct kthread_worker *worker; 95 }; 96 97 struct msm_drm_private { 98 99 struct drm_device *dev; 100 101 struct msm_kms *kms; 102 int (*kms_init)(struct drm_device *dev); 103 104 /* subordinate devices, if present: */ 105 struct platform_device *gpu_pdev; 106 107 /* possibly this should be in the kms component, but it is 108 * shared by both mdp4 and mdp5.. 109 */ 110 struct hdmi *hdmi; 111 112 /* DSI is shared by mdp4 and mdp5 */ 113 struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT]; 114 115 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT]; 116 117 /* when we have more than one 'msm_gpu' these need to be an array: */ 118 struct msm_gpu *gpu; 119 120 /* gpu is only set on open(), but we need this info earlier */ 121 bool is_a2xx; 122 bool has_cached_coherent; 123 124 struct msm_rd_state *rd; /* debugfs to dump all submits */ 125 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 126 struct msm_perf_state *perf; 127 128 /** 129 * List of all GEM objects (mainly for debugfs, protected by obj_lock 130 * (acquire before per GEM object lock) 131 */ 132 struct list_head objects; 133 struct mutex obj_lock; 134 135 /** 136 * lru: 137 * 138 * The various LRU's that a GEM object is in at various stages of 139 * it's lifetime. Objects start out in the unbacked LRU. When 140 * pinned (for scannout or permanently mapped GPU buffers, like 141 * ringbuffer, memptr, fw, etc) it moves to the pinned LRU. When 142 * unpinned, it moves into willneed or dontneed LRU depending on 143 * madvise state. When backing pages are evicted (willneed) or 144 * purged (dontneed) it moves back into the unbacked LRU. 145 * 146 * The dontneed LRU is considered by the shrinker for objects 147 * that are candidate for purging, and the willneed LRU is 148 * considered for objects that could be evicted. 149 */ 150 struct { 151 /** 152 * unbacked: 153 * 154 * The LRU for GEM objects without backing pages allocated. 155 * This mostly exists so that objects are always is one 156 * LRU. 157 */ 158 struct drm_gem_lru unbacked; 159 160 /** 161 * pinned: 162 * 163 * The LRU for pinned GEM objects 164 */ 165 struct drm_gem_lru pinned; 166 167 /** 168 * willneed: 169 * 170 * The LRU for unpinned GEM objects which are in madvise 171 * WILLNEED state (ie. can be evicted) 172 */ 173 struct drm_gem_lru willneed; 174 175 /** 176 * dontneed: 177 * 178 * The LRU for unpinned GEM objects which are in madvise 179 * DONTNEED state (ie. can be purged) 180 */ 181 struct drm_gem_lru dontneed; 182 183 /** 184 * lock: 185 * 186 * Protects manipulation of all of the LRUs. 187 */ 188 struct mutex lock; 189 } lru; 190 191 struct workqueue_struct *wq; 192 193 unsigned int num_crtcs; 194 195 struct msm_drm_thread event_thread[MAX_CRTCS]; 196 197 unsigned int num_bridges; 198 struct drm_bridge *bridges[MAX_BRIDGES]; 199 200 /* VRAM carveout, used when no IOMMU: */ 201 struct { 202 unsigned long size; 203 dma_addr_t paddr; 204 /* NOTE: mm managed at the page level, size is in # of pages 205 * and position mm_node->start is in # of pages: 206 */ 207 struct drm_mm mm; 208 spinlock_t lock; /* Protects drm_mm node allocation/removal */ 209 } vram; 210 211 struct notifier_block vmap_notifier; 212 struct shrinker shrinker; 213 214 struct drm_atomic_state *pm_state; 215 216 /** 217 * hangcheck_period: For hang detection, in ms 218 * 219 * Note that in practice, a submit/job will get at least two hangcheck 220 * periods, due to checking for progress being implemented as simply 221 * "have the CP position registers changed since last time?" 222 */ 223 unsigned int hangcheck_period; 224 225 /** gpu_devfreq_config: Devfreq tuning config for the GPU. */ 226 struct devfreq_simple_ondemand_data gpu_devfreq_config; 227 228 /** 229 * gpu_clamp_to_idle: Enable clamping to idle freq when inactive 230 */ 231 bool gpu_clamp_to_idle; 232 233 /** 234 * disable_err_irq: 235 * 236 * Disable handling of GPU hw error interrupts, to force fallback to 237 * sw hangcheck timer. Written (via debugfs) by igt tests to test 238 * the sw hangcheck mechanism. 239 */ 240 bool disable_err_irq; 241 }; 242 243 struct msm_format { 244 uint32_t pixel_format; 245 }; 246 247 struct msm_pending_timer; 248 249 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer, 250 struct msm_kms *kms, int crtc_idx); 251 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer); 252 void msm_atomic_commit_tail(struct drm_atomic_state *state); 253 int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); 254 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 255 void msm_atomic_state_clear(struct drm_atomic_state *state); 256 void msm_atomic_state_free(struct drm_atomic_state *state); 257 258 int msm_crtc_enable_vblank(struct drm_crtc *crtc); 259 void msm_crtc_disable_vblank(struct drm_crtc *crtc); 260 261 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 262 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 263 264 struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev); 265 bool msm_use_mmu(struct drm_device *dev); 266 267 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 268 struct drm_file *file); 269 270 #ifdef CONFIG_DEBUG_FS 271 unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan); 272 #endif 273 274 void msm_gem_shrinker_init(struct drm_device *dev); 275 void msm_gem_shrinker_cleanup(struct drm_device *dev); 276 277 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 278 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map); 279 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map); 280 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 281 struct dma_buf_attachment *attach, struct sg_table *sg); 282 int msm_gem_prime_pin(struct drm_gem_object *obj); 283 void msm_gem_prime_unpin(struct drm_gem_object *obj); 284 285 int msm_framebuffer_prepare(struct drm_framebuffer *fb, 286 struct msm_gem_address_space *aspace, bool needs_dirtyfb); 287 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, 288 struct msm_gem_address_space *aspace, bool needed_dirtyfb); 289 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, 290 struct msm_gem_address_space *aspace, int plane); 291 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 292 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 293 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 294 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 295 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 296 int w, int h, int p, uint32_t format); 297 298 #ifdef CONFIG_DRM_FBDEV_EMULATION 299 void msm_fbdev_setup(struct drm_device *dev); 300 #else 301 static inline void msm_fbdev_setup(struct drm_device *dev) 302 { 303 } 304 #endif 305 306 struct hdmi; 307 #ifdef CONFIG_DRM_MSM_HDMI 308 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 309 struct drm_encoder *encoder); 310 void __init msm_hdmi_register(void); 311 void __exit msm_hdmi_unregister(void); 312 #else 313 static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 314 struct drm_encoder *encoder) 315 { 316 return -EINVAL; 317 } 318 static inline void __init msm_hdmi_register(void) {} 319 static inline void __exit msm_hdmi_unregister(void) {} 320 #endif 321 322 struct msm_dsi; 323 #ifdef CONFIG_DRM_MSM_DSI 324 int dsi_dev_attach(struct platform_device *pdev); 325 void dsi_dev_detach(struct platform_device *pdev); 326 void __init msm_dsi_register(void); 327 void __exit msm_dsi_unregister(void); 328 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 329 struct drm_encoder *encoder); 330 void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi); 331 bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi); 332 bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); 333 bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi); 334 struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi); 335 #else 336 static inline void __init msm_dsi_register(void) 337 { 338 } 339 static inline void __exit msm_dsi_unregister(void) 340 { 341 } 342 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 343 struct drm_device *dev, 344 struct drm_encoder *encoder) 345 { 346 return -EINVAL; 347 } 348 static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) 349 { 350 } 351 static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi) 352 { 353 return false; 354 } 355 static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi) 356 { 357 return false; 358 } 359 static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi) 360 { 361 return false; 362 } 363 364 static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi) 365 { 366 return NULL; 367 } 368 #endif 369 370 #ifdef CONFIG_DRM_MSM_DP 371 int __init msm_dp_register(void); 372 void __exit msm_dp_unregister(void); 373 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, 374 struct drm_encoder *encoder); 375 void msm_dp_irq_postinstall(struct msm_dp *dp_display); 376 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); 377 378 void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor); 379 bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); 380 381 #else 382 static inline int __init msm_dp_register(void) 383 { 384 return -EINVAL; 385 } 386 static inline void __exit msm_dp_unregister(void) 387 { 388 } 389 static inline int msm_dp_modeset_init(struct msm_dp *dp_display, 390 struct drm_device *dev, 391 struct drm_encoder *encoder) 392 { 393 return -EINVAL; 394 } 395 396 static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display) 397 { 398 } 399 400 static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) 401 { 402 } 403 404 static inline void msm_dp_debugfs_init(struct msm_dp *dp_display, 405 struct drm_minor *minor) 406 { 407 } 408 409 static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) 410 { 411 return false; 412 } 413 414 #endif 415 416 #ifdef CONFIG_DRM_MSM_MDP4 417 void msm_mdp4_register(void); 418 void msm_mdp4_unregister(void); 419 #else 420 static inline void msm_mdp4_register(void) {} 421 static inline void msm_mdp4_unregister(void) {} 422 #endif 423 424 #ifdef CONFIG_DRM_MSM_MDP5 425 void msm_mdp_register(void); 426 void msm_mdp_unregister(void); 427 #else 428 static inline void msm_mdp_register(void) {} 429 static inline void msm_mdp_unregister(void) {} 430 #endif 431 432 #ifdef CONFIG_DRM_MSM_DPU 433 void msm_dpu_register(void); 434 void msm_dpu_unregister(void); 435 #else 436 static inline void msm_dpu_register(void) {} 437 static inline void msm_dpu_unregister(void) {} 438 #endif 439 440 #ifdef CONFIG_DRM_MSM_MDSS 441 void msm_mdss_register(void); 442 void msm_mdss_unregister(void); 443 #else 444 static inline void msm_mdss_register(void) {} 445 static inline void msm_mdss_unregister(void) {} 446 #endif 447 448 #ifdef CONFIG_DEBUG_FS 449 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 450 int msm_debugfs_late_init(struct drm_device *dev); 451 int msm_rd_debugfs_init(struct drm_minor *minor); 452 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 453 __printf(3, 4) 454 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 455 const char *fmt, ...); 456 int msm_perf_debugfs_init(struct drm_minor *minor); 457 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 458 #else 459 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 460 __printf(3, 4) 461 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, 462 struct msm_gem_submit *submit, 463 const char *fmt, ...) {} 464 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 465 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 466 #endif 467 468 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 469 470 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 471 const char *name); 472 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name); 473 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, 474 phys_addr_t *size); 475 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name); 476 477 struct icc_path *msm_icc_get(struct device *dev, const char *name); 478 479 #define msm_writel(data, addr) writel((data), (addr)) 480 #define msm_readl(addr) readl((addr)) 481 482 static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or) 483 { 484 u32 val = msm_readl(addr); 485 486 val &= ~mask; 487 msm_writel(val | or, addr); 488 } 489 490 /** 491 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work 492 * 493 * @timer: hrtimer to control when the kthread work is triggered 494 * @work: the kthread work 495 * @worker: the kthread worker the work will be scheduled on 496 */ 497 struct msm_hrtimer_work { 498 struct hrtimer timer; 499 struct kthread_work work; 500 struct kthread_worker *worker; 501 }; 502 503 void msm_hrtimer_queue_work(struct msm_hrtimer_work *work, 504 ktime_t wakeup_time, 505 enum hrtimer_mode mode); 506 void msm_hrtimer_work_init(struct msm_hrtimer_work *work, 507 struct kthread_worker *worker, 508 kthread_work_func_t fn, 509 clockid_t clock_id, 510 enum hrtimer_mode mode); 511 512 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 513 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 514 515 static inline int align_pitch(int width, int bpp) 516 { 517 int bytespp = (bpp + 7) / 8; 518 /* adreno needs pitch aligned to 32 pixels: */ 519 return bytespp * ALIGN(width, 32); 520 } 521 522 /* for the generated headers: */ 523 #define INVALID_IDX(idx) ({BUG(); 0;}) 524 #define fui(x) ({BUG(); 0;}) 525 #define _mesa_float_to_half(x) ({BUG(); 0;}) 526 527 528 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 529 530 /* for conditionally setting boolean flag(s): */ 531 #define COND(bool, val) ((bool) ? (val) : 0) 532 533 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 534 { 535 ktime_t now = ktime_get(); 536 s64 remaining_jiffies; 537 538 if (ktime_compare(*timeout, now) < 0) { 539 remaining_jiffies = 0; 540 } else { 541 ktime_t rem = ktime_sub(*timeout, now); 542 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ); 543 } 544 545 return clamp(remaining_jiffies, 1LL, (s64)INT_MAX); 546 } 547 548 /* Driver helpers */ 549 550 extern const struct component_master_ops msm_drm_ops; 551 552 int msm_pm_prepare(struct device *dev); 553 void msm_pm_complete(struct device *dev); 554 555 int msm_drv_probe(struct device *dev, 556 int (*kms_init)(struct drm_device *dev)); 557 void msm_drv_shutdown(struct platform_device *pdev); 558 559 560 #endif /* __MSM_DRV_H__ */ 561