1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/dma-mapping.h> 9 #include <linux/kthread.h> 10 #include <linux/sched/mm.h> 11 #include <linux/uaccess.h> 12 #include <uapi/linux/sched/types.h> 13 14 #include <drm/drm_bridge.h> 15 #include <drm/drm_drv.h> 16 #include <drm/drm_file.h> 17 #include <drm/drm_ioctl.h> 18 #include <drm/drm_prime.h> 19 #include <drm/drm_of.h> 20 #include <drm/drm_vblank.h> 21 22 #include "disp/msm_disp_snapshot.h" 23 #include "msm_drv.h" 24 #include "msm_debugfs.h" 25 #include "msm_fence.h" 26 #include "msm_gem.h" 27 #include "msm_gpu.h" 28 #include "msm_kms.h" 29 #include "adreno/adreno_gpu.h" 30 31 /* 32 * MSM driver version: 33 * - 1.0.0 - initial interface 34 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers 35 * - 1.2.0 - adds explicit fence support for submit ioctl 36 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW + 37 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for 38 * MSM_GEM_INFO ioctl. 39 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get 40 * GEM object's debug name 41 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl 42 * - 1.6.0 - Syncobj support 43 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count 44 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx) 45 * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN 46 */ 47 #define MSM_VERSION_MAJOR 1 48 #define MSM_VERSION_MINOR 9 49 #define MSM_VERSION_PATCHLEVEL 0 50 51 static const struct drm_mode_config_funcs mode_config_funcs = { 52 .fb_create = msm_framebuffer_create, 53 .output_poll_changed = drm_fb_helper_output_poll_changed, 54 .atomic_check = drm_atomic_helper_check, 55 .atomic_commit = drm_atomic_helper_commit, 56 }; 57 58 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = { 59 .atomic_commit_tail = msm_atomic_commit_tail, 60 }; 61 62 #ifdef CONFIG_DRM_FBDEV_EMULATION 63 static bool fbdev = true; 64 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer"); 65 module_param(fbdev, bool, 0600); 66 #endif 67 68 static char *vram = "16m"; 69 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)"); 70 module_param(vram, charp, 0); 71 72 bool dumpstate; 73 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors"); 74 module_param(dumpstate, bool, 0600); 75 76 static bool modeset = true; 77 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)"); 78 module_param(modeset, bool, 0600); 79 80 static irqreturn_t msm_irq(int irq, void *arg) 81 { 82 struct drm_device *dev = arg; 83 struct msm_drm_private *priv = dev->dev_private; 84 struct msm_kms *kms = priv->kms; 85 86 BUG_ON(!kms); 87 88 return kms->funcs->irq(kms); 89 } 90 91 static void msm_irq_preinstall(struct drm_device *dev) 92 { 93 struct msm_drm_private *priv = dev->dev_private; 94 struct msm_kms *kms = priv->kms; 95 96 BUG_ON(!kms); 97 98 kms->funcs->irq_preinstall(kms); 99 } 100 101 static int msm_irq_postinstall(struct drm_device *dev) 102 { 103 struct msm_drm_private *priv = dev->dev_private; 104 struct msm_kms *kms = priv->kms; 105 106 BUG_ON(!kms); 107 108 if (kms->funcs->irq_postinstall) 109 return kms->funcs->irq_postinstall(kms); 110 111 return 0; 112 } 113 114 static int msm_irq_install(struct drm_device *dev, unsigned int irq) 115 { 116 struct msm_drm_private *priv = dev->dev_private; 117 struct msm_kms *kms = priv->kms; 118 int ret; 119 120 if (irq == IRQ_NOTCONNECTED) 121 return -ENOTCONN; 122 123 msm_irq_preinstall(dev); 124 125 ret = request_irq(irq, msm_irq, 0, dev->driver->name, dev); 126 if (ret) 127 return ret; 128 129 kms->irq_requested = true; 130 131 ret = msm_irq_postinstall(dev); 132 if (ret) { 133 free_irq(irq, dev); 134 return ret; 135 } 136 137 return 0; 138 } 139 140 static void msm_irq_uninstall(struct drm_device *dev) 141 { 142 struct msm_drm_private *priv = dev->dev_private; 143 struct msm_kms *kms = priv->kms; 144 145 kms->funcs->irq_uninstall(kms); 146 if (kms->irq_requested) 147 free_irq(kms->irq, dev); 148 } 149 150 struct msm_vblank_work { 151 struct work_struct work; 152 int crtc_id; 153 bool enable; 154 struct msm_drm_private *priv; 155 }; 156 157 static void vblank_ctrl_worker(struct work_struct *work) 158 { 159 struct msm_vblank_work *vbl_work = container_of(work, 160 struct msm_vblank_work, work); 161 struct msm_drm_private *priv = vbl_work->priv; 162 struct msm_kms *kms = priv->kms; 163 164 if (vbl_work->enable) 165 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]); 166 else 167 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]); 168 169 kfree(vbl_work); 170 } 171 172 static int vblank_ctrl_queue_work(struct msm_drm_private *priv, 173 int crtc_id, bool enable) 174 { 175 struct msm_vblank_work *vbl_work; 176 177 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC); 178 if (!vbl_work) 179 return -ENOMEM; 180 181 INIT_WORK(&vbl_work->work, vblank_ctrl_worker); 182 183 vbl_work->crtc_id = crtc_id; 184 vbl_work->enable = enable; 185 vbl_work->priv = priv; 186 187 queue_work(priv->wq, &vbl_work->work); 188 189 return 0; 190 } 191 192 static int msm_drm_uninit(struct device *dev) 193 { 194 struct platform_device *pdev = to_platform_device(dev); 195 struct msm_drm_private *priv = platform_get_drvdata(pdev); 196 struct drm_device *ddev = priv->dev; 197 struct msm_kms *kms = priv->kms; 198 int i; 199 200 /* 201 * Shutdown the hw if we're far enough along where things might be on. 202 * If we run this too early, we'll end up panicking in any variety of 203 * places. Since we don't register the drm device until late in 204 * msm_drm_init, drm_dev->registered is used as an indicator that the 205 * shutdown will be successful. 206 */ 207 if (ddev->registered) { 208 drm_dev_unregister(ddev); 209 drm_atomic_helper_shutdown(ddev); 210 } 211 212 /* We must cancel and cleanup any pending vblank enable/disable 213 * work before msm_irq_uninstall() to avoid work re-enabling an 214 * irq after uninstall has disabled it. 215 */ 216 217 flush_workqueue(priv->wq); 218 219 /* clean up event worker threads */ 220 for (i = 0; i < priv->num_crtcs; i++) { 221 if (priv->event_thread[i].worker) 222 kthread_destroy_worker(priv->event_thread[i].worker); 223 } 224 225 msm_gem_shrinker_cleanup(ddev); 226 227 drm_kms_helper_poll_fini(ddev); 228 229 msm_perf_debugfs_cleanup(priv); 230 msm_rd_debugfs_cleanup(priv); 231 232 #ifdef CONFIG_DRM_FBDEV_EMULATION 233 if (fbdev && priv->fbdev) 234 msm_fbdev_free(ddev); 235 #endif 236 237 msm_disp_snapshot_destroy(ddev); 238 239 drm_mode_config_cleanup(ddev); 240 241 for (i = 0; i < priv->num_bridges; i++) 242 drm_bridge_remove(priv->bridges[i]); 243 244 pm_runtime_get_sync(dev); 245 msm_irq_uninstall(ddev); 246 pm_runtime_put_sync(dev); 247 248 if (kms && kms->funcs) 249 kms->funcs->destroy(kms); 250 251 if (priv->vram.paddr) { 252 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING; 253 drm_mm_takedown(&priv->vram.mm); 254 dma_free_attrs(dev, priv->vram.size, NULL, 255 priv->vram.paddr, attrs); 256 } 257 258 component_unbind_all(dev, ddev); 259 260 ddev->dev_private = NULL; 261 drm_dev_put(ddev); 262 263 destroy_workqueue(priv->wq); 264 265 return 0; 266 } 267 268 #include <linux/of_address.h> 269 270 bool msm_use_mmu(struct drm_device *dev) 271 { 272 struct msm_drm_private *priv = dev->dev_private; 273 274 /* a2xx comes with its own MMU */ 275 return priv->is_a2xx || iommu_present(&platform_bus_type); 276 } 277 278 static int msm_init_vram(struct drm_device *dev) 279 { 280 struct msm_drm_private *priv = dev->dev_private; 281 struct device_node *node; 282 unsigned long size = 0; 283 int ret = 0; 284 285 /* In the device-tree world, we could have a 'memory-region' 286 * phandle, which gives us a link to our "vram". Allocating 287 * is all nicely abstracted behind the dma api, but we need 288 * to know the entire size to allocate it all in one go. There 289 * are two cases: 290 * 1) device with no IOMMU, in which case we need exclusive 291 * access to a VRAM carveout big enough for all gpu 292 * buffers 293 * 2) device with IOMMU, but where the bootloader puts up 294 * a splash screen. In this case, the VRAM carveout 295 * need only be large enough for fbdev fb. But we need 296 * exclusive access to the buffer to avoid the kernel 297 * using those pages for other purposes (which appears 298 * as corruption on screen before we have a chance to 299 * load and do initial modeset) 300 */ 301 302 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0); 303 if (node) { 304 struct resource r; 305 ret = of_address_to_resource(node, 0, &r); 306 of_node_put(node); 307 if (ret) 308 return ret; 309 size = r.end - r.start + 1; 310 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start); 311 312 /* if we have no IOMMU, then we need to use carveout allocator. 313 * Grab the entire CMA chunk carved out in early startup in 314 * mach-msm: 315 */ 316 } else if (!msm_use_mmu(dev)) { 317 DRM_INFO("using %s VRAM carveout\n", vram); 318 size = memparse(vram, NULL); 319 } 320 321 if (size) { 322 unsigned long attrs = 0; 323 void *p; 324 325 priv->vram.size = size; 326 327 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1); 328 spin_lock_init(&priv->vram.lock); 329 330 attrs |= DMA_ATTR_NO_KERNEL_MAPPING; 331 attrs |= DMA_ATTR_WRITE_COMBINE; 332 333 /* note that for no-kernel-mapping, the vaddr returned 334 * is bogus, but non-null if allocation succeeded: 335 */ 336 p = dma_alloc_attrs(dev->dev, size, 337 &priv->vram.paddr, GFP_KERNEL, attrs); 338 if (!p) { 339 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n"); 340 priv->vram.paddr = 0; 341 return -ENOMEM; 342 } 343 344 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n", 345 (uint32_t)priv->vram.paddr, 346 (uint32_t)(priv->vram.paddr + size)); 347 } 348 349 return ret; 350 } 351 352 static int msm_drm_init(struct device *dev, const struct drm_driver *drv) 353 { 354 struct msm_drm_private *priv = dev_get_drvdata(dev); 355 struct drm_device *ddev; 356 struct msm_kms *kms; 357 int ret, i; 358 359 if (drm_firmware_drivers_only()) 360 return -ENODEV; 361 362 ddev = drm_dev_alloc(drv, dev); 363 if (IS_ERR(ddev)) { 364 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n"); 365 return PTR_ERR(ddev); 366 } 367 ddev->dev_private = priv; 368 priv->dev = ddev; 369 370 priv->wq = alloc_ordered_workqueue("msm", 0); 371 priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD; 372 373 INIT_LIST_HEAD(&priv->objects); 374 mutex_init(&priv->obj_lock); 375 376 INIT_LIST_HEAD(&priv->inactive_willneed); 377 INIT_LIST_HEAD(&priv->inactive_dontneed); 378 INIT_LIST_HEAD(&priv->inactive_unpinned); 379 mutex_init(&priv->mm_lock); 380 381 /* Teach lockdep about lock ordering wrt. shrinker: */ 382 fs_reclaim_acquire(GFP_KERNEL); 383 might_lock(&priv->mm_lock); 384 fs_reclaim_release(GFP_KERNEL); 385 386 drm_mode_config_init(ddev); 387 388 ret = msm_init_vram(ddev); 389 if (ret) 390 return ret; 391 392 /* Bind all our sub-components: */ 393 ret = component_bind_all(dev, ddev); 394 if (ret) 395 return ret; 396 397 dma_set_max_seg_size(dev, UINT_MAX); 398 399 msm_gem_shrinker_init(ddev); 400 401 if (priv->kms_init) { 402 ret = priv->kms_init(ddev); 403 if (ret) { 404 DRM_DEV_ERROR(dev, "failed to load kms\n"); 405 priv->kms = NULL; 406 goto err_msm_uninit; 407 } 408 kms = priv->kms; 409 } else { 410 /* valid only for the dummy headless case, where of_node=NULL */ 411 WARN_ON(dev->of_node); 412 kms = NULL; 413 } 414 415 /* Enable normalization of plane zpos */ 416 ddev->mode_config.normalize_zpos = true; 417 418 if (kms) { 419 kms->dev = ddev; 420 ret = kms->funcs->hw_init(kms); 421 if (ret) { 422 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret); 423 goto err_msm_uninit; 424 } 425 } 426 427 ddev->mode_config.funcs = &mode_config_funcs; 428 ddev->mode_config.helper_private = &mode_config_helper_funcs; 429 430 for (i = 0; i < priv->num_crtcs; i++) { 431 /* initialize event thread */ 432 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id; 433 priv->event_thread[i].dev = ddev; 434 priv->event_thread[i].worker = kthread_create_worker(0, 435 "crtc_event:%d", priv->event_thread[i].crtc_id); 436 if (IS_ERR(priv->event_thread[i].worker)) { 437 ret = PTR_ERR(priv->event_thread[i].worker); 438 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n"); 439 ret = PTR_ERR(priv->event_thread[i].worker); 440 goto err_msm_uninit; 441 } 442 443 sched_set_fifo(priv->event_thread[i].worker->task); 444 } 445 446 ret = drm_vblank_init(ddev, priv->num_crtcs); 447 if (ret < 0) { 448 DRM_DEV_ERROR(dev, "failed to initialize vblank\n"); 449 goto err_msm_uninit; 450 } 451 452 if (kms) { 453 pm_runtime_get_sync(dev); 454 ret = msm_irq_install(ddev, kms->irq); 455 pm_runtime_put_sync(dev); 456 if (ret < 0) { 457 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n"); 458 goto err_msm_uninit; 459 } 460 } 461 462 ret = drm_dev_register(ddev, 0); 463 if (ret) 464 goto err_msm_uninit; 465 466 if (kms) { 467 ret = msm_disp_snapshot_init(ddev); 468 if (ret) 469 DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret); 470 } 471 drm_mode_config_reset(ddev); 472 473 #ifdef CONFIG_DRM_FBDEV_EMULATION 474 if (kms && fbdev) 475 priv->fbdev = msm_fbdev_init(ddev); 476 #endif 477 478 ret = msm_debugfs_late_init(ddev); 479 if (ret) 480 goto err_msm_uninit; 481 482 drm_kms_helper_poll_init(ddev); 483 484 return 0; 485 486 err_msm_uninit: 487 msm_drm_uninit(dev); 488 return ret; 489 } 490 491 /* 492 * DRM operations: 493 */ 494 495 static void load_gpu(struct drm_device *dev) 496 { 497 static DEFINE_MUTEX(init_lock); 498 struct msm_drm_private *priv = dev->dev_private; 499 500 mutex_lock(&init_lock); 501 502 if (!priv->gpu) 503 priv->gpu = adreno_load_gpu(dev); 504 505 mutex_unlock(&init_lock); 506 } 507 508 static int context_init(struct drm_device *dev, struct drm_file *file) 509 { 510 static atomic_t ident = ATOMIC_INIT(0); 511 struct msm_drm_private *priv = dev->dev_private; 512 struct msm_file_private *ctx; 513 514 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 515 if (!ctx) 516 return -ENOMEM; 517 518 INIT_LIST_HEAD(&ctx->submitqueues); 519 rwlock_init(&ctx->queuelock); 520 521 kref_init(&ctx->ref); 522 msm_submitqueue_init(dev, ctx); 523 524 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current); 525 file->driver_priv = ctx; 526 527 ctx->seqno = atomic_inc_return(&ident); 528 529 return 0; 530 } 531 532 static int msm_open(struct drm_device *dev, struct drm_file *file) 533 { 534 /* For now, load gpu on open.. to avoid the requirement of having 535 * firmware in the initrd. 536 */ 537 load_gpu(dev); 538 539 return context_init(dev, file); 540 } 541 542 static void context_close(struct msm_file_private *ctx) 543 { 544 msm_submitqueue_close(ctx); 545 msm_file_private_put(ctx); 546 } 547 548 static void msm_postclose(struct drm_device *dev, struct drm_file *file) 549 { 550 struct msm_drm_private *priv = dev->dev_private; 551 struct msm_file_private *ctx = file->driver_priv; 552 553 /* 554 * It is not possible to set sysprof param to non-zero if gpu 555 * is not initialized: 556 */ 557 if (priv->gpu) 558 msm_file_private_set_sysprof(ctx, priv->gpu, 0); 559 560 context_close(ctx); 561 } 562 563 int msm_crtc_enable_vblank(struct drm_crtc *crtc) 564 { 565 struct drm_device *dev = crtc->dev; 566 unsigned int pipe = crtc->index; 567 struct msm_drm_private *priv = dev->dev_private; 568 struct msm_kms *kms = priv->kms; 569 if (!kms) 570 return -ENXIO; 571 drm_dbg_vbl(dev, "crtc=%u", pipe); 572 return vblank_ctrl_queue_work(priv, pipe, true); 573 } 574 575 void msm_crtc_disable_vblank(struct drm_crtc *crtc) 576 { 577 struct drm_device *dev = crtc->dev; 578 unsigned int pipe = crtc->index; 579 struct msm_drm_private *priv = dev->dev_private; 580 struct msm_kms *kms = priv->kms; 581 if (!kms) 582 return; 583 drm_dbg_vbl(dev, "crtc=%u", pipe); 584 vblank_ctrl_queue_work(priv, pipe, false); 585 } 586 587 /* 588 * DRM ioctls: 589 */ 590 591 static int msm_ioctl_get_param(struct drm_device *dev, void *data, 592 struct drm_file *file) 593 { 594 struct msm_drm_private *priv = dev->dev_private; 595 struct drm_msm_param *args = data; 596 struct msm_gpu *gpu; 597 598 /* for now, we just have 3d pipe.. eventually this would need to 599 * be more clever to dispatch to appropriate gpu module: 600 */ 601 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0)) 602 return -EINVAL; 603 604 gpu = priv->gpu; 605 606 if (!gpu) 607 return -ENXIO; 608 609 return gpu->funcs->get_param(gpu, file->driver_priv, 610 args->param, &args->value, &args->len); 611 } 612 613 static int msm_ioctl_set_param(struct drm_device *dev, void *data, 614 struct drm_file *file) 615 { 616 struct msm_drm_private *priv = dev->dev_private; 617 struct drm_msm_param *args = data; 618 struct msm_gpu *gpu; 619 620 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0)) 621 return -EINVAL; 622 623 gpu = priv->gpu; 624 625 if (!gpu) 626 return -ENXIO; 627 628 return gpu->funcs->set_param(gpu, file->driver_priv, 629 args->param, args->value, args->len); 630 } 631 632 static int msm_ioctl_gem_new(struct drm_device *dev, void *data, 633 struct drm_file *file) 634 { 635 struct drm_msm_gem_new *args = data; 636 637 if (args->flags & ~MSM_BO_FLAGS) { 638 DRM_ERROR("invalid flags: %08x\n", args->flags); 639 return -EINVAL; 640 } 641 642 return msm_gem_new_handle(dev, file, args->size, 643 args->flags, &args->handle, NULL); 644 } 645 646 static inline ktime_t to_ktime(struct drm_msm_timespec timeout) 647 { 648 return ktime_set(timeout.tv_sec, timeout.tv_nsec); 649 } 650 651 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, 652 struct drm_file *file) 653 { 654 struct drm_msm_gem_cpu_prep *args = data; 655 struct drm_gem_object *obj; 656 ktime_t timeout = to_ktime(args->timeout); 657 int ret; 658 659 if (args->op & ~MSM_PREP_FLAGS) { 660 DRM_ERROR("invalid op: %08x\n", args->op); 661 return -EINVAL; 662 } 663 664 obj = drm_gem_object_lookup(file, args->handle); 665 if (!obj) 666 return -ENOENT; 667 668 ret = msm_gem_cpu_prep(obj, args->op, &timeout); 669 670 drm_gem_object_put(obj); 671 672 return ret; 673 } 674 675 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, 676 struct drm_file *file) 677 { 678 struct drm_msm_gem_cpu_fini *args = data; 679 struct drm_gem_object *obj; 680 int ret; 681 682 obj = drm_gem_object_lookup(file, args->handle); 683 if (!obj) 684 return -ENOENT; 685 686 ret = msm_gem_cpu_fini(obj); 687 688 drm_gem_object_put(obj); 689 690 return ret; 691 } 692 693 static int msm_ioctl_gem_info_iova(struct drm_device *dev, 694 struct drm_file *file, struct drm_gem_object *obj, 695 uint64_t *iova) 696 { 697 struct msm_drm_private *priv = dev->dev_private; 698 struct msm_file_private *ctx = file->driver_priv; 699 700 if (!priv->gpu) 701 return -EINVAL; 702 703 /* 704 * Don't pin the memory here - just get an address so that userspace can 705 * be productive 706 */ 707 return msm_gem_get_iova(obj, ctx->aspace, iova); 708 } 709 710 static int msm_ioctl_gem_info_set_iova(struct drm_device *dev, 711 struct drm_file *file, struct drm_gem_object *obj, 712 uint64_t iova) 713 { 714 struct msm_drm_private *priv = dev->dev_private; 715 struct msm_file_private *ctx = file->driver_priv; 716 717 if (!priv->gpu) 718 return -EINVAL; 719 720 /* Only supported if per-process address space is supported: */ 721 if (priv->gpu->aspace == ctx->aspace) 722 return -EOPNOTSUPP; 723 724 return msm_gem_set_iova(obj, ctx->aspace, iova); 725 } 726 727 static int msm_ioctl_gem_info(struct drm_device *dev, void *data, 728 struct drm_file *file) 729 { 730 struct drm_msm_gem_info *args = data; 731 struct drm_gem_object *obj; 732 struct msm_gem_object *msm_obj; 733 int i, ret = 0; 734 735 if (args->pad) 736 return -EINVAL; 737 738 switch (args->info) { 739 case MSM_INFO_GET_OFFSET: 740 case MSM_INFO_GET_IOVA: 741 case MSM_INFO_SET_IOVA: 742 /* value returned as immediate, not pointer, so len==0: */ 743 if (args->len) 744 return -EINVAL; 745 break; 746 case MSM_INFO_SET_NAME: 747 case MSM_INFO_GET_NAME: 748 break; 749 default: 750 return -EINVAL; 751 } 752 753 obj = drm_gem_object_lookup(file, args->handle); 754 if (!obj) 755 return -ENOENT; 756 757 msm_obj = to_msm_bo(obj); 758 759 switch (args->info) { 760 case MSM_INFO_GET_OFFSET: 761 args->value = msm_gem_mmap_offset(obj); 762 break; 763 case MSM_INFO_GET_IOVA: 764 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value); 765 break; 766 case MSM_INFO_SET_IOVA: 767 ret = msm_ioctl_gem_info_set_iova(dev, file, obj, args->value); 768 break; 769 case MSM_INFO_SET_NAME: 770 /* length check should leave room for terminating null: */ 771 if (args->len >= sizeof(msm_obj->name)) { 772 ret = -EINVAL; 773 break; 774 } 775 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value), 776 args->len)) { 777 msm_obj->name[0] = '\0'; 778 ret = -EFAULT; 779 break; 780 } 781 msm_obj->name[args->len] = '\0'; 782 for (i = 0; i < args->len; i++) { 783 if (!isprint(msm_obj->name[i])) { 784 msm_obj->name[i] = '\0'; 785 break; 786 } 787 } 788 break; 789 case MSM_INFO_GET_NAME: 790 if (args->value && (args->len < strlen(msm_obj->name))) { 791 ret = -EINVAL; 792 break; 793 } 794 args->len = strlen(msm_obj->name); 795 if (args->value) { 796 if (copy_to_user(u64_to_user_ptr(args->value), 797 msm_obj->name, args->len)) 798 ret = -EFAULT; 799 } 800 break; 801 } 802 803 drm_gem_object_put(obj); 804 805 return ret; 806 } 807 808 static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id, 809 ktime_t timeout) 810 { 811 struct dma_fence *fence; 812 int ret; 813 814 if (fence_after(fence_id, queue->last_fence)) { 815 DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n", 816 fence_id, queue->last_fence); 817 return -EINVAL; 818 } 819 820 /* 821 * Map submitqueue scoped "seqno" (which is actually an idr key) 822 * back to underlying dma-fence 823 * 824 * The fence is removed from the fence_idr when the submit is 825 * retired, so if the fence is not found it means there is nothing 826 * to wait for 827 */ 828 ret = mutex_lock_interruptible(&queue->lock); 829 if (ret) 830 return ret; 831 fence = idr_find(&queue->fence_idr, fence_id); 832 if (fence) 833 fence = dma_fence_get_rcu(fence); 834 mutex_unlock(&queue->lock); 835 836 if (!fence) 837 return 0; 838 839 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout)); 840 if (ret == 0) { 841 ret = -ETIMEDOUT; 842 } else if (ret != -ERESTARTSYS) { 843 ret = 0; 844 } 845 846 dma_fence_put(fence); 847 848 return ret; 849 } 850 851 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, 852 struct drm_file *file) 853 { 854 struct msm_drm_private *priv = dev->dev_private; 855 struct drm_msm_wait_fence *args = data; 856 struct msm_gpu_submitqueue *queue; 857 int ret; 858 859 if (args->pad) { 860 DRM_ERROR("invalid pad: %08x\n", args->pad); 861 return -EINVAL; 862 } 863 864 if (!priv->gpu) 865 return 0; 866 867 queue = msm_submitqueue_get(file->driver_priv, args->queueid); 868 if (!queue) 869 return -ENOENT; 870 871 ret = wait_fence(queue, args->fence, to_ktime(args->timeout)); 872 873 msm_submitqueue_put(queue); 874 875 return ret; 876 } 877 878 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data, 879 struct drm_file *file) 880 { 881 struct drm_msm_gem_madvise *args = data; 882 struct drm_gem_object *obj; 883 int ret; 884 885 switch (args->madv) { 886 case MSM_MADV_DONTNEED: 887 case MSM_MADV_WILLNEED: 888 break; 889 default: 890 return -EINVAL; 891 } 892 893 obj = drm_gem_object_lookup(file, args->handle); 894 if (!obj) { 895 return -ENOENT; 896 } 897 898 ret = msm_gem_madvise(obj, args->madv); 899 if (ret >= 0) { 900 args->retained = ret; 901 ret = 0; 902 } 903 904 drm_gem_object_put(obj); 905 906 return ret; 907 } 908 909 910 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data, 911 struct drm_file *file) 912 { 913 struct drm_msm_submitqueue *args = data; 914 915 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS) 916 return -EINVAL; 917 918 return msm_submitqueue_create(dev, file->driver_priv, args->prio, 919 args->flags, &args->id); 920 } 921 922 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data, 923 struct drm_file *file) 924 { 925 return msm_submitqueue_query(dev, file->driver_priv, data); 926 } 927 928 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data, 929 struct drm_file *file) 930 { 931 u32 id = *(u32 *) data; 932 933 return msm_submitqueue_remove(file->driver_priv, id); 934 } 935 936 static const struct drm_ioctl_desc msm_ioctls[] = { 937 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW), 938 DRM_IOCTL_DEF_DRV(MSM_SET_PARAM, msm_ioctl_set_param, DRM_RENDER_ALLOW), 939 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW), 940 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW), 941 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW), 942 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW), 943 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW), 944 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW), 945 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW), 946 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW), 947 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW), 948 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW), 949 }; 950 951 DEFINE_DRM_GEM_FOPS(fops); 952 953 static const struct drm_driver msm_driver = { 954 .driver_features = DRIVER_GEM | 955 DRIVER_RENDER | 956 DRIVER_ATOMIC | 957 DRIVER_MODESET | 958 DRIVER_SYNCOBJ, 959 .open = msm_open, 960 .postclose = msm_postclose, 961 .lastclose = drm_fb_helper_lastclose, 962 .dumb_create = msm_gem_dumb_create, 963 .dumb_map_offset = msm_gem_dumb_map_offset, 964 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 965 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 966 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, 967 .gem_prime_mmap = drm_gem_prime_mmap, 968 #ifdef CONFIG_DEBUG_FS 969 .debugfs_init = msm_debugfs_init, 970 #endif 971 .ioctls = msm_ioctls, 972 .num_ioctls = ARRAY_SIZE(msm_ioctls), 973 .fops = &fops, 974 .name = "msm", 975 .desc = "MSM Snapdragon DRM", 976 .date = "20130625", 977 .major = MSM_VERSION_MAJOR, 978 .minor = MSM_VERSION_MINOR, 979 .patchlevel = MSM_VERSION_PATCHLEVEL, 980 }; 981 982 int msm_pm_prepare(struct device *dev) 983 { 984 struct msm_drm_private *priv = dev_get_drvdata(dev); 985 struct drm_device *ddev = priv ? priv->dev : NULL; 986 987 if (!priv || !priv->kms) 988 return 0; 989 990 return drm_mode_config_helper_suspend(ddev); 991 } 992 993 void msm_pm_complete(struct device *dev) 994 { 995 struct msm_drm_private *priv = dev_get_drvdata(dev); 996 struct drm_device *ddev = priv ? priv->dev : NULL; 997 998 if (!priv || !priv->kms) 999 return; 1000 1001 drm_mode_config_helper_resume(ddev); 1002 } 1003 1004 static const struct dev_pm_ops msm_pm_ops = { 1005 .prepare = msm_pm_prepare, 1006 .complete = msm_pm_complete, 1007 }; 1008 1009 /* 1010 * Componentized driver support: 1011 */ 1012 1013 /* 1014 * Identify what components need to be added by parsing what remote-endpoints 1015 * our MDP output ports are connected to. In the case of LVDS on MDP4, there 1016 * is no external component that we need to add since LVDS is within MDP4 1017 * itself. 1018 */ 1019 static int add_components_mdp(struct device *master_dev, 1020 struct component_match **matchptr) 1021 { 1022 struct device_node *np = master_dev->of_node; 1023 struct device_node *ep_node; 1024 1025 for_each_endpoint_of_node(np, ep_node) { 1026 struct device_node *intf; 1027 struct of_endpoint ep; 1028 int ret; 1029 1030 ret = of_graph_parse_endpoint(ep_node, &ep); 1031 if (ret) { 1032 DRM_DEV_ERROR(master_dev, "unable to parse port endpoint\n"); 1033 of_node_put(ep_node); 1034 return ret; 1035 } 1036 1037 /* 1038 * The LCDC/LVDS port on MDP4 is a speacial case where the 1039 * remote-endpoint isn't a component that we need to add 1040 */ 1041 if (of_device_is_compatible(np, "qcom,mdp4") && 1042 ep.port == 0) 1043 continue; 1044 1045 /* 1046 * It's okay if some of the ports don't have a remote endpoint 1047 * specified. It just means that the port isn't connected to 1048 * any external interface. 1049 */ 1050 intf = of_graph_get_remote_port_parent(ep_node); 1051 if (!intf) 1052 continue; 1053 1054 if (of_device_is_available(intf)) 1055 drm_of_component_match_add(master_dev, matchptr, 1056 component_compare_of, intf); 1057 1058 of_node_put(intf); 1059 } 1060 1061 return 0; 1062 } 1063 1064 /* 1065 * We don't know what's the best binding to link the gpu with the drm device. 1066 * Fow now, we just hunt for all the possible gpus that we support, and add them 1067 * as components. 1068 */ 1069 static const struct of_device_id msm_gpu_match[] = { 1070 { .compatible = "qcom,adreno" }, 1071 { .compatible = "qcom,adreno-3xx" }, 1072 { .compatible = "amd,imageon" }, 1073 { .compatible = "qcom,kgsl-3d0" }, 1074 { }, 1075 }; 1076 1077 static int add_gpu_components(struct device *dev, 1078 struct component_match **matchptr) 1079 { 1080 struct device_node *np; 1081 1082 np = of_find_matching_node(NULL, msm_gpu_match); 1083 if (!np) 1084 return 0; 1085 1086 if (of_device_is_available(np)) 1087 drm_of_component_match_add(dev, matchptr, component_compare_of, np); 1088 1089 of_node_put(np); 1090 1091 return 0; 1092 } 1093 1094 static int msm_drm_bind(struct device *dev) 1095 { 1096 return msm_drm_init(dev, &msm_driver); 1097 } 1098 1099 static void msm_drm_unbind(struct device *dev) 1100 { 1101 msm_drm_uninit(dev); 1102 } 1103 1104 const struct component_master_ops msm_drm_ops = { 1105 .bind = msm_drm_bind, 1106 .unbind = msm_drm_unbind, 1107 }; 1108 1109 int msm_drv_probe(struct device *master_dev, 1110 int (*kms_init)(struct drm_device *dev)) 1111 { 1112 struct msm_drm_private *priv; 1113 struct component_match *match = NULL; 1114 int ret; 1115 1116 priv = devm_kzalloc(master_dev, sizeof(*priv), GFP_KERNEL); 1117 if (!priv) 1118 return -ENOMEM; 1119 1120 priv->kms_init = kms_init; 1121 dev_set_drvdata(master_dev, priv); 1122 1123 /* Add mdp components if we have KMS. */ 1124 if (kms_init) { 1125 ret = add_components_mdp(master_dev, &match); 1126 if (ret) 1127 return ret; 1128 } 1129 1130 ret = add_gpu_components(master_dev, &match); 1131 if (ret) 1132 return ret; 1133 1134 /* on all devices that I am aware of, iommu's which can map 1135 * any address the cpu can see are used: 1136 */ 1137 ret = dma_set_mask_and_coherent(master_dev, ~0); 1138 if (ret) 1139 return ret; 1140 1141 ret = component_master_add_with_match(master_dev, &msm_drm_ops, match); 1142 if (ret) 1143 return ret; 1144 1145 return 0; 1146 } 1147 1148 /* 1149 * Platform driver: 1150 * Used only for headlesss GPU instances 1151 */ 1152 1153 static int msm_pdev_probe(struct platform_device *pdev) 1154 { 1155 return msm_drv_probe(&pdev->dev, NULL); 1156 } 1157 1158 static int msm_pdev_remove(struct platform_device *pdev) 1159 { 1160 component_master_del(&pdev->dev, &msm_drm_ops); 1161 1162 return 0; 1163 } 1164 1165 void msm_drv_shutdown(struct platform_device *pdev) 1166 { 1167 struct msm_drm_private *priv = platform_get_drvdata(pdev); 1168 struct drm_device *drm = priv ? priv->dev : NULL; 1169 1170 if (!priv || !priv->kms) 1171 return; 1172 1173 drm_atomic_helper_shutdown(drm); 1174 } 1175 1176 static struct platform_driver msm_platform_driver = { 1177 .probe = msm_pdev_probe, 1178 .remove = msm_pdev_remove, 1179 .shutdown = msm_drv_shutdown, 1180 .driver = { 1181 .name = "msm", 1182 .pm = &msm_pm_ops, 1183 }, 1184 }; 1185 1186 static int __init msm_drm_register(void) 1187 { 1188 if (!modeset) 1189 return -EINVAL; 1190 1191 DBG("init"); 1192 msm_mdp_register(); 1193 msm_dpu_register(); 1194 msm_dsi_register(); 1195 msm_hdmi_register(); 1196 msm_dp_register(); 1197 adreno_register(); 1198 msm_mdp4_register(); 1199 msm_mdss_register(); 1200 return platform_driver_register(&msm_platform_driver); 1201 } 1202 1203 static void __exit msm_drm_unregister(void) 1204 { 1205 DBG("fini"); 1206 platform_driver_unregister(&msm_platform_driver); 1207 msm_mdss_unregister(); 1208 msm_mdp4_unregister(); 1209 msm_dp_unregister(); 1210 msm_hdmi_unregister(); 1211 adreno_unregister(); 1212 msm_dsi_unregister(); 1213 msm_mdp_unregister(); 1214 msm_dpu_unregister(); 1215 } 1216 1217 module_init(msm_drm_register); 1218 module_exit(msm_drm_unregister); 1219 1220 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 1221 MODULE_DESCRIPTION("MSM DRM Driver"); 1222 MODULE_LICENSE("GPL"); 1223