1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/dma-mapping.h> 9 #include <linux/kthread.h> 10 #include <linux/sched/mm.h> 11 #include <linux/uaccess.h> 12 #include <uapi/linux/sched/types.h> 13 14 #include <drm/drm_bridge.h> 15 #include <drm/drm_drv.h> 16 #include <drm/drm_file.h> 17 #include <drm/drm_ioctl.h> 18 #include <drm/drm_prime.h> 19 #include <drm/drm_of.h> 20 #include <drm/drm_vblank.h> 21 22 #include "disp/msm_disp_snapshot.h" 23 #include "msm_drv.h" 24 #include "msm_debugfs.h" 25 #include "msm_fence.h" 26 #include "msm_gem.h" 27 #include "msm_gpu.h" 28 #include "msm_kms.h" 29 #include "msm_mmu.h" 30 #include "adreno/adreno_gpu.h" 31 32 /* 33 * MSM driver version: 34 * - 1.0.0 - initial interface 35 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers 36 * - 1.2.0 - adds explicit fence support for submit ioctl 37 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW + 38 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for 39 * MSM_GEM_INFO ioctl. 40 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get 41 * GEM object's debug name 42 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl 43 * - 1.6.0 - Syncobj support 44 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count 45 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx) 46 * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN 47 */ 48 #define MSM_VERSION_MAJOR 1 49 #define MSM_VERSION_MINOR 9 50 #define MSM_VERSION_PATCHLEVEL 0 51 52 static const struct drm_mode_config_funcs mode_config_funcs = { 53 .fb_create = msm_framebuffer_create, 54 .output_poll_changed = drm_fb_helper_output_poll_changed, 55 .atomic_check = drm_atomic_helper_check, 56 .atomic_commit = drm_atomic_helper_commit, 57 }; 58 59 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = { 60 .atomic_commit_tail = msm_atomic_commit_tail, 61 }; 62 63 #ifdef CONFIG_DRM_FBDEV_EMULATION 64 static bool fbdev = true; 65 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer"); 66 module_param(fbdev, bool, 0600); 67 #endif 68 69 static char *vram = "16m"; 70 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)"); 71 module_param(vram, charp, 0); 72 73 bool dumpstate; 74 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors"); 75 module_param(dumpstate, bool, 0600); 76 77 static bool modeset = true; 78 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)"); 79 module_param(modeset, bool, 0600); 80 81 static irqreturn_t msm_irq(int irq, void *arg) 82 { 83 struct drm_device *dev = arg; 84 struct msm_drm_private *priv = dev->dev_private; 85 struct msm_kms *kms = priv->kms; 86 87 BUG_ON(!kms); 88 89 return kms->funcs->irq(kms); 90 } 91 92 static void msm_irq_preinstall(struct drm_device *dev) 93 { 94 struct msm_drm_private *priv = dev->dev_private; 95 struct msm_kms *kms = priv->kms; 96 97 BUG_ON(!kms); 98 99 kms->funcs->irq_preinstall(kms); 100 } 101 102 static int msm_irq_postinstall(struct drm_device *dev) 103 { 104 struct msm_drm_private *priv = dev->dev_private; 105 struct msm_kms *kms = priv->kms; 106 107 BUG_ON(!kms); 108 109 if (kms->funcs->irq_postinstall) 110 return kms->funcs->irq_postinstall(kms); 111 112 return 0; 113 } 114 115 static int msm_irq_install(struct drm_device *dev, unsigned int irq) 116 { 117 struct msm_drm_private *priv = dev->dev_private; 118 struct msm_kms *kms = priv->kms; 119 int ret; 120 121 if (irq == IRQ_NOTCONNECTED) 122 return -ENOTCONN; 123 124 msm_irq_preinstall(dev); 125 126 ret = request_irq(irq, msm_irq, 0, dev->driver->name, dev); 127 if (ret) 128 return ret; 129 130 kms->irq_requested = true; 131 132 ret = msm_irq_postinstall(dev); 133 if (ret) { 134 free_irq(irq, dev); 135 return ret; 136 } 137 138 return 0; 139 } 140 141 static void msm_irq_uninstall(struct drm_device *dev) 142 { 143 struct msm_drm_private *priv = dev->dev_private; 144 struct msm_kms *kms = priv->kms; 145 146 kms->funcs->irq_uninstall(kms); 147 if (kms->irq_requested) 148 free_irq(kms->irq, dev); 149 } 150 151 struct msm_vblank_work { 152 struct work_struct work; 153 int crtc_id; 154 bool enable; 155 struct msm_drm_private *priv; 156 }; 157 158 static void vblank_ctrl_worker(struct work_struct *work) 159 { 160 struct msm_vblank_work *vbl_work = container_of(work, 161 struct msm_vblank_work, work); 162 struct msm_drm_private *priv = vbl_work->priv; 163 struct msm_kms *kms = priv->kms; 164 165 if (vbl_work->enable) 166 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]); 167 else 168 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]); 169 170 kfree(vbl_work); 171 } 172 173 static int vblank_ctrl_queue_work(struct msm_drm_private *priv, 174 int crtc_id, bool enable) 175 { 176 struct msm_vblank_work *vbl_work; 177 178 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC); 179 if (!vbl_work) 180 return -ENOMEM; 181 182 INIT_WORK(&vbl_work->work, vblank_ctrl_worker); 183 184 vbl_work->crtc_id = crtc_id; 185 vbl_work->enable = enable; 186 vbl_work->priv = priv; 187 188 queue_work(priv->wq, &vbl_work->work); 189 190 return 0; 191 } 192 193 static int msm_drm_uninit(struct device *dev) 194 { 195 struct platform_device *pdev = to_platform_device(dev); 196 struct msm_drm_private *priv = platform_get_drvdata(pdev); 197 struct drm_device *ddev = priv->dev; 198 struct msm_kms *kms = priv->kms; 199 int i; 200 201 /* 202 * Shutdown the hw if we're far enough along where things might be on. 203 * If we run this too early, we'll end up panicking in any variety of 204 * places. Since we don't register the drm device until late in 205 * msm_drm_init, drm_dev->registered is used as an indicator that the 206 * shutdown will be successful. 207 */ 208 if (ddev->registered) { 209 drm_dev_unregister(ddev); 210 drm_atomic_helper_shutdown(ddev); 211 } 212 213 /* We must cancel and cleanup any pending vblank enable/disable 214 * work before msm_irq_uninstall() to avoid work re-enabling an 215 * irq after uninstall has disabled it. 216 */ 217 218 flush_workqueue(priv->wq); 219 220 /* clean up event worker threads */ 221 for (i = 0; i < priv->num_crtcs; i++) { 222 if (priv->event_thread[i].worker) 223 kthread_destroy_worker(priv->event_thread[i].worker); 224 } 225 226 msm_gem_shrinker_cleanup(ddev); 227 228 drm_kms_helper_poll_fini(ddev); 229 230 msm_perf_debugfs_cleanup(priv); 231 msm_rd_debugfs_cleanup(priv); 232 233 #ifdef CONFIG_DRM_FBDEV_EMULATION 234 if (fbdev && priv->fbdev) 235 msm_fbdev_free(ddev); 236 #endif 237 238 msm_disp_snapshot_destroy(ddev); 239 240 drm_mode_config_cleanup(ddev); 241 242 for (i = 0; i < priv->num_bridges; i++) 243 drm_bridge_remove(priv->bridges[i]); 244 245 pm_runtime_get_sync(dev); 246 msm_irq_uninstall(ddev); 247 pm_runtime_put_sync(dev); 248 249 if (kms && kms->funcs) 250 kms->funcs->destroy(kms); 251 252 if (priv->vram.paddr) { 253 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING; 254 drm_mm_takedown(&priv->vram.mm); 255 dma_free_attrs(dev, priv->vram.size, NULL, 256 priv->vram.paddr, attrs); 257 } 258 259 component_unbind_all(dev, ddev); 260 261 ddev->dev_private = NULL; 262 drm_dev_put(ddev); 263 264 destroy_workqueue(priv->wq); 265 266 return 0; 267 } 268 269 #include <linux/of_address.h> 270 271 struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev) 272 { 273 struct iommu_domain *domain; 274 struct msm_gem_address_space *aspace; 275 struct msm_mmu *mmu; 276 struct device *mdp_dev = dev->dev; 277 struct device *mdss_dev = mdp_dev->parent; 278 struct device *iommu_dev; 279 280 /* 281 * IOMMUs can be a part of MDSS device tree binding, or the 282 * MDP/DPU device. 283 */ 284 if (device_iommu_mapped(mdp_dev)) 285 iommu_dev = mdp_dev; 286 else 287 iommu_dev = mdss_dev; 288 289 domain = iommu_domain_alloc(iommu_dev->bus); 290 if (!domain) { 291 drm_info(dev, "no IOMMU, fallback to phys contig buffers for scanout\n"); 292 return NULL; 293 } 294 295 mmu = msm_iommu_new(iommu_dev, domain); 296 if (IS_ERR(mmu)) { 297 iommu_domain_free(domain); 298 return ERR_CAST(mmu); 299 } 300 301 aspace = msm_gem_address_space_create(mmu, "mdp_kms", 302 0x1000, 0x100000000 - 0x1000); 303 if (IS_ERR(aspace)) 304 mmu->funcs->destroy(mmu); 305 306 return aspace; 307 } 308 309 bool msm_use_mmu(struct drm_device *dev) 310 { 311 struct msm_drm_private *priv = dev->dev_private; 312 313 /* 314 * a2xx comes with its own MMU 315 * On other platforms IOMMU can be declared specified either for the 316 * MDP/DPU device or for its parent, MDSS device. 317 */ 318 return priv->is_a2xx || 319 device_iommu_mapped(dev->dev) || 320 device_iommu_mapped(dev->dev->parent); 321 } 322 323 static int msm_init_vram(struct drm_device *dev) 324 { 325 struct msm_drm_private *priv = dev->dev_private; 326 struct device_node *node; 327 unsigned long size = 0; 328 int ret = 0; 329 330 /* In the device-tree world, we could have a 'memory-region' 331 * phandle, which gives us a link to our "vram". Allocating 332 * is all nicely abstracted behind the dma api, but we need 333 * to know the entire size to allocate it all in one go. There 334 * are two cases: 335 * 1) device with no IOMMU, in which case we need exclusive 336 * access to a VRAM carveout big enough for all gpu 337 * buffers 338 * 2) device with IOMMU, but where the bootloader puts up 339 * a splash screen. In this case, the VRAM carveout 340 * need only be large enough for fbdev fb. But we need 341 * exclusive access to the buffer to avoid the kernel 342 * using those pages for other purposes (which appears 343 * as corruption on screen before we have a chance to 344 * load and do initial modeset) 345 */ 346 347 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0); 348 if (node) { 349 struct resource r; 350 ret = of_address_to_resource(node, 0, &r); 351 of_node_put(node); 352 if (ret) 353 return ret; 354 size = r.end - r.start + 1; 355 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start); 356 357 /* if we have no IOMMU, then we need to use carveout allocator. 358 * Grab the entire CMA chunk carved out in early startup in 359 * mach-msm: 360 */ 361 } else if (!msm_use_mmu(dev)) { 362 DRM_INFO("using %s VRAM carveout\n", vram); 363 size = memparse(vram, NULL); 364 } 365 366 if (size) { 367 unsigned long attrs = 0; 368 void *p; 369 370 priv->vram.size = size; 371 372 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1); 373 spin_lock_init(&priv->vram.lock); 374 375 attrs |= DMA_ATTR_NO_KERNEL_MAPPING; 376 attrs |= DMA_ATTR_WRITE_COMBINE; 377 378 /* note that for no-kernel-mapping, the vaddr returned 379 * is bogus, but non-null if allocation succeeded: 380 */ 381 p = dma_alloc_attrs(dev->dev, size, 382 &priv->vram.paddr, GFP_KERNEL, attrs); 383 if (!p) { 384 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n"); 385 priv->vram.paddr = 0; 386 return -ENOMEM; 387 } 388 389 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n", 390 (uint32_t)priv->vram.paddr, 391 (uint32_t)(priv->vram.paddr + size)); 392 } 393 394 return ret; 395 } 396 397 static int msm_drm_init(struct device *dev, const struct drm_driver *drv) 398 { 399 struct msm_drm_private *priv = dev_get_drvdata(dev); 400 struct drm_device *ddev; 401 struct msm_kms *kms; 402 int ret, i; 403 404 if (drm_firmware_drivers_only()) 405 return -ENODEV; 406 407 ddev = drm_dev_alloc(drv, dev); 408 if (IS_ERR(ddev)) { 409 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n"); 410 return PTR_ERR(ddev); 411 } 412 ddev->dev_private = priv; 413 priv->dev = ddev; 414 415 priv->wq = alloc_ordered_workqueue("msm", 0); 416 priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD; 417 418 INIT_LIST_HEAD(&priv->objects); 419 mutex_init(&priv->obj_lock); 420 421 INIT_LIST_HEAD(&priv->inactive_willneed); 422 INIT_LIST_HEAD(&priv->inactive_dontneed); 423 INIT_LIST_HEAD(&priv->inactive_unpinned); 424 mutex_init(&priv->mm_lock); 425 426 /* Teach lockdep about lock ordering wrt. shrinker: */ 427 fs_reclaim_acquire(GFP_KERNEL); 428 might_lock(&priv->mm_lock); 429 fs_reclaim_release(GFP_KERNEL); 430 431 drm_mode_config_init(ddev); 432 433 ret = msm_init_vram(ddev); 434 if (ret) 435 return ret; 436 437 /* Bind all our sub-components: */ 438 ret = component_bind_all(dev, ddev); 439 if (ret) 440 return ret; 441 442 dma_set_max_seg_size(dev, UINT_MAX); 443 444 msm_gem_shrinker_init(ddev); 445 446 if (priv->kms_init) { 447 ret = priv->kms_init(ddev); 448 if (ret) { 449 DRM_DEV_ERROR(dev, "failed to load kms\n"); 450 priv->kms = NULL; 451 goto err_msm_uninit; 452 } 453 kms = priv->kms; 454 } else { 455 /* valid only for the dummy headless case, where of_node=NULL */ 456 WARN_ON(dev->of_node); 457 kms = NULL; 458 } 459 460 /* Enable normalization of plane zpos */ 461 ddev->mode_config.normalize_zpos = true; 462 463 if (kms) { 464 kms->dev = ddev; 465 ret = kms->funcs->hw_init(kms); 466 if (ret) { 467 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret); 468 goto err_msm_uninit; 469 } 470 } 471 472 drm_helper_move_panel_connectors_to_head(ddev); 473 474 ddev->mode_config.funcs = &mode_config_funcs; 475 ddev->mode_config.helper_private = &mode_config_helper_funcs; 476 477 for (i = 0; i < priv->num_crtcs; i++) { 478 /* initialize event thread */ 479 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id; 480 priv->event_thread[i].dev = ddev; 481 priv->event_thread[i].worker = kthread_create_worker(0, 482 "crtc_event:%d", priv->event_thread[i].crtc_id); 483 if (IS_ERR(priv->event_thread[i].worker)) { 484 ret = PTR_ERR(priv->event_thread[i].worker); 485 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n"); 486 ret = PTR_ERR(priv->event_thread[i].worker); 487 goto err_msm_uninit; 488 } 489 490 sched_set_fifo(priv->event_thread[i].worker->task); 491 } 492 493 ret = drm_vblank_init(ddev, priv->num_crtcs); 494 if (ret < 0) { 495 DRM_DEV_ERROR(dev, "failed to initialize vblank\n"); 496 goto err_msm_uninit; 497 } 498 499 if (kms) { 500 pm_runtime_get_sync(dev); 501 ret = msm_irq_install(ddev, kms->irq); 502 pm_runtime_put_sync(dev); 503 if (ret < 0) { 504 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n"); 505 goto err_msm_uninit; 506 } 507 } 508 509 ret = drm_dev_register(ddev, 0); 510 if (ret) 511 goto err_msm_uninit; 512 513 if (kms) { 514 ret = msm_disp_snapshot_init(ddev); 515 if (ret) 516 DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret); 517 } 518 drm_mode_config_reset(ddev); 519 520 #ifdef CONFIG_DRM_FBDEV_EMULATION 521 if (kms && fbdev) 522 priv->fbdev = msm_fbdev_init(ddev); 523 #endif 524 525 ret = msm_debugfs_late_init(ddev); 526 if (ret) 527 goto err_msm_uninit; 528 529 drm_kms_helper_poll_init(ddev); 530 531 return 0; 532 533 err_msm_uninit: 534 msm_drm_uninit(dev); 535 return ret; 536 } 537 538 /* 539 * DRM operations: 540 */ 541 542 static void load_gpu(struct drm_device *dev) 543 { 544 static DEFINE_MUTEX(init_lock); 545 struct msm_drm_private *priv = dev->dev_private; 546 547 mutex_lock(&init_lock); 548 549 if (!priv->gpu) 550 priv->gpu = adreno_load_gpu(dev); 551 552 mutex_unlock(&init_lock); 553 } 554 555 static int context_init(struct drm_device *dev, struct drm_file *file) 556 { 557 static atomic_t ident = ATOMIC_INIT(0); 558 struct msm_drm_private *priv = dev->dev_private; 559 struct msm_file_private *ctx; 560 561 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 562 if (!ctx) 563 return -ENOMEM; 564 565 INIT_LIST_HEAD(&ctx->submitqueues); 566 rwlock_init(&ctx->queuelock); 567 568 kref_init(&ctx->ref); 569 msm_submitqueue_init(dev, ctx); 570 571 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current); 572 file->driver_priv = ctx; 573 574 ctx->seqno = atomic_inc_return(&ident); 575 576 return 0; 577 } 578 579 static int msm_open(struct drm_device *dev, struct drm_file *file) 580 { 581 /* For now, load gpu on open.. to avoid the requirement of having 582 * firmware in the initrd. 583 */ 584 load_gpu(dev); 585 586 return context_init(dev, file); 587 } 588 589 static void context_close(struct msm_file_private *ctx) 590 { 591 msm_submitqueue_close(ctx); 592 msm_file_private_put(ctx); 593 } 594 595 static void msm_postclose(struct drm_device *dev, struct drm_file *file) 596 { 597 struct msm_drm_private *priv = dev->dev_private; 598 struct msm_file_private *ctx = file->driver_priv; 599 600 /* 601 * It is not possible to set sysprof param to non-zero if gpu 602 * is not initialized: 603 */ 604 if (priv->gpu) 605 msm_file_private_set_sysprof(ctx, priv->gpu, 0); 606 607 context_close(ctx); 608 } 609 610 int msm_crtc_enable_vblank(struct drm_crtc *crtc) 611 { 612 struct drm_device *dev = crtc->dev; 613 unsigned int pipe = crtc->index; 614 struct msm_drm_private *priv = dev->dev_private; 615 struct msm_kms *kms = priv->kms; 616 if (!kms) 617 return -ENXIO; 618 drm_dbg_vbl(dev, "crtc=%u", pipe); 619 return vblank_ctrl_queue_work(priv, pipe, true); 620 } 621 622 void msm_crtc_disable_vblank(struct drm_crtc *crtc) 623 { 624 struct drm_device *dev = crtc->dev; 625 unsigned int pipe = crtc->index; 626 struct msm_drm_private *priv = dev->dev_private; 627 struct msm_kms *kms = priv->kms; 628 if (!kms) 629 return; 630 drm_dbg_vbl(dev, "crtc=%u", pipe); 631 vblank_ctrl_queue_work(priv, pipe, false); 632 } 633 634 /* 635 * DRM ioctls: 636 */ 637 638 static int msm_ioctl_get_param(struct drm_device *dev, void *data, 639 struct drm_file *file) 640 { 641 struct msm_drm_private *priv = dev->dev_private; 642 struct drm_msm_param *args = data; 643 struct msm_gpu *gpu; 644 645 /* for now, we just have 3d pipe.. eventually this would need to 646 * be more clever to dispatch to appropriate gpu module: 647 */ 648 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0)) 649 return -EINVAL; 650 651 gpu = priv->gpu; 652 653 if (!gpu) 654 return -ENXIO; 655 656 return gpu->funcs->get_param(gpu, file->driver_priv, 657 args->param, &args->value, &args->len); 658 } 659 660 static int msm_ioctl_set_param(struct drm_device *dev, void *data, 661 struct drm_file *file) 662 { 663 struct msm_drm_private *priv = dev->dev_private; 664 struct drm_msm_param *args = data; 665 struct msm_gpu *gpu; 666 667 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0)) 668 return -EINVAL; 669 670 gpu = priv->gpu; 671 672 if (!gpu) 673 return -ENXIO; 674 675 return gpu->funcs->set_param(gpu, file->driver_priv, 676 args->param, args->value, args->len); 677 } 678 679 static int msm_ioctl_gem_new(struct drm_device *dev, void *data, 680 struct drm_file *file) 681 { 682 struct drm_msm_gem_new *args = data; 683 uint32_t flags = args->flags; 684 685 if (args->flags & ~MSM_BO_FLAGS) { 686 DRM_ERROR("invalid flags: %08x\n", args->flags); 687 return -EINVAL; 688 } 689 690 /* 691 * Uncached CPU mappings are deprecated, as of: 692 * 693 * 9ef364432db4 ("drm/msm: deprecate MSM_BO_UNCACHED (map as writecombine instead)") 694 * 695 * So promote them to WC. 696 */ 697 if (flags & MSM_BO_UNCACHED) { 698 flags &= ~MSM_BO_CACHED; 699 flags |= MSM_BO_WC; 700 } 701 702 return msm_gem_new_handle(dev, file, args->size, 703 args->flags, &args->handle, NULL); 704 } 705 706 static inline ktime_t to_ktime(struct drm_msm_timespec timeout) 707 { 708 return ktime_set(timeout.tv_sec, timeout.tv_nsec); 709 } 710 711 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, 712 struct drm_file *file) 713 { 714 struct drm_msm_gem_cpu_prep *args = data; 715 struct drm_gem_object *obj; 716 ktime_t timeout = to_ktime(args->timeout); 717 int ret; 718 719 if (args->op & ~MSM_PREP_FLAGS) { 720 DRM_ERROR("invalid op: %08x\n", args->op); 721 return -EINVAL; 722 } 723 724 obj = drm_gem_object_lookup(file, args->handle); 725 if (!obj) 726 return -ENOENT; 727 728 ret = msm_gem_cpu_prep(obj, args->op, &timeout); 729 730 drm_gem_object_put(obj); 731 732 return ret; 733 } 734 735 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, 736 struct drm_file *file) 737 { 738 struct drm_msm_gem_cpu_fini *args = data; 739 struct drm_gem_object *obj; 740 int ret; 741 742 obj = drm_gem_object_lookup(file, args->handle); 743 if (!obj) 744 return -ENOENT; 745 746 ret = msm_gem_cpu_fini(obj); 747 748 drm_gem_object_put(obj); 749 750 return ret; 751 } 752 753 static int msm_ioctl_gem_info_iova(struct drm_device *dev, 754 struct drm_file *file, struct drm_gem_object *obj, 755 uint64_t *iova) 756 { 757 struct msm_drm_private *priv = dev->dev_private; 758 struct msm_file_private *ctx = file->driver_priv; 759 760 if (!priv->gpu) 761 return -EINVAL; 762 763 /* 764 * Don't pin the memory here - just get an address so that userspace can 765 * be productive 766 */ 767 return msm_gem_get_iova(obj, ctx->aspace, iova); 768 } 769 770 static int msm_ioctl_gem_info_set_iova(struct drm_device *dev, 771 struct drm_file *file, struct drm_gem_object *obj, 772 uint64_t iova) 773 { 774 struct msm_drm_private *priv = dev->dev_private; 775 struct msm_file_private *ctx = file->driver_priv; 776 777 if (!priv->gpu) 778 return -EINVAL; 779 780 /* Only supported if per-process address space is supported: */ 781 if (priv->gpu->aspace == ctx->aspace) 782 return -EOPNOTSUPP; 783 784 return msm_gem_set_iova(obj, ctx->aspace, iova); 785 } 786 787 static int msm_ioctl_gem_info(struct drm_device *dev, void *data, 788 struct drm_file *file) 789 { 790 struct drm_msm_gem_info *args = data; 791 struct drm_gem_object *obj; 792 struct msm_gem_object *msm_obj; 793 int i, ret = 0; 794 795 if (args->pad) 796 return -EINVAL; 797 798 switch (args->info) { 799 case MSM_INFO_GET_OFFSET: 800 case MSM_INFO_GET_IOVA: 801 case MSM_INFO_SET_IOVA: 802 /* value returned as immediate, not pointer, so len==0: */ 803 if (args->len) 804 return -EINVAL; 805 break; 806 case MSM_INFO_SET_NAME: 807 case MSM_INFO_GET_NAME: 808 break; 809 default: 810 return -EINVAL; 811 } 812 813 obj = drm_gem_object_lookup(file, args->handle); 814 if (!obj) 815 return -ENOENT; 816 817 msm_obj = to_msm_bo(obj); 818 819 switch (args->info) { 820 case MSM_INFO_GET_OFFSET: 821 args->value = msm_gem_mmap_offset(obj); 822 break; 823 case MSM_INFO_GET_IOVA: 824 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value); 825 break; 826 case MSM_INFO_SET_IOVA: 827 ret = msm_ioctl_gem_info_set_iova(dev, file, obj, args->value); 828 break; 829 case MSM_INFO_SET_NAME: 830 /* length check should leave room for terminating null: */ 831 if (args->len >= sizeof(msm_obj->name)) { 832 ret = -EINVAL; 833 break; 834 } 835 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value), 836 args->len)) { 837 msm_obj->name[0] = '\0'; 838 ret = -EFAULT; 839 break; 840 } 841 msm_obj->name[args->len] = '\0'; 842 for (i = 0; i < args->len; i++) { 843 if (!isprint(msm_obj->name[i])) { 844 msm_obj->name[i] = '\0'; 845 break; 846 } 847 } 848 break; 849 case MSM_INFO_GET_NAME: 850 if (args->value && (args->len < strlen(msm_obj->name))) { 851 ret = -EINVAL; 852 break; 853 } 854 args->len = strlen(msm_obj->name); 855 if (args->value) { 856 if (copy_to_user(u64_to_user_ptr(args->value), 857 msm_obj->name, args->len)) 858 ret = -EFAULT; 859 } 860 break; 861 } 862 863 drm_gem_object_put(obj); 864 865 return ret; 866 } 867 868 static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id, 869 ktime_t timeout) 870 { 871 struct dma_fence *fence; 872 int ret; 873 874 if (fence_after(fence_id, queue->last_fence)) { 875 DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n", 876 fence_id, queue->last_fence); 877 return -EINVAL; 878 } 879 880 /* 881 * Map submitqueue scoped "seqno" (which is actually an idr key) 882 * back to underlying dma-fence 883 * 884 * The fence is removed from the fence_idr when the submit is 885 * retired, so if the fence is not found it means there is nothing 886 * to wait for 887 */ 888 ret = mutex_lock_interruptible(&queue->lock); 889 if (ret) 890 return ret; 891 fence = idr_find(&queue->fence_idr, fence_id); 892 if (fence) 893 fence = dma_fence_get_rcu(fence); 894 mutex_unlock(&queue->lock); 895 896 if (!fence) 897 return 0; 898 899 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout)); 900 if (ret == 0) { 901 ret = -ETIMEDOUT; 902 } else if (ret != -ERESTARTSYS) { 903 ret = 0; 904 } 905 906 dma_fence_put(fence); 907 908 return ret; 909 } 910 911 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, 912 struct drm_file *file) 913 { 914 struct msm_drm_private *priv = dev->dev_private; 915 struct drm_msm_wait_fence *args = data; 916 struct msm_gpu_submitqueue *queue; 917 int ret; 918 919 if (args->pad) { 920 DRM_ERROR("invalid pad: %08x\n", args->pad); 921 return -EINVAL; 922 } 923 924 if (!priv->gpu) 925 return 0; 926 927 queue = msm_submitqueue_get(file->driver_priv, args->queueid); 928 if (!queue) 929 return -ENOENT; 930 931 ret = wait_fence(queue, args->fence, to_ktime(args->timeout)); 932 933 msm_submitqueue_put(queue); 934 935 return ret; 936 } 937 938 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data, 939 struct drm_file *file) 940 { 941 struct drm_msm_gem_madvise *args = data; 942 struct drm_gem_object *obj; 943 int ret; 944 945 switch (args->madv) { 946 case MSM_MADV_DONTNEED: 947 case MSM_MADV_WILLNEED: 948 break; 949 default: 950 return -EINVAL; 951 } 952 953 obj = drm_gem_object_lookup(file, args->handle); 954 if (!obj) { 955 return -ENOENT; 956 } 957 958 ret = msm_gem_madvise(obj, args->madv); 959 if (ret >= 0) { 960 args->retained = ret; 961 ret = 0; 962 } 963 964 drm_gem_object_put(obj); 965 966 return ret; 967 } 968 969 970 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data, 971 struct drm_file *file) 972 { 973 struct drm_msm_submitqueue *args = data; 974 975 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS) 976 return -EINVAL; 977 978 return msm_submitqueue_create(dev, file->driver_priv, args->prio, 979 args->flags, &args->id); 980 } 981 982 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data, 983 struct drm_file *file) 984 { 985 return msm_submitqueue_query(dev, file->driver_priv, data); 986 } 987 988 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data, 989 struct drm_file *file) 990 { 991 u32 id = *(u32 *) data; 992 993 return msm_submitqueue_remove(file->driver_priv, id); 994 } 995 996 static const struct drm_ioctl_desc msm_ioctls[] = { 997 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW), 998 DRM_IOCTL_DEF_DRV(MSM_SET_PARAM, msm_ioctl_set_param, DRM_RENDER_ALLOW), 999 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW), 1000 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW), 1001 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW), 1002 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW), 1003 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW), 1004 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW), 1005 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW), 1006 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW), 1007 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW), 1008 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW), 1009 }; 1010 1011 static void msm_fop_show_fdinfo(struct seq_file *m, struct file *f) 1012 { 1013 struct drm_file *file = f->private_data; 1014 struct drm_device *dev = file->minor->dev; 1015 struct msm_drm_private *priv = dev->dev_private; 1016 struct drm_printer p = drm_seq_file_printer(m); 1017 1018 if (!priv->gpu) 1019 return; 1020 1021 msm_gpu_show_fdinfo(priv->gpu, file->driver_priv, &p); 1022 } 1023 1024 static const struct file_operations fops = { 1025 .owner = THIS_MODULE, 1026 DRM_GEM_FOPS, 1027 .show_fdinfo = msm_fop_show_fdinfo, 1028 }; 1029 1030 static const struct drm_driver msm_driver = { 1031 .driver_features = DRIVER_GEM | 1032 DRIVER_RENDER | 1033 DRIVER_ATOMIC | 1034 DRIVER_MODESET | 1035 DRIVER_SYNCOBJ, 1036 .open = msm_open, 1037 .postclose = msm_postclose, 1038 .lastclose = drm_fb_helper_lastclose, 1039 .dumb_create = msm_gem_dumb_create, 1040 .dumb_map_offset = msm_gem_dumb_map_offset, 1041 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1042 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1043 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, 1044 .gem_prime_mmap = msm_gem_prime_mmap, 1045 #ifdef CONFIG_DEBUG_FS 1046 .debugfs_init = msm_debugfs_init, 1047 #endif 1048 .ioctls = msm_ioctls, 1049 .num_ioctls = ARRAY_SIZE(msm_ioctls), 1050 .fops = &fops, 1051 .name = "msm", 1052 .desc = "MSM Snapdragon DRM", 1053 .date = "20130625", 1054 .major = MSM_VERSION_MAJOR, 1055 .minor = MSM_VERSION_MINOR, 1056 .patchlevel = MSM_VERSION_PATCHLEVEL, 1057 }; 1058 1059 int msm_pm_prepare(struct device *dev) 1060 { 1061 struct msm_drm_private *priv = dev_get_drvdata(dev); 1062 struct drm_device *ddev = priv ? priv->dev : NULL; 1063 1064 if (!priv || !priv->kms) 1065 return 0; 1066 1067 return drm_mode_config_helper_suspend(ddev); 1068 } 1069 1070 void msm_pm_complete(struct device *dev) 1071 { 1072 struct msm_drm_private *priv = dev_get_drvdata(dev); 1073 struct drm_device *ddev = priv ? priv->dev : NULL; 1074 1075 if (!priv || !priv->kms) 1076 return; 1077 1078 drm_mode_config_helper_resume(ddev); 1079 } 1080 1081 static const struct dev_pm_ops msm_pm_ops = { 1082 .prepare = msm_pm_prepare, 1083 .complete = msm_pm_complete, 1084 }; 1085 1086 /* 1087 * Componentized driver support: 1088 */ 1089 1090 /* 1091 * Identify what components need to be added by parsing what remote-endpoints 1092 * our MDP output ports are connected to. In the case of LVDS on MDP4, there 1093 * is no external component that we need to add since LVDS is within MDP4 1094 * itself. 1095 */ 1096 static int add_components_mdp(struct device *master_dev, 1097 struct component_match **matchptr) 1098 { 1099 struct device_node *np = master_dev->of_node; 1100 struct device_node *ep_node; 1101 1102 for_each_endpoint_of_node(np, ep_node) { 1103 struct device_node *intf; 1104 struct of_endpoint ep; 1105 int ret; 1106 1107 ret = of_graph_parse_endpoint(ep_node, &ep); 1108 if (ret) { 1109 DRM_DEV_ERROR(master_dev, "unable to parse port endpoint\n"); 1110 of_node_put(ep_node); 1111 return ret; 1112 } 1113 1114 /* 1115 * The LCDC/LVDS port on MDP4 is a speacial case where the 1116 * remote-endpoint isn't a component that we need to add 1117 */ 1118 if (of_device_is_compatible(np, "qcom,mdp4") && 1119 ep.port == 0) 1120 continue; 1121 1122 /* 1123 * It's okay if some of the ports don't have a remote endpoint 1124 * specified. It just means that the port isn't connected to 1125 * any external interface. 1126 */ 1127 intf = of_graph_get_remote_port_parent(ep_node); 1128 if (!intf) 1129 continue; 1130 1131 if (of_device_is_available(intf)) 1132 drm_of_component_match_add(master_dev, matchptr, 1133 component_compare_of, intf); 1134 1135 of_node_put(intf); 1136 } 1137 1138 return 0; 1139 } 1140 1141 /* 1142 * We don't know what's the best binding to link the gpu with the drm device. 1143 * Fow now, we just hunt for all the possible gpus that we support, and add them 1144 * as components. 1145 */ 1146 static const struct of_device_id msm_gpu_match[] = { 1147 { .compatible = "qcom,adreno" }, 1148 { .compatible = "qcom,adreno-3xx" }, 1149 { .compatible = "amd,imageon" }, 1150 { .compatible = "qcom,kgsl-3d0" }, 1151 { }, 1152 }; 1153 1154 static int add_gpu_components(struct device *dev, 1155 struct component_match **matchptr) 1156 { 1157 struct device_node *np; 1158 1159 np = of_find_matching_node(NULL, msm_gpu_match); 1160 if (!np) 1161 return 0; 1162 1163 if (of_device_is_available(np)) 1164 drm_of_component_match_add(dev, matchptr, component_compare_of, np); 1165 1166 of_node_put(np); 1167 1168 return 0; 1169 } 1170 1171 static int msm_drm_bind(struct device *dev) 1172 { 1173 return msm_drm_init(dev, &msm_driver); 1174 } 1175 1176 static void msm_drm_unbind(struct device *dev) 1177 { 1178 msm_drm_uninit(dev); 1179 } 1180 1181 const struct component_master_ops msm_drm_ops = { 1182 .bind = msm_drm_bind, 1183 .unbind = msm_drm_unbind, 1184 }; 1185 1186 int msm_drv_probe(struct device *master_dev, 1187 int (*kms_init)(struct drm_device *dev)) 1188 { 1189 struct msm_drm_private *priv; 1190 struct component_match *match = NULL; 1191 int ret; 1192 1193 priv = devm_kzalloc(master_dev, sizeof(*priv), GFP_KERNEL); 1194 if (!priv) 1195 return -ENOMEM; 1196 1197 priv->kms_init = kms_init; 1198 dev_set_drvdata(master_dev, priv); 1199 1200 /* Add mdp components if we have KMS. */ 1201 if (kms_init) { 1202 ret = add_components_mdp(master_dev, &match); 1203 if (ret) 1204 return ret; 1205 } 1206 1207 ret = add_gpu_components(master_dev, &match); 1208 if (ret) 1209 return ret; 1210 1211 /* on all devices that I am aware of, iommu's which can map 1212 * any address the cpu can see are used: 1213 */ 1214 ret = dma_set_mask_and_coherent(master_dev, ~0); 1215 if (ret) 1216 return ret; 1217 1218 ret = component_master_add_with_match(master_dev, &msm_drm_ops, match); 1219 if (ret) 1220 return ret; 1221 1222 return 0; 1223 } 1224 1225 /* 1226 * Platform driver: 1227 * Used only for headlesss GPU instances 1228 */ 1229 1230 static int msm_pdev_probe(struct platform_device *pdev) 1231 { 1232 return msm_drv_probe(&pdev->dev, NULL); 1233 } 1234 1235 static int msm_pdev_remove(struct platform_device *pdev) 1236 { 1237 component_master_del(&pdev->dev, &msm_drm_ops); 1238 1239 return 0; 1240 } 1241 1242 void msm_drv_shutdown(struct platform_device *pdev) 1243 { 1244 struct msm_drm_private *priv = platform_get_drvdata(pdev); 1245 struct drm_device *drm = priv ? priv->dev : NULL; 1246 1247 if (!priv || !priv->kms) 1248 return; 1249 1250 drm_atomic_helper_shutdown(drm); 1251 } 1252 1253 static struct platform_driver msm_platform_driver = { 1254 .probe = msm_pdev_probe, 1255 .remove = msm_pdev_remove, 1256 .shutdown = msm_drv_shutdown, 1257 .driver = { 1258 .name = "msm", 1259 .pm = &msm_pm_ops, 1260 }, 1261 }; 1262 1263 static int __init msm_drm_register(void) 1264 { 1265 if (!modeset) 1266 return -EINVAL; 1267 1268 DBG("init"); 1269 msm_mdp_register(); 1270 msm_dpu_register(); 1271 msm_dsi_register(); 1272 msm_hdmi_register(); 1273 msm_dp_register(); 1274 adreno_register(); 1275 msm_mdp4_register(); 1276 msm_mdss_register(); 1277 return platform_driver_register(&msm_platform_driver); 1278 } 1279 1280 static void __exit msm_drm_unregister(void) 1281 { 1282 DBG("fini"); 1283 platform_driver_unregister(&msm_platform_driver); 1284 msm_mdss_unregister(); 1285 msm_mdp4_unregister(); 1286 msm_dp_unregister(); 1287 msm_hdmi_unregister(); 1288 adreno_unregister(); 1289 msm_dsi_unregister(); 1290 msm_mdp_unregister(); 1291 msm_dpu_unregister(); 1292 } 1293 1294 module_init(msm_drm_register); 1295 module_exit(msm_drm_unregister); 1296 1297 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 1298 MODULE_DESCRIPTION("MSM DRM Driver"); 1299 MODULE_LICENSE("GPL"); 1300