xref: /openbmc/linux/drivers/gpu/drm/msm/msm_drv.c (revision 9a8f3203)
1 /*
2  * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License version 2 as published by
8  * the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18 
19 #include <linux/kthread.h>
20 #include <uapi/linux/sched/types.h>
21 #include <drm/drm_of.h>
22 
23 #include "msm_drv.h"
24 #include "msm_debugfs.h"
25 #include "msm_fence.h"
26 #include "msm_gem.h"
27 #include "msm_gpu.h"
28 #include "msm_kms.h"
29 #include "adreno/adreno_gpu.h"
30 
31 
32 /*
33  * MSM driver version:
34  * - 1.0.0 - initial interface
35  * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
36  * - 1.2.0 - adds explicit fence support for submit ioctl
37  * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
38  *           SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
39  *           MSM_GEM_INFO ioctl.
40  * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
41  *           GEM object's debug name
42  */
43 #define MSM_VERSION_MAJOR	1
44 #define MSM_VERSION_MINOR	4
45 #define MSM_VERSION_PATCHLEVEL	0
46 
47 static const struct drm_mode_config_funcs mode_config_funcs = {
48 	.fb_create = msm_framebuffer_create,
49 	.output_poll_changed = drm_fb_helper_output_poll_changed,
50 	.atomic_check = drm_atomic_helper_check,
51 	.atomic_commit = drm_atomic_helper_commit,
52 };
53 
54 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
55 	.atomic_commit_tail = msm_atomic_commit_tail,
56 };
57 
58 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
59 static bool reglog = false;
60 MODULE_PARM_DESC(reglog, "Enable register read/write logging");
61 module_param(reglog, bool, 0600);
62 #else
63 #define reglog 0
64 #endif
65 
66 #ifdef CONFIG_DRM_FBDEV_EMULATION
67 static bool fbdev = true;
68 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
69 module_param(fbdev, bool, 0600);
70 #endif
71 
72 static char *vram = "16m";
73 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
74 module_param(vram, charp, 0);
75 
76 bool dumpstate = false;
77 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
78 module_param(dumpstate, bool, 0600);
79 
80 static bool modeset = true;
81 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
82 module_param(modeset, bool, 0600);
83 
84 /*
85  * Util/helpers:
86  */
87 
88 int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk)
89 {
90 	struct property *prop;
91 	const char *name;
92 	struct clk_bulk_data *local;
93 	int i = 0, ret, count;
94 
95 	count = of_property_count_strings(dev->of_node, "clock-names");
96 	if (count < 1)
97 		return 0;
98 
99 	local = devm_kcalloc(dev, sizeof(struct clk_bulk_data *),
100 		count, GFP_KERNEL);
101 	if (!local)
102 		return -ENOMEM;
103 
104 	of_property_for_each_string(dev->of_node, "clock-names", prop, name) {
105 		local[i].id = devm_kstrdup(dev, name, GFP_KERNEL);
106 		if (!local[i].id) {
107 			devm_kfree(dev, local);
108 			return -ENOMEM;
109 		}
110 
111 		i++;
112 	}
113 
114 	ret = devm_clk_bulk_get(dev, count, local);
115 
116 	if (ret) {
117 		for (i = 0; i < count; i++)
118 			devm_kfree(dev, (void *) local[i].id);
119 		devm_kfree(dev, local);
120 
121 		return ret;
122 	}
123 
124 	*bulk = local;
125 	return count;
126 }
127 
128 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
129 		const char *name)
130 {
131 	int i;
132 	char n[32];
133 
134 	snprintf(n, sizeof(n), "%s_clk", name);
135 
136 	for (i = 0; bulk && i < count; i++) {
137 		if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
138 			return bulk[i].clk;
139 	}
140 
141 
142 	return NULL;
143 }
144 
145 struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
146 {
147 	struct clk *clk;
148 	char name2[32];
149 
150 	clk = devm_clk_get(&pdev->dev, name);
151 	if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
152 		return clk;
153 
154 	snprintf(name2, sizeof(name2), "%s_clk", name);
155 
156 	clk = devm_clk_get(&pdev->dev, name2);
157 	if (!IS_ERR(clk))
158 		dev_warn(&pdev->dev, "Using legacy clk name binding.  Use "
159 				"\"%s\" instead of \"%s\"\n", name, name2);
160 
161 	return clk;
162 }
163 
164 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
165 		const char *dbgname)
166 {
167 	struct resource *res;
168 	unsigned long size;
169 	void __iomem *ptr;
170 
171 	if (name)
172 		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
173 	else
174 		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
175 
176 	if (!res) {
177 		DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
178 		return ERR_PTR(-EINVAL);
179 	}
180 
181 	size = resource_size(res);
182 
183 	ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
184 	if (!ptr) {
185 		DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
186 		return ERR_PTR(-ENOMEM);
187 	}
188 
189 	if (reglog)
190 		printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
191 
192 	return ptr;
193 }
194 
195 void msm_writel(u32 data, void __iomem *addr)
196 {
197 	if (reglog)
198 		printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
199 	writel(data, addr);
200 }
201 
202 u32 msm_readl(const void __iomem *addr)
203 {
204 	u32 val = readl(addr);
205 	if (reglog)
206 		pr_err("IO:R %p %08x\n", addr, val);
207 	return val;
208 }
209 
210 struct msm_vblank_work {
211 	struct work_struct work;
212 	int crtc_id;
213 	bool enable;
214 	struct msm_drm_private *priv;
215 };
216 
217 static void vblank_ctrl_worker(struct work_struct *work)
218 {
219 	struct msm_vblank_work *vbl_work = container_of(work,
220 						struct msm_vblank_work, work);
221 	struct msm_drm_private *priv = vbl_work->priv;
222 	struct msm_kms *kms = priv->kms;
223 
224 	if (vbl_work->enable)
225 		kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
226 	else
227 		kms->funcs->disable_vblank(kms,	priv->crtcs[vbl_work->crtc_id]);
228 
229 	kfree(vbl_work);
230 }
231 
232 static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
233 					int crtc_id, bool enable)
234 {
235 	struct msm_vblank_work *vbl_work;
236 
237 	vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
238 	if (!vbl_work)
239 		return -ENOMEM;
240 
241 	INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
242 
243 	vbl_work->crtc_id = crtc_id;
244 	vbl_work->enable = enable;
245 	vbl_work->priv = priv;
246 
247 	queue_work(priv->wq, &vbl_work->work);
248 
249 	return 0;
250 }
251 
252 static int msm_drm_uninit(struct device *dev)
253 {
254 	struct platform_device *pdev = to_platform_device(dev);
255 	struct drm_device *ddev = platform_get_drvdata(pdev);
256 	struct msm_drm_private *priv = ddev->dev_private;
257 	struct msm_kms *kms = priv->kms;
258 	struct msm_mdss *mdss = priv->mdss;
259 	int i;
260 
261 	/* We must cancel and cleanup any pending vblank enable/disable
262 	 * work before drm_irq_uninstall() to avoid work re-enabling an
263 	 * irq after uninstall has disabled it.
264 	 */
265 
266 	flush_workqueue(priv->wq);
267 	destroy_workqueue(priv->wq);
268 
269 	/* clean up event worker threads */
270 	for (i = 0; i < priv->num_crtcs; i++) {
271 		if (priv->event_thread[i].thread) {
272 			kthread_destroy_worker(&priv->event_thread[i].worker);
273 			priv->event_thread[i].thread = NULL;
274 		}
275 	}
276 
277 	msm_gem_shrinker_cleanup(ddev);
278 
279 	drm_kms_helper_poll_fini(ddev);
280 
281 	drm_dev_unregister(ddev);
282 
283 	msm_perf_debugfs_cleanup(priv);
284 	msm_rd_debugfs_cleanup(priv);
285 
286 #ifdef CONFIG_DRM_FBDEV_EMULATION
287 	if (fbdev && priv->fbdev)
288 		msm_fbdev_free(ddev);
289 #endif
290 	drm_atomic_helper_shutdown(ddev);
291 	drm_mode_config_cleanup(ddev);
292 
293 	pm_runtime_get_sync(dev);
294 	drm_irq_uninstall(ddev);
295 	pm_runtime_put_sync(dev);
296 
297 	if (kms && kms->funcs)
298 		kms->funcs->destroy(kms);
299 
300 	if (priv->vram.paddr) {
301 		unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
302 		drm_mm_takedown(&priv->vram.mm);
303 		dma_free_attrs(dev, priv->vram.size, NULL,
304 			       priv->vram.paddr, attrs);
305 	}
306 
307 	component_unbind_all(dev, ddev);
308 
309 	if (mdss && mdss->funcs)
310 		mdss->funcs->destroy(ddev);
311 
312 	ddev->dev_private = NULL;
313 	drm_dev_put(ddev);
314 
315 	kfree(priv);
316 
317 	return 0;
318 }
319 
320 #define KMS_MDP4 4
321 #define KMS_MDP5 5
322 #define KMS_DPU  3
323 
324 static int get_mdp_ver(struct platform_device *pdev)
325 {
326 	struct device *dev = &pdev->dev;
327 
328 	return (int) (unsigned long) of_device_get_match_data(dev);
329 }
330 
331 #include <linux/of_address.h>
332 
333 bool msm_use_mmu(struct drm_device *dev)
334 {
335 	struct msm_drm_private *priv = dev->dev_private;
336 
337 	/* a2xx comes with its own MMU */
338 	return priv->is_a2xx || iommu_present(&platform_bus_type);
339 }
340 
341 static int msm_init_vram(struct drm_device *dev)
342 {
343 	struct msm_drm_private *priv = dev->dev_private;
344 	struct device_node *node;
345 	unsigned long size = 0;
346 	int ret = 0;
347 
348 	/* In the device-tree world, we could have a 'memory-region'
349 	 * phandle, which gives us a link to our "vram".  Allocating
350 	 * is all nicely abstracted behind the dma api, but we need
351 	 * to know the entire size to allocate it all in one go. There
352 	 * are two cases:
353 	 *  1) device with no IOMMU, in which case we need exclusive
354 	 *     access to a VRAM carveout big enough for all gpu
355 	 *     buffers
356 	 *  2) device with IOMMU, but where the bootloader puts up
357 	 *     a splash screen.  In this case, the VRAM carveout
358 	 *     need only be large enough for fbdev fb.  But we need
359 	 *     exclusive access to the buffer to avoid the kernel
360 	 *     using those pages for other purposes (which appears
361 	 *     as corruption on screen before we have a chance to
362 	 *     load and do initial modeset)
363 	 */
364 
365 	node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
366 	if (node) {
367 		struct resource r;
368 		ret = of_address_to_resource(node, 0, &r);
369 		of_node_put(node);
370 		if (ret)
371 			return ret;
372 		size = r.end - r.start;
373 		DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
374 
375 		/* if we have no IOMMU, then we need to use carveout allocator.
376 		 * Grab the entire CMA chunk carved out in early startup in
377 		 * mach-msm:
378 		 */
379 	} else if (!msm_use_mmu(dev)) {
380 		DRM_INFO("using %s VRAM carveout\n", vram);
381 		size = memparse(vram, NULL);
382 	}
383 
384 	if (size) {
385 		unsigned long attrs = 0;
386 		void *p;
387 
388 		priv->vram.size = size;
389 
390 		drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
391 		spin_lock_init(&priv->vram.lock);
392 
393 		attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
394 		attrs |= DMA_ATTR_WRITE_COMBINE;
395 
396 		/* note that for no-kernel-mapping, the vaddr returned
397 		 * is bogus, but non-null if allocation succeeded:
398 		 */
399 		p = dma_alloc_attrs(dev->dev, size,
400 				&priv->vram.paddr, GFP_KERNEL, attrs);
401 		if (!p) {
402 			DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
403 			priv->vram.paddr = 0;
404 			return -ENOMEM;
405 		}
406 
407 		DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
408 				(uint32_t)priv->vram.paddr,
409 				(uint32_t)(priv->vram.paddr + size));
410 	}
411 
412 	return ret;
413 }
414 
415 static int msm_drm_init(struct device *dev, struct drm_driver *drv)
416 {
417 	struct platform_device *pdev = to_platform_device(dev);
418 	struct drm_device *ddev;
419 	struct msm_drm_private *priv;
420 	struct msm_kms *kms;
421 	struct msm_mdss *mdss;
422 	int ret, i;
423 	struct sched_param param;
424 
425 	ddev = drm_dev_alloc(drv, dev);
426 	if (IS_ERR(ddev)) {
427 		DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
428 		return PTR_ERR(ddev);
429 	}
430 
431 	platform_set_drvdata(pdev, ddev);
432 
433 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
434 	if (!priv) {
435 		ret = -ENOMEM;
436 		goto err_put_drm_dev;
437 	}
438 
439 	ddev->dev_private = priv;
440 	priv->dev = ddev;
441 
442 	switch (get_mdp_ver(pdev)) {
443 	case KMS_MDP5:
444 		ret = mdp5_mdss_init(ddev);
445 		break;
446 	case KMS_DPU:
447 		ret = dpu_mdss_init(ddev);
448 		break;
449 	default:
450 		ret = 0;
451 		break;
452 	}
453 	if (ret)
454 		goto err_free_priv;
455 
456 	mdss = priv->mdss;
457 
458 	priv->wq = alloc_ordered_workqueue("msm", 0);
459 
460 	INIT_LIST_HEAD(&priv->inactive_list);
461 
462 	drm_mode_config_init(ddev);
463 
464 	/* Bind all our sub-components: */
465 	ret = component_bind_all(dev, ddev);
466 	if (ret)
467 		goto err_destroy_mdss;
468 
469 	ret = msm_init_vram(ddev);
470 	if (ret)
471 		goto err_msm_uninit;
472 
473 	msm_gem_shrinker_init(ddev);
474 
475 	switch (get_mdp_ver(pdev)) {
476 	case KMS_MDP4:
477 		kms = mdp4_kms_init(ddev);
478 		priv->kms = kms;
479 		break;
480 	case KMS_MDP5:
481 		kms = mdp5_kms_init(ddev);
482 		break;
483 	case KMS_DPU:
484 		kms = dpu_kms_init(ddev);
485 		priv->kms = kms;
486 		break;
487 	default:
488 		/* valid only for the dummy headless case, where of_node=NULL */
489 		WARN_ON(dev->of_node);
490 		kms = NULL;
491 		break;
492 	}
493 
494 	if (IS_ERR(kms)) {
495 		DRM_DEV_ERROR(dev, "failed to load kms\n");
496 		ret = PTR_ERR(kms);
497 		priv->kms = NULL;
498 		goto err_msm_uninit;
499 	}
500 
501 	/* Enable normalization of plane zpos */
502 	ddev->mode_config.normalize_zpos = true;
503 
504 	if (kms) {
505 		ret = kms->funcs->hw_init(kms);
506 		if (ret) {
507 			DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
508 			goto err_msm_uninit;
509 		}
510 	}
511 
512 	ddev->mode_config.funcs = &mode_config_funcs;
513 	ddev->mode_config.helper_private = &mode_config_helper_funcs;
514 
515 	/**
516 	 * this priority was found during empiric testing to have appropriate
517 	 * realtime scheduling to process display updates and interact with
518 	 * other real time and normal priority task
519 	 */
520 	param.sched_priority = 16;
521 	for (i = 0; i < priv->num_crtcs; i++) {
522 		/* initialize event thread */
523 		priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
524 		kthread_init_worker(&priv->event_thread[i].worker);
525 		priv->event_thread[i].dev = ddev;
526 		priv->event_thread[i].thread =
527 			kthread_run(kthread_worker_fn,
528 				&priv->event_thread[i].worker,
529 				"crtc_event:%d", priv->event_thread[i].crtc_id);
530 		if (IS_ERR(priv->event_thread[i].thread)) {
531 			DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
532 			priv->event_thread[i].thread = NULL;
533 			goto err_msm_uninit;
534 		}
535 
536 		ret = sched_setscheduler(priv->event_thread[i].thread,
537 					 SCHED_FIFO, &param);
538 		if (ret)
539 			dev_warn(dev, "event_thread set priority failed:%d\n",
540 				 ret);
541 	}
542 
543 	ret = drm_vblank_init(ddev, priv->num_crtcs);
544 	if (ret < 0) {
545 		DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
546 		goto err_msm_uninit;
547 	}
548 
549 	if (kms) {
550 		pm_runtime_get_sync(dev);
551 		ret = drm_irq_install(ddev, kms->irq);
552 		pm_runtime_put_sync(dev);
553 		if (ret < 0) {
554 			DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
555 			goto err_msm_uninit;
556 		}
557 	}
558 
559 	ret = drm_dev_register(ddev, 0);
560 	if (ret)
561 		goto err_msm_uninit;
562 
563 	drm_mode_config_reset(ddev);
564 
565 #ifdef CONFIG_DRM_FBDEV_EMULATION
566 	if (kms && fbdev)
567 		priv->fbdev = msm_fbdev_init(ddev);
568 #endif
569 
570 	ret = msm_debugfs_late_init(ddev);
571 	if (ret)
572 		goto err_msm_uninit;
573 
574 	drm_kms_helper_poll_init(ddev);
575 
576 	return 0;
577 
578 err_msm_uninit:
579 	msm_drm_uninit(dev);
580 	return ret;
581 err_destroy_mdss:
582 	if (mdss && mdss->funcs)
583 		mdss->funcs->destroy(ddev);
584 err_free_priv:
585 	kfree(priv);
586 err_put_drm_dev:
587 	drm_dev_put(ddev);
588 	return ret;
589 }
590 
591 /*
592  * DRM operations:
593  */
594 
595 static void load_gpu(struct drm_device *dev)
596 {
597 	static DEFINE_MUTEX(init_lock);
598 	struct msm_drm_private *priv = dev->dev_private;
599 
600 	mutex_lock(&init_lock);
601 
602 	if (!priv->gpu)
603 		priv->gpu = adreno_load_gpu(dev);
604 
605 	mutex_unlock(&init_lock);
606 }
607 
608 static int context_init(struct drm_device *dev, struct drm_file *file)
609 {
610 	struct msm_file_private *ctx;
611 
612 	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
613 	if (!ctx)
614 		return -ENOMEM;
615 
616 	msm_submitqueue_init(dev, ctx);
617 
618 	file->driver_priv = ctx;
619 
620 	return 0;
621 }
622 
623 static int msm_open(struct drm_device *dev, struct drm_file *file)
624 {
625 	/* For now, load gpu on open.. to avoid the requirement of having
626 	 * firmware in the initrd.
627 	 */
628 	load_gpu(dev);
629 
630 	return context_init(dev, file);
631 }
632 
633 static void context_close(struct msm_file_private *ctx)
634 {
635 	msm_submitqueue_close(ctx);
636 	kfree(ctx);
637 }
638 
639 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
640 {
641 	struct msm_drm_private *priv = dev->dev_private;
642 	struct msm_file_private *ctx = file->driver_priv;
643 
644 	mutex_lock(&dev->struct_mutex);
645 	if (ctx == priv->lastctx)
646 		priv->lastctx = NULL;
647 	mutex_unlock(&dev->struct_mutex);
648 
649 	context_close(ctx);
650 }
651 
652 static irqreturn_t msm_irq(int irq, void *arg)
653 {
654 	struct drm_device *dev = arg;
655 	struct msm_drm_private *priv = dev->dev_private;
656 	struct msm_kms *kms = priv->kms;
657 	BUG_ON(!kms);
658 	return kms->funcs->irq(kms);
659 }
660 
661 static void msm_irq_preinstall(struct drm_device *dev)
662 {
663 	struct msm_drm_private *priv = dev->dev_private;
664 	struct msm_kms *kms = priv->kms;
665 	BUG_ON(!kms);
666 	kms->funcs->irq_preinstall(kms);
667 }
668 
669 static int msm_irq_postinstall(struct drm_device *dev)
670 {
671 	struct msm_drm_private *priv = dev->dev_private;
672 	struct msm_kms *kms = priv->kms;
673 	BUG_ON(!kms);
674 
675 	if (kms->funcs->irq_postinstall)
676 		return kms->funcs->irq_postinstall(kms);
677 
678 	return 0;
679 }
680 
681 static void msm_irq_uninstall(struct drm_device *dev)
682 {
683 	struct msm_drm_private *priv = dev->dev_private;
684 	struct msm_kms *kms = priv->kms;
685 	BUG_ON(!kms);
686 	kms->funcs->irq_uninstall(kms);
687 }
688 
689 static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
690 {
691 	struct msm_drm_private *priv = dev->dev_private;
692 	struct msm_kms *kms = priv->kms;
693 	if (!kms)
694 		return -ENXIO;
695 	DBG("dev=%p, crtc=%u", dev, pipe);
696 	return vblank_ctrl_queue_work(priv, pipe, true);
697 }
698 
699 static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
700 {
701 	struct msm_drm_private *priv = dev->dev_private;
702 	struct msm_kms *kms = priv->kms;
703 	if (!kms)
704 		return;
705 	DBG("dev=%p, crtc=%u", dev, pipe);
706 	vblank_ctrl_queue_work(priv, pipe, false);
707 }
708 
709 /*
710  * DRM ioctls:
711  */
712 
713 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
714 		struct drm_file *file)
715 {
716 	struct msm_drm_private *priv = dev->dev_private;
717 	struct drm_msm_param *args = data;
718 	struct msm_gpu *gpu;
719 
720 	/* for now, we just have 3d pipe.. eventually this would need to
721 	 * be more clever to dispatch to appropriate gpu module:
722 	 */
723 	if (args->pipe != MSM_PIPE_3D0)
724 		return -EINVAL;
725 
726 	gpu = priv->gpu;
727 
728 	if (!gpu)
729 		return -ENXIO;
730 
731 	return gpu->funcs->get_param(gpu, args->param, &args->value);
732 }
733 
734 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
735 		struct drm_file *file)
736 {
737 	struct drm_msm_gem_new *args = data;
738 
739 	if (args->flags & ~MSM_BO_FLAGS) {
740 		DRM_ERROR("invalid flags: %08x\n", args->flags);
741 		return -EINVAL;
742 	}
743 
744 	return msm_gem_new_handle(dev, file, args->size,
745 			args->flags, &args->handle, NULL);
746 }
747 
748 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
749 {
750 	return ktime_set(timeout.tv_sec, timeout.tv_nsec);
751 }
752 
753 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
754 		struct drm_file *file)
755 {
756 	struct drm_msm_gem_cpu_prep *args = data;
757 	struct drm_gem_object *obj;
758 	ktime_t timeout = to_ktime(args->timeout);
759 	int ret;
760 
761 	if (args->op & ~MSM_PREP_FLAGS) {
762 		DRM_ERROR("invalid op: %08x\n", args->op);
763 		return -EINVAL;
764 	}
765 
766 	obj = drm_gem_object_lookup(file, args->handle);
767 	if (!obj)
768 		return -ENOENT;
769 
770 	ret = msm_gem_cpu_prep(obj, args->op, &timeout);
771 
772 	drm_gem_object_put_unlocked(obj);
773 
774 	return ret;
775 }
776 
777 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
778 		struct drm_file *file)
779 {
780 	struct drm_msm_gem_cpu_fini *args = data;
781 	struct drm_gem_object *obj;
782 	int ret;
783 
784 	obj = drm_gem_object_lookup(file, args->handle);
785 	if (!obj)
786 		return -ENOENT;
787 
788 	ret = msm_gem_cpu_fini(obj);
789 
790 	drm_gem_object_put_unlocked(obj);
791 
792 	return ret;
793 }
794 
795 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
796 		struct drm_gem_object *obj, uint64_t *iova)
797 {
798 	struct msm_drm_private *priv = dev->dev_private;
799 
800 	if (!priv->gpu)
801 		return -EINVAL;
802 
803 	/*
804 	 * Don't pin the memory here - just get an address so that userspace can
805 	 * be productive
806 	 */
807 	return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
808 }
809 
810 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
811 		struct drm_file *file)
812 {
813 	struct drm_msm_gem_info *args = data;
814 	struct drm_gem_object *obj;
815 	struct msm_gem_object *msm_obj;
816 	int i, ret = 0;
817 
818 	if (args->pad)
819 		return -EINVAL;
820 
821 	switch (args->info) {
822 	case MSM_INFO_GET_OFFSET:
823 	case MSM_INFO_GET_IOVA:
824 		/* value returned as immediate, not pointer, so len==0: */
825 		if (args->len)
826 			return -EINVAL;
827 		break;
828 	case MSM_INFO_SET_NAME:
829 	case MSM_INFO_GET_NAME:
830 		break;
831 	default:
832 		return -EINVAL;
833 	}
834 
835 	obj = drm_gem_object_lookup(file, args->handle);
836 	if (!obj)
837 		return -ENOENT;
838 
839 	msm_obj = to_msm_bo(obj);
840 
841 	switch (args->info) {
842 	case MSM_INFO_GET_OFFSET:
843 		args->value = msm_gem_mmap_offset(obj);
844 		break;
845 	case MSM_INFO_GET_IOVA:
846 		ret = msm_ioctl_gem_info_iova(dev, obj, &args->value);
847 		break;
848 	case MSM_INFO_SET_NAME:
849 		/* length check should leave room for terminating null: */
850 		if (args->len >= sizeof(msm_obj->name)) {
851 			ret = -EINVAL;
852 			break;
853 		}
854 		if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
855 				   args->len)) {
856 			msm_obj->name[0] = '\0';
857 			ret = -EFAULT;
858 			break;
859 		}
860 		msm_obj->name[args->len] = '\0';
861 		for (i = 0; i < args->len; i++) {
862 			if (!isprint(msm_obj->name[i])) {
863 				msm_obj->name[i] = '\0';
864 				break;
865 			}
866 		}
867 		break;
868 	case MSM_INFO_GET_NAME:
869 		if (args->value && (args->len < strlen(msm_obj->name))) {
870 			ret = -EINVAL;
871 			break;
872 		}
873 		args->len = strlen(msm_obj->name);
874 		if (args->value) {
875 			if (copy_to_user(u64_to_user_ptr(args->value),
876 					 msm_obj->name, args->len))
877 				ret = -EFAULT;
878 		}
879 		break;
880 	}
881 
882 	drm_gem_object_put_unlocked(obj);
883 
884 	return ret;
885 }
886 
887 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
888 		struct drm_file *file)
889 {
890 	struct msm_drm_private *priv = dev->dev_private;
891 	struct drm_msm_wait_fence *args = data;
892 	ktime_t timeout = to_ktime(args->timeout);
893 	struct msm_gpu_submitqueue *queue;
894 	struct msm_gpu *gpu = priv->gpu;
895 	int ret;
896 
897 	if (args->pad) {
898 		DRM_ERROR("invalid pad: %08x\n", args->pad);
899 		return -EINVAL;
900 	}
901 
902 	if (!gpu)
903 		return 0;
904 
905 	queue = msm_submitqueue_get(file->driver_priv, args->queueid);
906 	if (!queue)
907 		return -ENOENT;
908 
909 	ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
910 		true);
911 
912 	msm_submitqueue_put(queue);
913 	return ret;
914 }
915 
916 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
917 		struct drm_file *file)
918 {
919 	struct drm_msm_gem_madvise *args = data;
920 	struct drm_gem_object *obj;
921 	int ret;
922 
923 	switch (args->madv) {
924 	case MSM_MADV_DONTNEED:
925 	case MSM_MADV_WILLNEED:
926 		break;
927 	default:
928 		return -EINVAL;
929 	}
930 
931 	ret = mutex_lock_interruptible(&dev->struct_mutex);
932 	if (ret)
933 		return ret;
934 
935 	obj = drm_gem_object_lookup(file, args->handle);
936 	if (!obj) {
937 		ret = -ENOENT;
938 		goto unlock;
939 	}
940 
941 	ret = msm_gem_madvise(obj, args->madv);
942 	if (ret >= 0) {
943 		args->retained = ret;
944 		ret = 0;
945 	}
946 
947 	drm_gem_object_put(obj);
948 
949 unlock:
950 	mutex_unlock(&dev->struct_mutex);
951 	return ret;
952 }
953 
954 
955 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
956 		struct drm_file *file)
957 {
958 	struct drm_msm_submitqueue *args = data;
959 
960 	if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
961 		return -EINVAL;
962 
963 	return msm_submitqueue_create(dev, file->driver_priv, args->prio,
964 		args->flags, &args->id);
965 }
966 
967 
968 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
969 		struct drm_file *file)
970 {
971 	u32 id = *(u32 *) data;
972 
973 	return msm_submitqueue_remove(file->driver_priv, id);
974 }
975 
976 static const struct drm_ioctl_desc msm_ioctls[] = {
977 	DRM_IOCTL_DEF_DRV(MSM_GET_PARAM,    msm_ioctl_get_param,    DRM_AUTH|DRM_RENDER_ALLOW),
978 	DRM_IOCTL_DEF_DRV(MSM_GEM_NEW,      msm_ioctl_gem_new,      DRM_AUTH|DRM_RENDER_ALLOW),
979 	DRM_IOCTL_DEF_DRV(MSM_GEM_INFO,     msm_ioctl_gem_info,     DRM_AUTH|DRM_RENDER_ALLOW),
980 	DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
981 	DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
982 	DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT,   msm_ioctl_gem_submit,   DRM_AUTH|DRM_RENDER_ALLOW),
983 	DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE,   msm_ioctl_wait_fence,   DRM_AUTH|DRM_RENDER_ALLOW),
984 	DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE,  msm_ioctl_gem_madvise,  DRM_AUTH|DRM_RENDER_ALLOW),
985 	DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW,   msm_ioctl_submitqueue_new,   DRM_AUTH|DRM_RENDER_ALLOW),
986 	DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_AUTH|DRM_RENDER_ALLOW),
987 };
988 
989 static const struct vm_operations_struct vm_ops = {
990 	.fault = msm_gem_fault,
991 	.open = drm_gem_vm_open,
992 	.close = drm_gem_vm_close,
993 };
994 
995 static const struct file_operations fops = {
996 	.owner              = THIS_MODULE,
997 	.open               = drm_open,
998 	.release            = drm_release,
999 	.unlocked_ioctl     = drm_ioctl,
1000 	.compat_ioctl       = drm_compat_ioctl,
1001 	.poll               = drm_poll,
1002 	.read               = drm_read,
1003 	.llseek             = no_llseek,
1004 	.mmap               = msm_gem_mmap,
1005 };
1006 
1007 static struct drm_driver msm_driver = {
1008 	.driver_features    = DRIVER_GEM |
1009 				DRIVER_PRIME |
1010 				DRIVER_RENDER |
1011 				DRIVER_ATOMIC |
1012 				DRIVER_MODESET,
1013 	.open               = msm_open,
1014 	.postclose           = msm_postclose,
1015 	.lastclose          = drm_fb_helper_lastclose,
1016 	.irq_handler        = msm_irq,
1017 	.irq_preinstall     = msm_irq_preinstall,
1018 	.irq_postinstall    = msm_irq_postinstall,
1019 	.irq_uninstall      = msm_irq_uninstall,
1020 	.enable_vblank      = msm_enable_vblank,
1021 	.disable_vblank     = msm_disable_vblank,
1022 	.gem_free_object    = msm_gem_free_object,
1023 	.gem_vm_ops         = &vm_ops,
1024 	.dumb_create        = msm_gem_dumb_create,
1025 	.dumb_map_offset    = msm_gem_dumb_map_offset,
1026 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1027 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1028 	.gem_prime_export   = drm_gem_prime_export,
1029 	.gem_prime_import   = drm_gem_prime_import,
1030 	.gem_prime_res_obj  = msm_gem_prime_res_obj,
1031 	.gem_prime_pin      = msm_gem_prime_pin,
1032 	.gem_prime_unpin    = msm_gem_prime_unpin,
1033 	.gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
1034 	.gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1035 	.gem_prime_vmap     = msm_gem_prime_vmap,
1036 	.gem_prime_vunmap   = msm_gem_prime_vunmap,
1037 	.gem_prime_mmap     = msm_gem_prime_mmap,
1038 #ifdef CONFIG_DEBUG_FS
1039 	.debugfs_init       = msm_debugfs_init,
1040 #endif
1041 	.ioctls             = msm_ioctls,
1042 	.num_ioctls         = ARRAY_SIZE(msm_ioctls),
1043 	.fops               = &fops,
1044 	.name               = "msm",
1045 	.desc               = "MSM Snapdragon DRM",
1046 	.date               = "20130625",
1047 	.major              = MSM_VERSION_MAJOR,
1048 	.minor              = MSM_VERSION_MINOR,
1049 	.patchlevel         = MSM_VERSION_PATCHLEVEL,
1050 };
1051 
1052 #ifdef CONFIG_PM_SLEEP
1053 static int msm_pm_suspend(struct device *dev)
1054 {
1055 	struct drm_device *ddev = dev_get_drvdata(dev);
1056 	struct msm_drm_private *priv = ddev->dev_private;
1057 
1058 	if (WARN_ON(priv->pm_state))
1059 		drm_atomic_state_put(priv->pm_state);
1060 
1061 	priv->pm_state = drm_atomic_helper_suspend(ddev);
1062 	if (IS_ERR(priv->pm_state)) {
1063 		int ret = PTR_ERR(priv->pm_state);
1064 		DRM_ERROR("Failed to suspend dpu, %d\n", ret);
1065 		return ret;
1066 	}
1067 
1068 	return 0;
1069 }
1070 
1071 static int msm_pm_resume(struct device *dev)
1072 {
1073 	struct drm_device *ddev = dev_get_drvdata(dev);
1074 	struct msm_drm_private *priv = ddev->dev_private;
1075 	int ret;
1076 
1077 	if (WARN_ON(!priv->pm_state))
1078 		return -ENOENT;
1079 
1080 	ret = drm_atomic_helper_resume(ddev, priv->pm_state);
1081 	if (!ret)
1082 		priv->pm_state = NULL;
1083 
1084 	return ret;
1085 }
1086 #endif
1087 
1088 #ifdef CONFIG_PM
1089 static int msm_runtime_suspend(struct device *dev)
1090 {
1091 	struct drm_device *ddev = dev_get_drvdata(dev);
1092 	struct msm_drm_private *priv = ddev->dev_private;
1093 	struct msm_mdss *mdss = priv->mdss;
1094 
1095 	DBG("");
1096 
1097 	if (mdss && mdss->funcs)
1098 		return mdss->funcs->disable(mdss);
1099 
1100 	return 0;
1101 }
1102 
1103 static int msm_runtime_resume(struct device *dev)
1104 {
1105 	struct drm_device *ddev = dev_get_drvdata(dev);
1106 	struct msm_drm_private *priv = ddev->dev_private;
1107 	struct msm_mdss *mdss = priv->mdss;
1108 
1109 	DBG("");
1110 
1111 	if (mdss && mdss->funcs)
1112 		return mdss->funcs->enable(mdss);
1113 
1114 	return 0;
1115 }
1116 #endif
1117 
1118 static const struct dev_pm_ops msm_pm_ops = {
1119 	SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1120 	SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1121 };
1122 
1123 /*
1124  * Componentized driver support:
1125  */
1126 
1127 /*
1128  * NOTE: duplication of the same code as exynos or imx (or probably any other).
1129  * so probably some room for some helpers
1130  */
1131 static int compare_of(struct device *dev, void *data)
1132 {
1133 	return dev->of_node == data;
1134 }
1135 
1136 /*
1137  * Identify what components need to be added by parsing what remote-endpoints
1138  * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1139  * is no external component that we need to add since LVDS is within MDP4
1140  * itself.
1141  */
1142 static int add_components_mdp(struct device *mdp_dev,
1143 			      struct component_match **matchptr)
1144 {
1145 	struct device_node *np = mdp_dev->of_node;
1146 	struct device_node *ep_node;
1147 	struct device *master_dev;
1148 
1149 	/*
1150 	 * on MDP4 based platforms, the MDP platform device is the component
1151 	 * master that adds other display interface components to itself.
1152 	 *
1153 	 * on MDP5 based platforms, the MDSS platform device is the component
1154 	 * master that adds MDP5 and other display interface components to
1155 	 * itself.
1156 	 */
1157 	if (of_device_is_compatible(np, "qcom,mdp4"))
1158 		master_dev = mdp_dev;
1159 	else
1160 		master_dev = mdp_dev->parent;
1161 
1162 	for_each_endpoint_of_node(np, ep_node) {
1163 		struct device_node *intf;
1164 		struct of_endpoint ep;
1165 		int ret;
1166 
1167 		ret = of_graph_parse_endpoint(ep_node, &ep);
1168 		if (ret) {
1169 			DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1170 			of_node_put(ep_node);
1171 			return ret;
1172 		}
1173 
1174 		/*
1175 		 * The LCDC/LVDS port on MDP4 is a speacial case where the
1176 		 * remote-endpoint isn't a component that we need to add
1177 		 */
1178 		if (of_device_is_compatible(np, "qcom,mdp4") &&
1179 		    ep.port == 0)
1180 			continue;
1181 
1182 		/*
1183 		 * It's okay if some of the ports don't have a remote endpoint
1184 		 * specified. It just means that the port isn't connected to
1185 		 * any external interface.
1186 		 */
1187 		intf = of_graph_get_remote_port_parent(ep_node);
1188 		if (!intf)
1189 			continue;
1190 
1191 		if (of_device_is_available(intf))
1192 			drm_of_component_match_add(master_dev, matchptr,
1193 						   compare_of, intf);
1194 
1195 		of_node_put(intf);
1196 	}
1197 
1198 	return 0;
1199 }
1200 
1201 static int compare_name_mdp(struct device *dev, void *data)
1202 {
1203 	return (strstr(dev_name(dev), "mdp") != NULL);
1204 }
1205 
1206 static int add_display_components(struct device *dev,
1207 				  struct component_match **matchptr)
1208 {
1209 	struct device *mdp_dev;
1210 	int ret;
1211 
1212 	/*
1213 	 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1214 	 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1215 	 * Populate the children devices, find the MDP5/DPU node, and then add
1216 	 * the interfaces to our components list.
1217 	 */
1218 	if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
1219 	    of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss")) {
1220 		ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1221 		if (ret) {
1222 			DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1223 			return ret;
1224 		}
1225 
1226 		mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1227 		if (!mdp_dev) {
1228 			DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1229 			of_platform_depopulate(dev);
1230 			return -ENODEV;
1231 		}
1232 
1233 		put_device(mdp_dev);
1234 
1235 		/* add the MDP component itself */
1236 		drm_of_component_match_add(dev, matchptr, compare_of,
1237 					   mdp_dev->of_node);
1238 	} else {
1239 		/* MDP4 */
1240 		mdp_dev = dev;
1241 	}
1242 
1243 	ret = add_components_mdp(mdp_dev, matchptr);
1244 	if (ret)
1245 		of_platform_depopulate(dev);
1246 
1247 	return ret;
1248 }
1249 
1250 /*
1251  * We don't know what's the best binding to link the gpu with the drm device.
1252  * Fow now, we just hunt for all the possible gpus that we support, and add them
1253  * as components.
1254  */
1255 static const struct of_device_id msm_gpu_match[] = {
1256 	{ .compatible = "qcom,adreno" },
1257 	{ .compatible = "qcom,adreno-3xx" },
1258 	{ .compatible = "amd,imageon" },
1259 	{ .compatible = "qcom,kgsl-3d0" },
1260 	{ },
1261 };
1262 
1263 static int add_gpu_components(struct device *dev,
1264 			      struct component_match **matchptr)
1265 {
1266 	struct device_node *np;
1267 
1268 	np = of_find_matching_node(NULL, msm_gpu_match);
1269 	if (!np)
1270 		return 0;
1271 
1272 	drm_of_component_match_add(dev, matchptr, compare_of, np);
1273 
1274 	of_node_put(np);
1275 
1276 	return 0;
1277 }
1278 
1279 static int msm_drm_bind(struct device *dev)
1280 {
1281 	return msm_drm_init(dev, &msm_driver);
1282 }
1283 
1284 static void msm_drm_unbind(struct device *dev)
1285 {
1286 	msm_drm_uninit(dev);
1287 }
1288 
1289 static const struct component_master_ops msm_drm_ops = {
1290 	.bind = msm_drm_bind,
1291 	.unbind = msm_drm_unbind,
1292 };
1293 
1294 /*
1295  * Platform driver:
1296  */
1297 
1298 static int msm_pdev_probe(struct platform_device *pdev)
1299 {
1300 	struct component_match *match = NULL;
1301 	int ret;
1302 
1303 	if (get_mdp_ver(pdev)) {
1304 		ret = add_display_components(&pdev->dev, &match);
1305 		if (ret)
1306 			return ret;
1307 	}
1308 
1309 	ret = add_gpu_components(&pdev->dev, &match);
1310 	if (ret)
1311 		return ret;
1312 
1313 	/* on all devices that I am aware of, iommu's which can map
1314 	 * any address the cpu can see are used:
1315 	 */
1316 	ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1317 	if (ret)
1318 		return ret;
1319 
1320 	return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1321 }
1322 
1323 static int msm_pdev_remove(struct platform_device *pdev)
1324 {
1325 	component_master_del(&pdev->dev, &msm_drm_ops);
1326 	of_platform_depopulate(&pdev->dev);
1327 
1328 	return 0;
1329 }
1330 
1331 static const struct of_device_id dt_match[] = {
1332 	{ .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1333 	{ .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1334 	{ .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1335 	{}
1336 };
1337 MODULE_DEVICE_TABLE(of, dt_match);
1338 
1339 static struct platform_driver msm_platform_driver = {
1340 	.probe      = msm_pdev_probe,
1341 	.remove     = msm_pdev_remove,
1342 	.driver     = {
1343 		.name   = "msm",
1344 		.of_match_table = dt_match,
1345 		.pm     = &msm_pm_ops,
1346 	},
1347 };
1348 
1349 static int __init msm_drm_register(void)
1350 {
1351 	if (!modeset)
1352 		return -EINVAL;
1353 
1354 	DBG("init");
1355 	msm_mdp_register();
1356 	msm_dpu_register();
1357 	msm_dsi_register();
1358 	msm_edp_register();
1359 	msm_hdmi_register();
1360 	adreno_register();
1361 	return platform_driver_register(&msm_platform_driver);
1362 }
1363 
1364 static void __exit msm_drm_unregister(void)
1365 {
1366 	DBG("fini");
1367 	platform_driver_unregister(&msm_platform_driver);
1368 	msm_hdmi_unregister();
1369 	adreno_unregister();
1370 	msm_edp_unregister();
1371 	msm_dsi_unregister();
1372 	msm_mdp_unregister();
1373 	msm_dpu_unregister();
1374 }
1375 
1376 module_init(msm_drm_register);
1377 module_exit(msm_drm_unregister);
1378 
1379 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1380 MODULE_DESCRIPTION("MSM DRM Driver");
1381 MODULE_LICENSE("GPL");
1382