1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/dma-mapping.h> 9 #include <linux/kthread.h> 10 #include <linux/sched/mm.h> 11 #include <linux/uaccess.h> 12 #include <uapi/linux/sched/types.h> 13 14 #include <drm/drm_drv.h> 15 #include <drm/drm_file.h> 16 #include <drm/drm_ioctl.h> 17 #include <drm/drm_prime.h> 18 #include <drm/drm_of.h> 19 #include <drm/drm_vblank.h> 20 21 #include "disp/msm_disp_snapshot.h" 22 #include "msm_drv.h" 23 #include "msm_debugfs.h" 24 #include "msm_fence.h" 25 #include "msm_gem.h" 26 #include "msm_gpu.h" 27 #include "msm_kms.h" 28 #include "adreno/adreno_gpu.h" 29 30 /* 31 * MSM driver version: 32 * - 1.0.0 - initial interface 33 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers 34 * - 1.2.0 - adds explicit fence support for submit ioctl 35 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW + 36 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for 37 * MSM_GEM_INFO ioctl. 38 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get 39 * GEM object's debug name 40 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl 41 * - 1.6.0 - Syncobj support 42 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count 43 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx) 44 */ 45 #define MSM_VERSION_MAJOR 1 46 #define MSM_VERSION_MINOR 8 47 #define MSM_VERSION_PATCHLEVEL 0 48 49 static const struct drm_mode_config_funcs mode_config_funcs = { 50 .fb_create = msm_framebuffer_create, 51 .output_poll_changed = drm_fb_helper_output_poll_changed, 52 .atomic_check = drm_atomic_helper_check, 53 .atomic_commit = drm_atomic_helper_commit, 54 }; 55 56 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = { 57 .atomic_commit_tail = msm_atomic_commit_tail, 58 }; 59 60 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING 61 static bool reglog = false; 62 MODULE_PARM_DESC(reglog, "Enable register read/write logging"); 63 module_param(reglog, bool, 0600); 64 #else 65 #define reglog 0 66 #endif 67 68 #ifdef CONFIG_DRM_FBDEV_EMULATION 69 static bool fbdev = true; 70 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer"); 71 module_param(fbdev, bool, 0600); 72 #endif 73 74 static char *vram = "16m"; 75 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)"); 76 module_param(vram, charp, 0); 77 78 bool dumpstate = false; 79 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors"); 80 module_param(dumpstate, bool, 0600); 81 82 static bool modeset = true; 83 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)"); 84 module_param(modeset, bool, 0600); 85 86 /* 87 * Util/helpers: 88 */ 89 90 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 91 const char *name) 92 { 93 int i; 94 char n[32]; 95 96 snprintf(n, sizeof(n), "%s_clk", name); 97 98 for (i = 0; bulk && i < count; i++) { 99 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n)) 100 return bulk[i].clk; 101 } 102 103 104 return NULL; 105 } 106 107 struct clk *msm_clk_get(struct platform_device *pdev, const char *name) 108 { 109 struct clk *clk; 110 char name2[32]; 111 112 clk = devm_clk_get(&pdev->dev, name); 113 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER) 114 return clk; 115 116 snprintf(name2, sizeof(name2), "%s_clk", name); 117 118 clk = devm_clk_get(&pdev->dev, name2); 119 if (!IS_ERR(clk)) 120 dev_warn(&pdev->dev, "Using legacy clk name binding. Use " 121 "\"%s\" instead of \"%s\"\n", name, name2); 122 123 return clk; 124 } 125 126 static void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name, 127 const char *dbgname, bool quiet, phys_addr_t *psize) 128 { 129 struct resource *res; 130 unsigned long size; 131 void __iomem *ptr; 132 133 if (name) 134 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 135 else 136 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 137 138 if (!res) { 139 if (!quiet) 140 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name); 141 return ERR_PTR(-EINVAL); 142 } 143 144 size = resource_size(res); 145 146 ptr = devm_ioremap(&pdev->dev, res->start, size); 147 if (!ptr) { 148 if (!quiet) 149 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name); 150 return ERR_PTR(-ENOMEM); 151 } 152 153 if (reglog) 154 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size); 155 156 if (psize) 157 *psize = size; 158 159 return ptr; 160 } 161 162 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, 163 const char *dbgname) 164 { 165 return _msm_ioremap(pdev, name, dbgname, false, NULL); 166 } 167 168 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name, 169 const char *dbgname) 170 { 171 return _msm_ioremap(pdev, name, dbgname, true, NULL); 172 } 173 174 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, 175 const char *dbgname, phys_addr_t *psize) 176 { 177 return _msm_ioremap(pdev, name, dbgname, false, psize); 178 } 179 180 void msm_writel(u32 data, void __iomem *addr) 181 { 182 if (reglog) 183 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data); 184 writel(data, addr); 185 } 186 187 u32 msm_readl(const void __iomem *addr) 188 { 189 u32 val = readl(addr); 190 if (reglog) 191 pr_err("IO:R %p %08x\n", addr, val); 192 return val; 193 } 194 195 void msm_rmw(void __iomem *addr, u32 mask, u32 or) 196 { 197 u32 val = msm_readl(addr); 198 199 val &= ~mask; 200 msm_writel(val | or, addr); 201 } 202 203 static irqreturn_t msm_irq(int irq, void *arg) 204 { 205 struct drm_device *dev = arg; 206 struct msm_drm_private *priv = dev->dev_private; 207 struct msm_kms *kms = priv->kms; 208 209 BUG_ON(!kms); 210 211 return kms->funcs->irq(kms); 212 } 213 214 static void msm_irq_preinstall(struct drm_device *dev) 215 { 216 struct msm_drm_private *priv = dev->dev_private; 217 struct msm_kms *kms = priv->kms; 218 219 BUG_ON(!kms); 220 221 kms->funcs->irq_preinstall(kms); 222 } 223 224 static int msm_irq_postinstall(struct drm_device *dev) 225 { 226 struct msm_drm_private *priv = dev->dev_private; 227 struct msm_kms *kms = priv->kms; 228 229 BUG_ON(!kms); 230 231 if (kms->funcs->irq_postinstall) 232 return kms->funcs->irq_postinstall(kms); 233 234 return 0; 235 } 236 237 static int msm_irq_install(struct drm_device *dev, unsigned int irq) 238 { 239 int ret; 240 241 if (irq == IRQ_NOTCONNECTED) 242 return -ENOTCONN; 243 244 msm_irq_preinstall(dev); 245 246 ret = request_irq(irq, msm_irq, 0, dev->driver->name, dev); 247 if (ret) 248 return ret; 249 250 ret = msm_irq_postinstall(dev); 251 if (ret) { 252 free_irq(irq, dev); 253 return ret; 254 } 255 256 return 0; 257 } 258 259 static void msm_irq_uninstall(struct drm_device *dev) 260 { 261 struct msm_drm_private *priv = dev->dev_private; 262 struct msm_kms *kms = priv->kms; 263 264 kms->funcs->irq_uninstall(kms); 265 free_irq(kms->irq, dev); 266 } 267 268 struct msm_vblank_work { 269 struct work_struct work; 270 int crtc_id; 271 bool enable; 272 struct msm_drm_private *priv; 273 }; 274 275 static void vblank_ctrl_worker(struct work_struct *work) 276 { 277 struct msm_vblank_work *vbl_work = container_of(work, 278 struct msm_vblank_work, work); 279 struct msm_drm_private *priv = vbl_work->priv; 280 struct msm_kms *kms = priv->kms; 281 282 if (vbl_work->enable) 283 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]); 284 else 285 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]); 286 287 kfree(vbl_work); 288 } 289 290 static int vblank_ctrl_queue_work(struct msm_drm_private *priv, 291 int crtc_id, bool enable) 292 { 293 struct msm_vblank_work *vbl_work; 294 295 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC); 296 if (!vbl_work) 297 return -ENOMEM; 298 299 INIT_WORK(&vbl_work->work, vblank_ctrl_worker); 300 301 vbl_work->crtc_id = crtc_id; 302 vbl_work->enable = enable; 303 vbl_work->priv = priv; 304 305 queue_work(priv->wq, &vbl_work->work); 306 307 return 0; 308 } 309 310 static int msm_drm_uninit(struct device *dev) 311 { 312 struct platform_device *pdev = to_platform_device(dev); 313 struct drm_device *ddev = platform_get_drvdata(pdev); 314 struct msm_drm_private *priv = ddev->dev_private; 315 struct msm_kms *kms = priv->kms; 316 struct msm_mdss *mdss = priv->mdss; 317 int i; 318 319 /* 320 * Shutdown the hw if we're far enough along where things might be on. 321 * If we run this too early, we'll end up panicking in any variety of 322 * places. Since we don't register the drm device until late in 323 * msm_drm_init, drm_dev->registered is used as an indicator that the 324 * shutdown will be successful. 325 */ 326 if (ddev->registered) { 327 drm_dev_unregister(ddev); 328 drm_atomic_helper_shutdown(ddev); 329 } 330 331 /* We must cancel and cleanup any pending vblank enable/disable 332 * work before msm_irq_uninstall() to avoid work re-enabling an 333 * irq after uninstall has disabled it. 334 */ 335 336 flush_workqueue(priv->wq); 337 338 /* clean up event worker threads */ 339 for (i = 0; i < priv->num_crtcs; i++) { 340 if (priv->event_thread[i].worker) 341 kthread_destroy_worker(priv->event_thread[i].worker); 342 } 343 344 msm_gem_shrinker_cleanup(ddev); 345 346 drm_kms_helper_poll_fini(ddev); 347 348 msm_perf_debugfs_cleanup(priv); 349 msm_rd_debugfs_cleanup(priv); 350 351 #ifdef CONFIG_DRM_FBDEV_EMULATION 352 if (fbdev && priv->fbdev) 353 msm_fbdev_free(ddev); 354 #endif 355 356 msm_disp_snapshot_destroy(ddev); 357 358 drm_mode_config_cleanup(ddev); 359 360 pm_runtime_get_sync(dev); 361 msm_irq_uninstall(ddev); 362 pm_runtime_put_sync(dev); 363 364 if (kms && kms->funcs) 365 kms->funcs->destroy(kms); 366 367 if (priv->vram.paddr) { 368 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING; 369 drm_mm_takedown(&priv->vram.mm); 370 dma_free_attrs(dev, priv->vram.size, NULL, 371 priv->vram.paddr, attrs); 372 } 373 374 component_unbind_all(dev, ddev); 375 376 if (mdss && mdss->funcs) 377 mdss->funcs->destroy(ddev); 378 379 ddev->dev_private = NULL; 380 drm_dev_put(ddev); 381 382 destroy_workqueue(priv->wq); 383 kfree(priv); 384 385 return 0; 386 } 387 388 #define KMS_MDP4 4 389 #define KMS_MDP5 5 390 #define KMS_DPU 3 391 392 static int get_mdp_ver(struct platform_device *pdev) 393 { 394 struct device *dev = &pdev->dev; 395 396 return (int) (unsigned long) of_device_get_match_data(dev); 397 } 398 399 #include <linux/of_address.h> 400 401 bool msm_use_mmu(struct drm_device *dev) 402 { 403 struct msm_drm_private *priv = dev->dev_private; 404 405 /* a2xx comes with its own MMU */ 406 return priv->is_a2xx || iommu_present(&platform_bus_type); 407 } 408 409 static int msm_init_vram(struct drm_device *dev) 410 { 411 struct msm_drm_private *priv = dev->dev_private; 412 struct device_node *node; 413 unsigned long size = 0; 414 int ret = 0; 415 416 /* In the device-tree world, we could have a 'memory-region' 417 * phandle, which gives us a link to our "vram". Allocating 418 * is all nicely abstracted behind the dma api, but we need 419 * to know the entire size to allocate it all in one go. There 420 * are two cases: 421 * 1) device with no IOMMU, in which case we need exclusive 422 * access to a VRAM carveout big enough for all gpu 423 * buffers 424 * 2) device with IOMMU, but where the bootloader puts up 425 * a splash screen. In this case, the VRAM carveout 426 * need only be large enough for fbdev fb. But we need 427 * exclusive access to the buffer to avoid the kernel 428 * using those pages for other purposes (which appears 429 * as corruption on screen before we have a chance to 430 * load and do initial modeset) 431 */ 432 433 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0); 434 if (node) { 435 struct resource r; 436 ret = of_address_to_resource(node, 0, &r); 437 of_node_put(node); 438 if (ret) 439 return ret; 440 size = r.end - r.start; 441 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start); 442 443 /* if we have no IOMMU, then we need to use carveout allocator. 444 * Grab the entire CMA chunk carved out in early startup in 445 * mach-msm: 446 */ 447 } else if (!msm_use_mmu(dev)) { 448 DRM_INFO("using %s VRAM carveout\n", vram); 449 size = memparse(vram, NULL); 450 } 451 452 if (size) { 453 unsigned long attrs = 0; 454 void *p; 455 456 priv->vram.size = size; 457 458 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1); 459 spin_lock_init(&priv->vram.lock); 460 461 attrs |= DMA_ATTR_NO_KERNEL_MAPPING; 462 attrs |= DMA_ATTR_WRITE_COMBINE; 463 464 /* note that for no-kernel-mapping, the vaddr returned 465 * is bogus, but non-null if allocation succeeded: 466 */ 467 p = dma_alloc_attrs(dev->dev, size, 468 &priv->vram.paddr, GFP_KERNEL, attrs); 469 if (!p) { 470 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n"); 471 priv->vram.paddr = 0; 472 return -ENOMEM; 473 } 474 475 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n", 476 (uint32_t)priv->vram.paddr, 477 (uint32_t)(priv->vram.paddr + size)); 478 } 479 480 return ret; 481 } 482 483 static int msm_drm_init(struct device *dev, const struct drm_driver *drv) 484 { 485 struct platform_device *pdev = to_platform_device(dev); 486 struct drm_device *ddev; 487 struct msm_drm_private *priv; 488 struct msm_kms *kms; 489 struct msm_mdss *mdss; 490 int ret, i; 491 492 ddev = drm_dev_alloc(drv, dev); 493 if (IS_ERR(ddev)) { 494 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n"); 495 return PTR_ERR(ddev); 496 } 497 498 platform_set_drvdata(pdev, ddev); 499 500 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 501 if (!priv) { 502 ret = -ENOMEM; 503 goto err_put_drm_dev; 504 } 505 506 ddev->dev_private = priv; 507 priv->dev = ddev; 508 509 switch (get_mdp_ver(pdev)) { 510 case KMS_MDP5: 511 ret = mdp5_mdss_init(ddev); 512 break; 513 case KMS_DPU: 514 ret = dpu_mdss_init(ddev); 515 break; 516 default: 517 ret = 0; 518 break; 519 } 520 if (ret) 521 goto err_free_priv; 522 523 mdss = priv->mdss; 524 525 priv->wq = alloc_ordered_workqueue("msm", 0); 526 priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD; 527 528 INIT_LIST_HEAD(&priv->objects); 529 mutex_init(&priv->obj_lock); 530 531 INIT_LIST_HEAD(&priv->inactive_willneed); 532 INIT_LIST_HEAD(&priv->inactive_dontneed); 533 INIT_LIST_HEAD(&priv->inactive_unpinned); 534 mutex_init(&priv->mm_lock); 535 536 /* Teach lockdep about lock ordering wrt. shrinker: */ 537 fs_reclaim_acquire(GFP_KERNEL); 538 might_lock(&priv->mm_lock); 539 fs_reclaim_release(GFP_KERNEL); 540 541 drm_mode_config_init(ddev); 542 543 ret = msm_init_vram(ddev); 544 if (ret) 545 goto err_destroy_mdss; 546 547 /* Bind all our sub-components: */ 548 ret = component_bind_all(dev, ddev); 549 if (ret) 550 goto err_destroy_mdss; 551 552 dma_set_max_seg_size(dev, UINT_MAX); 553 554 msm_gem_shrinker_init(ddev); 555 556 switch (get_mdp_ver(pdev)) { 557 case KMS_MDP4: 558 kms = mdp4_kms_init(ddev); 559 priv->kms = kms; 560 break; 561 case KMS_MDP5: 562 kms = mdp5_kms_init(ddev); 563 break; 564 case KMS_DPU: 565 kms = dpu_kms_init(ddev); 566 priv->kms = kms; 567 break; 568 default: 569 /* valid only for the dummy headless case, where of_node=NULL */ 570 WARN_ON(dev->of_node); 571 kms = NULL; 572 break; 573 } 574 575 if (IS_ERR(kms)) { 576 DRM_DEV_ERROR(dev, "failed to load kms\n"); 577 ret = PTR_ERR(kms); 578 priv->kms = NULL; 579 goto err_msm_uninit; 580 } 581 582 /* Enable normalization of plane zpos */ 583 ddev->mode_config.normalize_zpos = true; 584 585 if (kms) { 586 kms->dev = ddev; 587 ret = kms->funcs->hw_init(kms); 588 if (ret) { 589 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret); 590 goto err_msm_uninit; 591 } 592 } 593 594 ddev->mode_config.funcs = &mode_config_funcs; 595 ddev->mode_config.helper_private = &mode_config_helper_funcs; 596 597 for (i = 0; i < priv->num_crtcs; i++) { 598 /* initialize event thread */ 599 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id; 600 priv->event_thread[i].dev = ddev; 601 priv->event_thread[i].worker = kthread_create_worker(0, 602 "crtc_event:%d", priv->event_thread[i].crtc_id); 603 if (IS_ERR(priv->event_thread[i].worker)) { 604 ret = PTR_ERR(priv->event_thread[i].worker); 605 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n"); 606 ret = PTR_ERR(priv->event_thread[i].worker); 607 goto err_msm_uninit; 608 } 609 610 sched_set_fifo(priv->event_thread[i].worker->task); 611 } 612 613 ret = drm_vblank_init(ddev, priv->num_crtcs); 614 if (ret < 0) { 615 DRM_DEV_ERROR(dev, "failed to initialize vblank\n"); 616 goto err_msm_uninit; 617 } 618 619 if (kms) { 620 pm_runtime_get_sync(dev); 621 ret = msm_irq_install(ddev, kms->irq); 622 pm_runtime_put_sync(dev); 623 if (ret < 0) { 624 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n"); 625 goto err_msm_uninit; 626 } 627 } 628 629 ret = drm_dev_register(ddev, 0); 630 if (ret) 631 goto err_msm_uninit; 632 633 ret = msm_disp_snapshot_init(ddev); 634 if (ret) 635 DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret); 636 637 drm_mode_config_reset(ddev); 638 639 #ifdef CONFIG_DRM_FBDEV_EMULATION 640 if (kms && fbdev) 641 priv->fbdev = msm_fbdev_init(ddev); 642 #endif 643 644 ret = msm_debugfs_late_init(ddev); 645 if (ret) 646 goto err_msm_uninit; 647 648 drm_kms_helper_poll_init(ddev); 649 650 return 0; 651 652 err_msm_uninit: 653 msm_drm_uninit(dev); 654 return ret; 655 err_destroy_mdss: 656 if (mdss && mdss->funcs) 657 mdss->funcs->destroy(ddev); 658 err_free_priv: 659 kfree(priv); 660 err_put_drm_dev: 661 drm_dev_put(ddev); 662 platform_set_drvdata(pdev, NULL); 663 return ret; 664 } 665 666 /* 667 * DRM operations: 668 */ 669 670 static void load_gpu(struct drm_device *dev) 671 { 672 static DEFINE_MUTEX(init_lock); 673 struct msm_drm_private *priv = dev->dev_private; 674 675 mutex_lock(&init_lock); 676 677 if (!priv->gpu) 678 priv->gpu = adreno_load_gpu(dev); 679 680 mutex_unlock(&init_lock); 681 } 682 683 static int context_init(struct drm_device *dev, struct drm_file *file) 684 { 685 struct msm_drm_private *priv = dev->dev_private; 686 struct msm_file_private *ctx; 687 688 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 689 if (!ctx) 690 return -ENOMEM; 691 692 kref_init(&ctx->ref); 693 msm_submitqueue_init(dev, ctx); 694 695 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current); 696 file->driver_priv = ctx; 697 698 return 0; 699 } 700 701 static int msm_open(struct drm_device *dev, struct drm_file *file) 702 { 703 /* For now, load gpu on open.. to avoid the requirement of having 704 * firmware in the initrd. 705 */ 706 load_gpu(dev); 707 708 return context_init(dev, file); 709 } 710 711 static void context_close(struct msm_file_private *ctx) 712 { 713 msm_submitqueue_close(ctx); 714 msm_file_private_put(ctx); 715 } 716 717 static void msm_postclose(struct drm_device *dev, struct drm_file *file) 718 { 719 struct msm_drm_private *priv = dev->dev_private; 720 struct msm_file_private *ctx = file->driver_priv; 721 722 mutex_lock(&dev->struct_mutex); 723 if (ctx == priv->lastctx) 724 priv->lastctx = NULL; 725 mutex_unlock(&dev->struct_mutex); 726 727 context_close(ctx); 728 } 729 730 int msm_crtc_enable_vblank(struct drm_crtc *crtc) 731 { 732 struct drm_device *dev = crtc->dev; 733 unsigned int pipe = crtc->index; 734 struct msm_drm_private *priv = dev->dev_private; 735 struct msm_kms *kms = priv->kms; 736 if (!kms) 737 return -ENXIO; 738 drm_dbg_vbl(dev, "crtc=%u", pipe); 739 return vblank_ctrl_queue_work(priv, pipe, true); 740 } 741 742 void msm_crtc_disable_vblank(struct drm_crtc *crtc) 743 { 744 struct drm_device *dev = crtc->dev; 745 unsigned int pipe = crtc->index; 746 struct msm_drm_private *priv = dev->dev_private; 747 struct msm_kms *kms = priv->kms; 748 if (!kms) 749 return; 750 drm_dbg_vbl(dev, "crtc=%u", pipe); 751 vblank_ctrl_queue_work(priv, pipe, false); 752 } 753 754 /* 755 * DRM ioctls: 756 */ 757 758 static int msm_ioctl_get_param(struct drm_device *dev, void *data, 759 struct drm_file *file) 760 { 761 struct msm_drm_private *priv = dev->dev_private; 762 struct drm_msm_param *args = data; 763 struct msm_gpu *gpu; 764 765 /* for now, we just have 3d pipe.. eventually this would need to 766 * be more clever to dispatch to appropriate gpu module: 767 */ 768 if (args->pipe != MSM_PIPE_3D0) 769 return -EINVAL; 770 771 gpu = priv->gpu; 772 773 if (!gpu) 774 return -ENXIO; 775 776 return gpu->funcs->get_param(gpu, args->param, &args->value); 777 } 778 779 static int msm_ioctl_gem_new(struct drm_device *dev, void *data, 780 struct drm_file *file) 781 { 782 struct drm_msm_gem_new *args = data; 783 784 if (args->flags & ~MSM_BO_FLAGS) { 785 DRM_ERROR("invalid flags: %08x\n", args->flags); 786 return -EINVAL; 787 } 788 789 return msm_gem_new_handle(dev, file, args->size, 790 args->flags, &args->handle, NULL); 791 } 792 793 static inline ktime_t to_ktime(struct drm_msm_timespec timeout) 794 { 795 return ktime_set(timeout.tv_sec, timeout.tv_nsec); 796 } 797 798 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, 799 struct drm_file *file) 800 { 801 struct drm_msm_gem_cpu_prep *args = data; 802 struct drm_gem_object *obj; 803 ktime_t timeout = to_ktime(args->timeout); 804 int ret; 805 806 if (args->op & ~MSM_PREP_FLAGS) { 807 DRM_ERROR("invalid op: %08x\n", args->op); 808 return -EINVAL; 809 } 810 811 obj = drm_gem_object_lookup(file, args->handle); 812 if (!obj) 813 return -ENOENT; 814 815 ret = msm_gem_cpu_prep(obj, args->op, &timeout); 816 817 drm_gem_object_put(obj); 818 819 return ret; 820 } 821 822 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, 823 struct drm_file *file) 824 { 825 struct drm_msm_gem_cpu_fini *args = data; 826 struct drm_gem_object *obj; 827 int ret; 828 829 obj = drm_gem_object_lookup(file, args->handle); 830 if (!obj) 831 return -ENOENT; 832 833 ret = msm_gem_cpu_fini(obj); 834 835 drm_gem_object_put(obj); 836 837 return ret; 838 } 839 840 static int msm_ioctl_gem_info_iova(struct drm_device *dev, 841 struct drm_file *file, struct drm_gem_object *obj, 842 uint64_t *iova) 843 { 844 struct msm_drm_private *priv = dev->dev_private; 845 struct msm_file_private *ctx = file->driver_priv; 846 847 if (!priv->gpu) 848 return -EINVAL; 849 850 /* 851 * Don't pin the memory here - just get an address so that userspace can 852 * be productive 853 */ 854 return msm_gem_get_iova(obj, ctx->aspace, iova); 855 } 856 857 static int msm_ioctl_gem_info(struct drm_device *dev, void *data, 858 struct drm_file *file) 859 { 860 struct drm_msm_gem_info *args = data; 861 struct drm_gem_object *obj; 862 struct msm_gem_object *msm_obj; 863 int i, ret = 0; 864 865 if (args->pad) 866 return -EINVAL; 867 868 switch (args->info) { 869 case MSM_INFO_GET_OFFSET: 870 case MSM_INFO_GET_IOVA: 871 /* value returned as immediate, not pointer, so len==0: */ 872 if (args->len) 873 return -EINVAL; 874 break; 875 case MSM_INFO_SET_NAME: 876 case MSM_INFO_GET_NAME: 877 break; 878 default: 879 return -EINVAL; 880 } 881 882 obj = drm_gem_object_lookup(file, args->handle); 883 if (!obj) 884 return -ENOENT; 885 886 msm_obj = to_msm_bo(obj); 887 888 switch (args->info) { 889 case MSM_INFO_GET_OFFSET: 890 args->value = msm_gem_mmap_offset(obj); 891 break; 892 case MSM_INFO_GET_IOVA: 893 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value); 894 break; 895 case MSM_INFO_SET_NAME: 896 /* length check should leave room for terminating null: */ 897 if (args->len >= sizeof(msm_obj->name)) { 898 ret = -EINVAL; 899 break; 900 } 901 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value), 902 args->len)) { 903 msm_obj->name[0] = '\0'; 904 ret = -EFAULT; 905 break; 906 } 907 msm_obj->name[args->len] = '\0'; 908 for (i = 0; i < args->len; i++) { 909 if (!isprint(msm_obj->name[i])) { 910 msm_obj->name[i] = '\0'; 911 break; 912 } 913 } 914 break; 915 case MSM_INFO_GET_NAME: 916 if (args->value && (args->len < strlen(msm_obj->name))) { 917 ret = -EINVAL; 918 break; 919 } 920 args->len = strlen(msm_obj->name); 921 if (args->value) { 922 if (copy_to_user(u64_to_user_ptr(args->value), 923 msm_obj->name, args->len)) 924 ret = -EFAULT; 925 } 926 break; 927 } 928 929 drm_gem_object_put(obj); 930 931 return ret; 932 } 933 934 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, 935 struct drm_file *file) 936 { 937 struct msm_drm_private *priv = dev->dev_private; 938 struct drm_msm_wait_fence *args = data; 939 ktime_t timeout = to_ktime(args->timeout); 940 struct msm_gpu_submitqueue *queue; 941 struct msm_gpu *gpu = priv->gpu; 942 struct dma_fence *fence; 943 int ret; 944 945 if (args->pad) { 946 DRM_ERROR("invalid pad: %08x\n", args->pad); 947 return -EINVAL; 948 } 949 950 if (!gpu) 951 return 0; 952 953 queue = msm_submitqueue_get(file->driver_priv, args->queueid); 954 if (!queue) 955 return -ENOENT; 956 957 /* 958 * Map submitqueue scoped "seqno" (which is actually an idr key) 959 * back to underlying dma-fence 960 * 961 * The fence is removed from the fence_idr when the submit is 962 * retired, so if the fence is not found it means there is nothing 963 * to wait for 964 */ 965 ret = mutex_lock_interruptible(&queue->lock); 966 if (ret) 967 return ret; 968 fence = idr_find(&queue->fence_idr, args->fence); 969 if (fence) 970 fence = dma_fence_get_rcu(fence); 971 mutex_unlock(&queue->lock); 972 973 if (!fence) 974 return 0; 975 976 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout)); 977 if (ret == 0) { 978 ret = -ETIMEDOUT; 979 } else if (ret != -ERESTARTSYS) { 980 ret = 0; 981 } 982 983 dma_fence_put(fence); 984 msm_submitqueue_put(queue); 985 986 return ret; 987 } 988 989 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data, 990 struct drm_file *file) 991 { 992 struct drm_msm_gem_madvise *args = data; 993 struct drm_gem_object *obj; 994 int ret; 995 996 switch (args->madv) { 997 case MSM_MADV_DONTNEED: 998 case MSM_MADV_WILLNEED: 999 break; 1000 default: 1001 return -EINVAL; 1002 } 1003 1004 obj = drm_gem_object_lookup(file, args->handle); 1005 if (!obj) { 1006 return -ENOENT; 1007 } 1008 1009 ret = msm_gem_madvise(obj, args->madv); 1010 if (ret >= 0) { 1011 args->retained = ret; 1012 ret = 0; 1013 } 1014 1015 drm_gem_object_put(obj); 1016 1017 return ret; 1018 } 1019 1020 1021 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data, 1022 struct drm_file *file) 1023 { 1024 struct drm_msm_submitqueue *args = data; 1025 1026 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS) 1027 return -EINVAL; 1028 1029 return msm_submitqueue_create(dev, file->driver_priv, args->prio, 1030 args->flags, &args->id); 1031 } 1032 1033 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data, 1034 struct drm_file *file) 1035 { 1036 return msm_submitqueue_query(dev, file->driver_priv, data); 1037 } 1038 1039 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data, 1040 struct drm_file *file) 1041 { 1042 u32 id = *(u32 *) data; 1043 1044 return msm_submitqueue_remove(file->driver_priv, id); 1045 } 1046 1047 static const struct drm_ioctl_desc msm_ioctls[] = { 1048 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW), 1049 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW), 1050 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW), 1051 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW), 1052 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW), 1053 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW), 1054 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW), 1055 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW), 1056 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW), 1057 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW), 1058 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW), 1059 }; 1060 1061 DEFINE_DRM_GEM_FOPS(fops); 1062 1063 static const struct drm_driver msm_driver = { 1064 .driver_features = DRIVER_GEM | 1065 DRIVER_RENDER | 1066 DRIVER_ATOMIC | 1067 DRIVER_MODESET | 1068 DRIVER_SYNCOBJ, 1069 .open = msm_open, 1070 .postclose = msm_postclose, 1071 .lastclose = drm_fb_helper_lastclose, 1072 .dumb_create = msm_gem_dumb_create, 1073 .dumb_map_offset = msm_gem_dumb_map_offset, 1074 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1075 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1076 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, 1077 .gem_prime_mmap = drm_gem_prime_mmap, 1078 #ifdef CONFIG_DEBUG_FS 1079 .debugfs_init = msm_debugfs_init, 1080 #endif 1081 .ioctls = msm_ioctls, 1082 .num_ioctls = ARRAY_SIZE(msm_ioctls), 1083 .fops = &fops, 1084 .name = "msm", 1085 .desc = "MSM Snapdragon DRM", 1086 .date = "20130625", 1087 .major = MSM_VERSION_MAJOR, 1088 .minor = MSM_VERSION_MINOR, 1089 .patchlevel = MSM_VERSION_PATCHLEVEL, 1090 }; 1091 1092 static int __maybe_unused msm_runtime_suspend(struct device *dev) 1093 { 1094 struct drm_device *ddev = dev_get_drvdata(dev); 1095 struct msm_drm_private *priv = ddev->dev_private; 1096 struct msm_mdss *mdss = priv->mdss; 1097 1098 DBG(""); 1099 1100 if (mdss && mdss->funcs) 1101 return mdss->funcs->disable(mdss); 1102 1103 return 0; 1104 } 1105 1106 static int __maybe_unused msm_runtime_resume(struct device *dev) 1107 { 1108 struct drm_device *ddev = dev_get_drvdata(dev); 1109 struct msm_drm_private *priv = ddev->dev_private; 1110 struct msm_mdss *mdss = priv->mdss; 1111 1112 DBG(""); 1113 1114 if (mdss && mdss->funcs) 1115 return mdss->funcs->enable(mdss); 1116 1117 return 0; 1118 } 1119 1120 static int __maybe_unused msm_pm_suspend(struct device *dev) 1121 { 1122 1123 if (pm_runtime_suspended(dev)) 1124 return 0; 1125 1126 return msm_runtime_suspend(dev); 1127 } 1128 1129 static int __maybe_unused msm_pm_resume(struct device *dev) 1130 { 1131 if (pm_runtime_suspended(dev)) 1132 return 0; 1133 1134 return msm_runtime_resume(dev); 1135 } 1136 1137 static int __maybe_unused msm_pm_prepare(struct device *dev) 1138 { 1139 struct drm_device *ddev = dev_get_drvdata(dev); 1140 struct msm_drm_private *priv = ddev ? ddev->dev_private : NULL; 1141 1142 if (!priv || !priv->kms) 1143 return 0; 1144 1145 return drm_mode_config_helper_suspend(ddev); 1146 } 1147 1148 static void __maybe_unused msm_pm_complete(struct device *dev) 1149 { 1150 struct drm_device *ddev = dev_get_drvdata(dev); 1151 struct msm_drm_private *priv = ddev ? ddev->dev_private : NULL; 1152 1153 if (!priv || !priv->kms) 1154 return; 1155 1156 drm_mode_config_helper_resume(ddev); 1157 } 1158 1159 static const struct dev_pm_ops msm_pm_ops = { 1160 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume) 1161 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL) 1162 .prepare = msm_pm_prepare, 1163 .complete = msm_pm_complete, 1164 }; 1165 1166 /* 1167 * Componentized driver support: 1168 */ 1169 1170 /* 1171 * NOTE: duplication of the same code as exynos or imx (or probably any other). 1172 * so probably some room for some helpers 1173 */ 1174 static int compare_of(struct device *dev, void *data) 1175 { 1176 return dev->of_node == data; 1177 } 1178 1179 /* 1180 * Identify what components need to be added by parsing what remote-endpoints 1181 * our MDP output ports are connected to. In the case of LVDS on MDP4, there 1182 * is no external component that we need to add since LVDS is within MDP4 1183 * itself. 1184 */ 1185 static int add_components_mdp(struct device *mdp_dev, 1186 struct component_match **matchptr) 1187 { 1188 struct device_node *np = mdp_dev->of_node; 1189 struct device_node *ep_node; 1190 struct device *master_dev; 1191 1192 /* 1193 * on MDP4 based platforms, the MDP platform device is the component 1194 * master that adds other display interface components to itself. 1195 * 1196 * on MDP5 based platforms, the MDSS platform device is the component 1197 * master that adds MDP5 and other display interface components to 1198 * itself. 1199 */ 1200 if (of_device_is_compatible(np, "qcom,mdp4")) 1201 master_dev = mdp_dev; 1202 else 1203 master_dev = mdp_dev->parent; 1204 1205 for_each_endpoint_of_node(np, ep_node) { 1206 struct device_node *intf; 1207 struct of_endpoint ep; 1208 int ret; 1209 1210 ret = of_graph_parse_endpoint(ep_node, &ep); 1211 if (ret) { 1212 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n"); 1213 of_node_put(ep_node); 1214 return ret; 1215 } 1216 1217 /* 1218 * The LCDC/LVDS port on MDP4 is a speacial case where the 1219 * remote-endpoint isn't a component that we need to add 1220 */ 1221 if (of_device_is_compatible(np, "qcom,mdp4") && 1222 ep.port == 0) 1223 continue; 1224 1225 /* 1226 * It's okay if some of the ports don't have a remote endpoint 1227 * specified. It just means that the port isn't connected to 1228 * any external interface. 1229 */ 1230 intf = of_graph_get_remote_port_parent(ep_node); 1231 if (!intf) 1232 continue; 1233 1234 if (of_device_is_available(intf)) 1235 drm_of_component_match_add(master_dev, matchptr, 1236 compare_of, intf); 1237 1238 of_node_put(intf); 1239 } 1240 1241 return 0; 1242 } 1243 1244 static int compare_name_mdp(struct device *dev, void *data) 1245 { 1246 return (strstr(dev_name(dev), "mdp") != NULL); 1247 } 1248 1249 static int add_display_components(struct platform_device *pdev, 1250 struct component_match **matchptr) 1251 { 1252 struct device *mdp_dev; 1253 struct device *dev = &pdev->dev; 1254 int ret; 1255 1256 /* 1257 * MDP5/DPU based devices don't have a flat hierarchy. There is a top 1258 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc. 1259 * Populate the children devices, find the MDP5/DPU node, and then add 1260 * the interfaces to our components list. 1261 */ 1262 switch (get_mdp_ver(pdev)) { 1263 case KMS_MDP5: 1264 case KMS_DPU: 1265 ret = of_platform_populate(dev->of_node, NULL, NULL, dev); 1266 if (ret) { 1267 DRM_DEV_ERROR(dev, "failed to populate children devices\n"); 1268 return ret; 1269 } 1270 1271 mdp_dev = device_find_child(dev, NULL, compare_name_mdp); 1272 if (!mdp_dev) { 1273 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n"); 1274 of_platform_depopulate(dev); 1275 return -ENODEV; 1276 } 1277 1278 put_device(mdp_dev); 1279 1280 /* add the MDP component itself */ 1281 drm_of_component_match_add(dev, matchptr, compare_of, 1282 mdp_dev->of_node); 1283 break; 1284 case KMS_MDP4: 1285 /* MDP4 */ 1286 mdp_dev = dev; 1287 break; 1288 } 1289 1290 ret = add_components_mdp(mdp_dev, matchptr); 1291 if (ret) 1292 of_platform_depopulate(dev); 1293 1294 return ret; 1295 } 1296 1297 /* 1298 * We don't know what's the best binding to link the gpu with the drm device. 1299 * Fow now, we just hunt for all the possible gpus that we support, and add them 1300 * as components. 1301 */ 1302 static const struct of_device_id msm_gpu_match[] = { 1303 { .compatible = "qcom,adreno" }, 1304 { .compatible = "qcom,adreno-3xx" }, 1305 { .compatible = "amd,imageon" }, 1306 { .compatible = "qcom,kgsl-3d0" }, 1307 { }, 1308 }; 1309 1310 static int add_gpu_components(struct device *dev, 1311 struct component_match **matchptr) 1312 { 1313 struct device_node *np; 1314 1315 np = of_find_matching_node(NULL, msm_gpu_match); 1316 if (!np) 1317 return 0; 1318 1319 if (of_device_is_available(np)) 1320 drm_of_component_match_add(dev, matchptr, compare_of, np); 1321 1322 of_node_put(np); 1323 1324 return 0; 1325 } 1326 1327 static int msm_drm_bind(struct device *dev) 1328 { 1329 return msm_drm_init(dev, &msm_driver); 1330 } 1331 1332 static void msm_drm_unbind(struct device *dev) 1333 { 1334 msm_drm_uninit(dev); 1335 } 1336 1337 static const struct component_master_ops msm_drm_ops = { 1338 .bind = msm_drm_bind, 1339 .unbind = msm_drm_unbind, 1340 }; 1341 1342 /* 1343 * Platform driver: 1344 */ 1345 1346 static int msm_pdev_probe(struct platform_device *pdev) 1347 { 1348 struct component_match *match = NULL; 1349 int ret; 1350 1351 if (get_mdp_ver(pdev)) { 1352 ret = add_display_components(pdev, &match); 1353 if (ret) 1354 return ret; 1355 } 1356 1357 ret = add_gpu_components(&pdev->dev, &match); 1358 if (ret) 1359 goto fail; 1360 1361 /* on all devices that I am aware of, iommu's which can map 1362 * any address the cpu can see are used: 1363 */ 1364 ret = dma_set_mask_and_coherent(&pdev->dev, ~0); 1365 if (ret) 1366 goto fail; 1367 1368 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match); 1369 if (ret) 1370 goto fail; 1371 1372 return 0; 1373 1374 fail: 1375 of_platform_depopulate(&pdev->dev); 1376 return ret; 1377 } 1378 1379 static int msm_pdev_remove(struct platform_device *pdev) 1380 { 1381 component_master_del(&pdev->dev, &msm_drm_ops); 1382 of_platform_depopulate(&pdev->dev); 1383 1384 return 0; 1385 } 1386 1387 static void msm_pdev_shutdown(struct platform_device *pdev) 1388 { 1389 struct drm_device *drm = platform_get_drvdata(pdev); 1390 struct msm_drm_private *priv = drm ? drm->dev_private : NULL; 1391 1392 if (!priv || !priv->kms) 1393 return; 1394 1395 drm_atomic_helper_shutdown(drm); 1396 } 1397 1398 static const struct of_device_id dt_match[] = { 1399 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 }, 1400 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 }, 1401 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU }, 1402 { .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU }, 1403 { .compatible = "qcom,sc7280-mdss", .data = (void *)KMS_DPU }, 1404 { .compatible = "qcom,sm8150-mdss", .data = (void *)KMS_DPU }, 1405 { .compatible = "qcom,sm8250-mdss", .data = (void *)KMS_DPU }, 1406 {} 1407 }; 1408 MODULE_DEVICE_TABLE(of, dt_match); 1409 1410 static struct platform_driver msm_platform_driver = { 1411 .probe = msm_pdev_probe, 1412 .remove = msm_pdev_remove, 1413 .shutdown = msm_pdev_shutdown, 1414 .driver = { 1415 .name = "msm", 1416 .of_match_table = dt_match, 1417 .pm = &msm_pm_ops, 1418 }, 1419 }; 1420 1421 static int __init msm_drm_register(void) 1422 { 1423 if (!modeset) 1424 return -EINVAL; 1425 1426 DBG("init"); 1427 msm_mdp_register(); 1428 msm_dpu_register(); 1429 msm_dsi_register(); 1430 msm_edp_register(); 1431 msm_hdmi_register(); 1432 msm_dp_register(); 1433 adreno_register(); 1434 return platform_driver_register(&msm_platform_driver); 1435 } 1436 1437 static void __exit msm_drm_unregister(void) 1438 { 1439 DBG("fini"); 1440 platform_driver_unregister(&msm_platform_driver); 1441 msm_dp_unregister(); 1442 msm_hdmi_unregister(); 1443 adreno_unregister(); 1444 msm_edp_unregister(); 1445 msm_dsi_unregister(); 1446 msm_mdp_unregister(); 1447 msm_dpu_unregister(); 1448 } 1449 1450 module_init(msm_drm_register); 1451 module_exit(msm_drm_unregister); 1452 1453 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 1454 MODULE_DESCRIPTION("MSM DRM Driver"); 1455 MODULE_LICENSE("GPL"); 1456