1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/dma-mapping.h> 9 #include <linux/kthread.h> 10 #include <linux/sched/mm.h> 11 #include <linux/uaccess.h> 12 #include <uapi/linux/sched/types.h> 13 14 #include <drm/drm_drv.h> 15 #include <drm/drm_file.h> 16 #include <drm/drm_ioctl.h> 17 #include <drm/drm_irq.h> 18 #include <drm/drm_prime.h> 19 #include <drm/drm_of.h> 20 #include <drm/drm_vblank.h> 21 22 #include "msm_drv.h" 23 #include "msm_debugfs.h" 24 #include "msm_fence.h" 25 #include "msm_gem.h" 26 #include "msm_gpu.h" 27 #include "msm_kms.h" 28 #include "adreno/adreno_gpu.h" 29 30 /* 31 * MSM driver version: 32 * - 1.0.0 - initial interface 33 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers 34 * - 1.2.0 - adds explicit fence support for submit ioctl 35 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW + 36 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for 37 * MSM_GEM_INFO ioctl. 38 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get 39 * GEM object's debug name 40 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl 41 * - 1.6.0 - Syncobj support 42 */ 43 #define MSM_VERSION_MAJOR 1 44 #define MSM_VERSION_MINOR 6 45 #define MSM_VERSION_PATCHLEVEL 0 46 47 static const struct drm_mode_config_funcs mode_config_funcs = { 48 .fb_create = msm_framebuffer_create, 49 .output_poll_changed = drm_fb_helper_output_poll_changed, 50 .atomic_check = drm_atomic_helper_check, 51 .atomic_commit = drm_atomic_helper_commit, 52 }; 53 54 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = { 55 .atomic_commit_tail = msm_atomic_commit_tail, 56 }; 57 58 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING 59 static bool reglog = false; 60 MODULE_PARM_DESC(reglog, "Enable register read/write logging"); 61 module_param(reglog, bool, 0600); 62 #else 63 #define reglog 0 64 #endif 65 66 #ifdef CONFIG_DRM_FBDEV_EMULATION 67 static bool fbdev = true; 68 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer"); 69 module_param(fbdev, bool, 0600); 70 #endif 71 72 static char *vram = "16m"; 73 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)"); 74 module_param(vram, charp, 0); 75 76 bool dumpstate = false; 77 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors"); 78 module_param(dumpstate, bool, 0600); 79 80 static bool modeset = true; 81 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)"); 82 module_param(modeset, bool, 0600); 83 84 /* 85 * Util/helpers: 86 */ 87 88 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 89 const char *name) 90 { 91 int i; 92 char n[32]; 93 94 snprintf(n, sizeof(n), "%s_clk", name); 95 96 for (i = 0; bulk && i < count; i++) { 97 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n)) 98 return bulk[i].clk; 99 } 100 101 102 return NULL; 103 } 104 105 struct clk *msm_clk_get(struct platform_device *pdev, const char *name) 106 { 107 struct clk *clk; 108 char name2[32]; 109 110 clk = devm_clk_get(&pdev->dev, name); 111 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER) 112 return clk; 113 114 snprintf(name2, sizeof(name2), "%s_clk", name); 115 116 clk = devm_clk_get(&pdev->dev, name2); 117 if (!IS_ERR(clk)) 118 dev_warn(&pdev->dev, "Using legacy clk name binding. Use " 119 "\"%s\" instead of \"%s\"\n", name, name2); 120 121 return clk; 122 } 123 124 static void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name, 125 const char *dbgname, bool quiet) 126 { 127 struct resource *res; 128 unsigned long size; 129 void __iomem *ptr; 130 131 if (name) 132 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 133 else 134 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 135 136 if (!res) { 137 if (!quiet) 138 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name); 139 return ERR_PTR(-EINVAL); 140 } 141 142 size = resource_size(res); 143 144 ptr = devm_ioremap(&pdev->dev, res->start, size); 145 if (!ptr) { 146 if (!quiet) 147 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name); 148 return ERR_PTR(-ENOMEM); 149 } 150 151 if (reglog) 152 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size); 153 154 return ptr; 155 } 156 157 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, 158 const char *dbgname) 159 { 160 return _msm_ioremap(pdev, name, dbgname, false); 161 } 162 163 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name, 164 const char *dbgname) 165 { 166 return _msm_ioremap(pdev, name, dbgname, true); 167 } 168 169 void msm_writel(u32 data, void __iomem *addr) 170 { 171 if (reglog) 172 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data); 173 writel(data, addr); 174 } 175 176 u32 msm_readl(const void __iomem *addr) 177 { 178 u32 val = readl(addr); 179 if (reglog) 180 pr_err("IO:R %p %08x\n", addr, val); 181 return val; 182 } 183 184 void msm_rmw(void __iomem *addr, u32 mask, u32 or) 185 { 186 u32 val = msm_readl(addr); 187 188 val &= ~mask; 189 msm_writel(val | or, addr); 190 } 191 192 struct msm_vblank_work { 193 struct work_struct work; 194 int crtc_id; 195 bool enable; 196 struct msm_drm_private *priv; 197 }; 198 199 static void vblank_ctrl_worker(struct work_struct *work) 200 { 201 struct msm_vblank_work *vbl_work = container_of(work, 202 struct msm_vblank_work, work); 203 struct msm_drm_private *priv = vbl_work->priv; 204 struct msm_kms *kms = priv->kms; 205 206 if (vbl_work->enable) 207 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]); 208 else 209 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]); 210 211 kfree(vbl_work); 212 } 213 214 static int vblank_ctrl_queue_work(struct msm_drm_private *priv, 215 int crtc_id, bool enable) 216 { 217 struct msm_vblank_work *vbl_work; 218 219 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC); 220 if (!vbl_work) 221 return -ENOMEM; 222 223 INIT_WORK(&vbl_work->work, vblank_ctrl_worker); 224 225 vbl_work->crtc_id = crtc_id; 226 vbl_work->enable = enable; 227 vbl_work->priv = priv; 228 229 queue_work(priv->wq, &vbl_work->work); 230 231 return 0; 232 } 233 234 static int msm_drm_uninit(struct device *dev) 235 { 236 struct platform_device *pdev = to_platform_device(dev); 237 struct drm_device *ddev = platform_get_drvdata(pdev); 238 struct msm_drm_private *priv = ddev->dev_private; 239 struct msm_kms *kms = priv->kms; 240 struct msm_mdss *mdss = priv->mdss; 241 int i; 242 243 /* 244 * Shutdown the hw if we're far enough along where things might be on. 245 * If we run this too early, we'll end up panicking in any variety of 246 * places. Since we don't register the drm device until late in 247 * msm_drm_init, drm_dev->registered is used as an indicator that the 248 * shutdown will be successful. 249 */ 250 if (ddev->registered) { 251 drm_dev_unregister(ddev); 252 drm_atomic_helper_shutdown(ddev); 253 } 254 255 /* We must cancel and cleanup any pending vblank enable/disable 256 * work before drm_irq_uninstall() to avoid work re-enabling an 257 * irq after uninstall has disabled it. 258 */ 259 260 flush_workqueue(priv->wq); 261 262 /* clean up event worker threads */ 263 for (i = 0; i < priv->num_crtcs; i++) { 264 if (priv->event_thread[i].worker) 265 kthread_destroy_worker(priv->event_thread[i].worker); 266 } 267 268 msm_gem_shrinker_cleanup(ddev); 269 270 drm_kms_helper_poll_fini(ddev); 271 272 msm_perf_debugfs_cleanup(priv); 273 msm_rd_debugfs_cleanup(priv); 274 275 #ifdef CONFIG_DRM_FBDEV_EMULATION 276 if (fbdev && priv->fbdev) 277 msm_fbdev_free(ddev); 278 #endif 279 280 drm_mode_config_cleanup(ddev); 281 282 pm_runtime_get_sync(dev); 283 drm_irq_uninstall(ddev); 284 pm_runtime_put_sync(dev); 285 286 if (kms && kms->funcs) 287 kms->funcs->destroy(kms); 288 289 if (priv->vram.paddr) { 290 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING; 291 drm_mm_takedown(&priv->vram.mm); 292 dma_free_attrs(dev, priv->vram.size, NULL, 293 priv->vram.paddr, attrs); 294 } 295 296 component_unbind_all(dev, ddev); 297 298 if (mdss && mdss->funcs) 299 mdss->funcs->destroy(ddev); 300 301 ddev->dev_private = NULL; 302 drm_dev_put(ddev); 303 304 destroy_workqueue(priv->wq); 305 kfree(priv); 306 307 return 0; 308 } 309 310 #define KMS_MDP4 4 311 #define KMS_MDP5 5 312 #define KMS_DPU 3 313 314 static int get_mdp_ver(struct platform_device *pdev) 315 { 316 struct device *dev = &pdev->dev; 317 318 return (int) (unsigned long) of_device_get_match_data(dev); 319 } 320 321 #include <linux/of_address.h> 322 323 bool msm_use_mmu(struct drm_device *dev) 324 { 325 struct msm_drm_private *priv = dev->dev_private; 326 327 /* a2xx comes with its own MMU */ 328 return priv->is_a2xx || iommu_present(&platform_bus_type); 329 } 330 331 static int msm_init_vram(struct drm_device *dev) 332 { 333 struct msm_drm_private *priv = dev->dev_private; 334 struct device_node *node; 335 unsigned long size = 0; 336 int ret = 0; 337 338 /* In the device-tree world, we could have a 'memory-region' 339 * phandle, which gives us a link to our "vram". Allocating 340 * is all nicely abstracted behind the dma api, but we need 341 * to know the entire size to allocate it all in one go. There 342 * are two cases: 343 * 1) device with no IOMMU, in which case we need exclusive 344 * access to a VRAM carveout big enough for all gpu 345 * buffers 346 * 2) device with IOMMU, but where the bootloader puts up 347 * a splash screen. In this case, the VRAM carveout 348 * need only be large enough for fbdev fb. But we need 349 * exclusive access to the buffer to avoid the kernel 350 * using those pages for other purposes (which appears 351 * as corruption on screen before we have a chance to 352 * load and do initial modeset) 353 */ 354 355 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0); 356 if (node) { 357 struct resource r; 358 ret = of_address_to_resource(node, 0, &r); 359 of_node_put(node); 360 if (ret) 361 return ret; 362 size = r.end - r.start; 363 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start); 364 365 /* if we have no IOMMU, then we need to use carveout allocator. 366 * Grab the entire CMA chunk carved out in early startup in 367 * mach-msm: 368 */ 369 } else if (!msm_use_mmu(dev)) { 370 DRM_INFO("using %s VRAM carveout\n", vram); 371 size = memparse(vram, NULL); 372 } 373 374 if (size) { 375 unsigned long attrs = 0; 376 void *p; 377 378 priv->vram.size = size; 379 380 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1); 381 spin_lock_init(&priv->vram.lock); 382 383 attrs |= DMA_ATTR_NO_KERNEL_MAPPING; 384 attrs |= DMA_ATTR_WRITE_COMBINE; 385 386 /* note that for no-kernel-mapping, the vaddr returned 387 * is bogus, but non-null if allocation succeeded: 388 */ 389 p = dma_alloc_attrs(dev->dev, size, 390 &priv->vram.paddr, GFP_KERNEL, attrs); 391 if (!p) { 392 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n"); 393 priv->vram.paddr = 0; 394 return -ENOMEM; 395 } 396 397 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n", 398 (uint32_t)priv->vram.paddr, 399 (uint32_t)(priv->vram.paddr + size)); 400 } 401 402 return ret; 403 } 404 405 static int msm_drm_init(struct device *dev, const struct drm_driver *drv) 406 { 407 struct platform_device *pdev = to_platform_device(dev); 408 struct drm_device *ddev; 409 struct msm_drm_private *priv; 410 struct msm_kms *kms; 411 struct msm_mdss *mdss; 412 int ret, i; 413 414 ddev = drm_dev_alloc(drv, dev); 415 if (IS_ERR(ddev)) { 416 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n"); 417 return PTR_ERR(ddev); 418 } 419 420 platform_set_drvdata(pdev, ddev); 421 422 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 423 if (!priv) { 424 ret = -ENOMEM; 425 goto err_put_drm_dev; 426 } 427 428 ddev->dev_private = priv; 429 priv->dev = ddev; 430 431 switch (get_mdp_ver(pdev)) { 432 case KMS_MDP5: 433 ret = mdp5_mdss_init(ddev); 434 break; 435 case KMS_DPU: 436 ret = dpu_mdss_init(ddev); 437 break; 438 default: 439 ret = 0; 440 break; 441 } 442 if (ret) 443 goto err_free_priv; 444 445 mdss = priv->mdss; 446 447 priv->wq = alloc_ordered_workqueue("msm", 0); 448 449 INIT_LIST_HEAD(&priv->inactive_willneed); 450 INIT_LIST_HEAD(&priv->inactive_dontneed); 451 mutex_init(&priv->mm_lock); 452 453 /* Teach lockdep about lock ordering wrt. shrinker: */ 454 fs_reclaim_acquire(GFP_KERNEL); 455 might_lock(&priv->mm_lock); 456 fs_reclaim_release(GFP_KERNEL); 457 458 drm_mode_config_init(ddev); 459 460 ret = msm_init_vram(ddev); 461 if (ret) 462 goto err_destroy_mdss; 463 464 /* Bind all our sub-components: */ 465 ret = component_bind_all(dev, ddev); 466 if (ret) 467 goto err_destroy_mdss; 468 469 dma_set_max_seg_size(dev, UINT_MAX); 470 471 msm_gem_shrinker_init(ddev); 472 473 switch (get_mdp_ver(pdev)) { 474 case KMS_MDP4: 475 kms = mdp4_kms_init(ddev); 476 priv->kms = kms; 477 break; 478 case KMS_MDP5: 479 kms = mdp5_kms_init(ddev); 480 break; 481 case KMS_DPU: 482 kms = dpu_kms_init(ddev); 483 priv->kms = kms; 484 break; 485 default: 486 /* valid only for the dummy headless case, where of_node=NULL */ 487 WARN_ON(dev->of_node); 488 kms = NULL; 489 break; 490 } 491 492 if (IS_ERR(kms)) { 493 DRM_DEV_ERROR(dev, "failed to load kms\n"); 494 ret = PTR_ERR(kms); 495 priv->kms = NULL; 496 goto err_msm_uninit; 497 } 498 499 /* Enable normalization of plane zpos */ 500 ddev->mode_config.normalize_zpos = true; 501 502 if (kms) { 503 kms->dev = ddev; 504 ret = kms->funcs->hw_init(kms); 505 if (ret) { 506 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret); 507 goto err_msm_uninit; 508 } 509 } 510 511 ddev->mode_config.funcs = &mode_config_funcs; 512 ddev->mode_config.helper_private = &mode_config_helper_funcs; 513 514 for (i = 0; i < priv->num_crtcs; i++) { 515 /* initialize event thread */ 516 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id; 517 priv->event_thread[i].dev = ddev; 518 priv->event_thread[i].worker = kthread_create_worker(0, 519 "crtc_event:%d", priv->event_thread[i].crtc_id); 520 if (IS_ERR(priv->event_thread[i].worker)) { 521 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n"); 522 goto err_msm_uninit; 523 } 524 525 sched_set_fifo(priv->event_thread[i].worker->task); 526 } 527 528 ret = drm_vblank_init(ddev, priv->num_crtcs); 529 if (ret < 0) { 530 DRM_DEV_ERROR(dev, "failed to initialize vblank\n"); 531 goto err_msm_uninit; 532 } 533 534 if (kms) { 535 pm_runtime_get_sync(dev); 536 ret = drm_irq_install(ddev, kms->irq); 537 pm_runtime_put_sync(dev); 538 if (ret < 0) { 539 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n"); 540 goto err_msm_uninit; 541 } 542 } 543 544 ret = drm_dev_register(ddev, 0); 545 if (ret) 546 goto err_msm_uninit; 547 548 drm_mode_config_reset(ddev); 549 550 #ifdef CONFIG_DRM_FBDEV_EMULATION 551 if (kms && fbdev) 552 priv->fbdev = msm_fbdev_init(ddev); 553 #endif 554 555 ret = msm_debugfs_late_init(ddev); 556 if (ret) 557 goto err_msm_uninit; 558 559 drm_kms_helper_poll_init(ddev); 560 561 return 0; 562 563 err_msm_uninit: 564 msm_drm_uninit(dev); 565 return ret; 566 err_destroy_mdss: 567 if (mdss && mdss->funcs) 568 mdss->funcs->destroy(ddev); 569 err_free_priv: 570 kfree(priv); 571 err_put_drm_dev: 572 drm_dev_put(ddev); 573 platform_set_drvdata(pdev, NULL); 574 return ret; 575 } 576 577 /* 578 * DRM operations: 579 */ 580 581 static void load_gpu(struct drm_device *dev) 582 { 583 static DEFINE_MUTEX(init_lock); 584 struct msm_drm_private *priv = dev->dev_private; 585 586 mutex_lock(&init_lock); 587 588 if (!priv->gpu) 589 priv->gpu = adreno_load_gpu(dev); 590 591 mutex_unlock(&init_lock); 592 } 593 594 static int context_init(struct drm_device *dev, struct drm_file *file) 595 { 596 struct msm_drm_private *priv = dev->dev_private; 597 struct msm_file_private *ctx; 598 599 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 600 if (!ctx) 601 return -ENOMEM; 602 603 kref_init(&ctx->ref); 604 msm_submitqueue_init(dev, ctx); 605 606 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current); 607 file->driver_priv = ctx; 608 609 return 0; 610 } 611 612 static int msm_open(struct drm_device *dev, struct drm_file *file) 613 { 614 /* For now, load gpu on open.. to avoid the requirement of having 615 * firmware in the initrd. 616 */ 617 load_gpu(dev); 618 619 return context_init(dev, file); 620 } 621 622 static void context_close(struct msm_file_private *ctx) 623 { 624 msm_submitqueue_close(ctx); 625 msm_file_private_put(ctx); 626 } 627 628 static void msm_postclose(struct drm_device *dev, struct drm_file *file) 629 { 630 struct msm_drm_private *priv = dev->dev_private; 631 struct msm_file_private *ctx = file->driver_priv; 632 633 mutex_lock(&dev->struct_mutex); 634 if (ctx == priv->lastctx) 635 priv->lastctx = NULL; 636 mutex_unlock(&dev->struct_mutex); 637 638 context_close(ctx); 639 } 640 641 static irqreturn_t msm_irq(int irq, void *arg) 642 { 643 struct drm_device *dev = arg; 644 struct msm_drm_private *priv = dev->dev_private; 645 struct msm_kms *kms = priv->kms; 646 BUG_ON(!kms); 647 return kms->funcs->irq(kms); 648 } 649 650 static void msm_irq_preinstall(struct drm_device *dev) 651 { 652 struct msm_drm_private *priv = dev->dev_private; 653 struct msm_kms *kms = priv->kms; 654 BUG_ON(!kms); 655 kms->funcs->irq_preinstall(kms); 656 } 657 658 static int msm_irq_postinstall(struct drm_device *dev) 659 { 660 struct msm_drm_private *priv = dev->dev_private; 661 struct msm_kms *kms = priv->kms; 662 BUG_ON(!kms); 663 664 if (kms->funcs->irq_postinstall) 665 return kms->funcs->irq_postinstall(kms); 666 667 return 0; 668 } 669 670 static void msm_irq_uninstall(struct drm_device *dev) 671 { 672 struct msm_drm_private *priv = dev->dev_private; 673 struct msm_kms *kms = priv->kms; 674 BUG_ON(!kms); 675 kms->funcs->irq_uninstall(kms); 676 } 677 678 int msm_crtc_enable_vblank(struct drm_crtc *crtc) 679 { 680 struct drm_device *dev = crtc->dev; 681 unsigned int pipe = crtc->index; 682 struct msm_drm_private *priv = dev->dev_private; 683 struct msm_kms *kms = priv->kms; 684 if (!kms) 685 return -ENXIO; 686 DBG("dev=%p, crtc=%u", dev, pipe); 687 return vblank_ctrl_queue_work(priv, pipe, true); 688 } 689 690 void msm_crtc_disable_vblank(struct drm_crtc *crtc) 691 { 692 struct drm_device *dev = crtc->dev; 693 unsigned int pipe = crtc->index; 694 struct msm_drm_private *priv = dev->dev_private; 695 struct msm_kms *kms = priv->kms; 696 if (!kms) 697 return; 698 DBG("dev=%p, crtc=%u", dev, pipe); 699 vblank_ctrl_queue_work(priv, pipe, false); 700 } 701 702 /* 703 * DRM ioctls: 704 */ 705 706 static int msm_ioctl_get_param(struct drm_device *dev, void *data, 707 struct drm_file *file) 708 { 709 struct msm_drm_private *priv = dev->dev_private; 710 struct drm_msm_param *args = data; 711 struct msm_gpu *gpu; 712 713 /* for now, we just have 3d pipe.. eventually this would need to 714 * be more clever to dispatch to appropriate gpu module: 715 */ 716 if (args->pipe != MSM_PIPE_3D0) 717 return -EINVAL; 718 719 gpu = priv->gpu; 720 721 if (!gpu) 722 return -ENXIO; 723 724 return gpu->funcs->get_param(gpu, args->param, &args->value); 725 } 726 727 static int msm_ioctl_gem_new(struct drm_device *dev, void *data, 728 struct drm_file *file) 729 { 730 struct drm_msm_gem_new *args = data; 731 732 if (args->flags & ~MSM_BO_FLAGS) { 733 DRM_ERROR("invalid flags: %08x\n", args->flags); 734 return -EINVAL; 735 } 736 737 return msm_gem_new_handle(dev, file, args->size, 738 args->flags, &args->handle, NULL); 739 } 740 741 static inline ktime_t to_ktime(struct drm_msm_timespec timeout) 742 { 743 return ktime_set(timeout.tv_sec, timeout.tv_nsec); 744 } 745 746 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, 747 struct drm_file *file) 748 { 749 struct drm_msm_gem_cpu_prep *args = data; 750 struct drm_gem_object *obj; 751 ktime_t timeout = to_ktime(args->timeout); 752 int ret; 753 754 if (args->op & ~MSM_PREP_FLAGS) { 755 DRM_ERROR("invalid op: %08x\n", args->op); 756 return -EINVAL; 757 } 758 759 obj = drm_gem_object_lookup(file, args->handle); 760 if (!obj) 761 return -ENOENT; 762 763 ret = msm_gem_cpu_prep(obj, args->op, &timeout); 764 765 drm_gem_object_put(obj); 766 767 return ret; 768 } 769 770 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, 771 struct drm_file *file) 772 { 773 struct drm_msm_gem_cpu_fini *args = data; 774 struct drm_gem_object *obj; 775 int ret; 776 777 obj = drm_gem_object_lookup(file, args->handle); 778 if (!obj) 779 return -ENOENT; 780 781 ret = msm_gem_cpu_fini(obj); 782 783 drm_gem_object_put(obj); 784 785 return ret; 786 } 787 788 static int msm_ioctl_gem_info_iova(struct drm_device *dev, 789 struct drm_file *file, struct drm_gem_object *obj, 790 uint64_t *iova) 791 { 792 struct msm_drm_private *priv = dev->dev_private; 793 struct msm_file_private *ctx = file->driver_priv; 794 795 if (!priv->gpu) 796 return -EINVAL; 797 798 /* 799 * Don't pin the memory here - just get an address so that userspace can 800 * be productive 801 */ 802 return msm_gem_get_iova(obj, ctx->aspace, iova); 803 } 804 805 static int msm_ioctl_gem_info(struct drm_device *dev, void *data, 806 struct drm_file *file) 807 { 808 struct drm_msm_gem_info *args = data; 809 struct drm_gem_object *obj; 810 struct msm_gem_object *msm_obj; 811 int i, ret = 0; 812 813 if (args->pad) 814 return -EINVAL; 815 816 switch (args->info) { 817 case MSM_INFO_GET_OFFSET: 818 case MSM_INFO_GET_IOVA: 819 /* value returned as immediate, not pointer, so len==0: */ 820 if (args->len) 821 return -EINVAL; 822 break; 823 case MSM_INFO_SET_NAME: 824 case MSM_INFO_GET_NAME: 825 break; 826 default: 827 return -EINVAL; 828 } 829 830 obj = drm_gem_object_lookup(file, args->handle); 831 if (!obj) 832 return -ENOENT; 833 834 msm_obj = to_msm_bo(obj); 835 836 switch (args->info) { 837 case MSM_INFO_GET_OFFSET: 838 args->value = msm_gem_mmap_offset(obj); 839 break; 840 case MSM_INFO_GET_IOVA: 841 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value); 842 break; 843 case MSM_INFO_SET_NAME: 844 /* length check should leave room for terminating null: */ 845 if (args->len >= sizeof(msm_obj->name)) { 846 ret = -EINVAL; 847 break; 848 } 849 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value), 850 args->len)) { 851 msm_obj->name[0] = '\0'; 852 ret = -EFAULT; 853 break; 854 } 855 msm_obj->name[args->len] = '\0'; 856 for (i = 0; i < args->len; i++) { 857 if (!isprint(msm_obj->name[i])) { 858 msm_obj->name[i] = '\0'; 859 break; 860 } 861 } 862 break; 863 case MSM_INFO_GET_NAME: 864 if (args->value && (args->len < strlen(msm_obj->name))) { 865 ret = -EINVAL; 866 break; 867 } 868 args->len = strlen(msm_obj->name); 869 if (args->value) { 870 if (copy_to_user(u64_to_user_ptr(args->value), 871 msm_obj->name, args->len)) 872 ret = -EFAULT; 873 } 874 break; 875 } 876 877 drm_gem_object_put(obj); 878 879 return ret; 880 } 881 882 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, 883 struct drm_file *file) 884 { 885 struct msm_drm_private *priv = dev->dev_private; 886 struct drm_msm_wait_fence *args = data; 887 ktime_t timeout = to_ktime(args->timeout); 888 struct msm_gpu_submitqueue *queue; 889 struct msm_gpu *gpu = priv->gpu; 890 int ret; 891 892 if (args->pad) { 893 DRM_ERROR("invalid pad: %08x\n", args->pad); 894 return -EINVAL; 895 } 896 897 if (!gpu) 898 return 0; 899 900 queue = msm_submitqueue_get(file->driver_priv, args->queueid); 901 if (!queue) 902 return -ENOENT; 903 904 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout, 905 true); 906 907 msm_submitqueue_put(queue); 908 return ret; 909 } 910 911 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data, 912 struct drm_file *file) 913 { 914 struct drm_msm_gem_madvise *args = data; 915 struct drm_gem_object *obj; 916 int ret; 917 918 switch (args->madv) { 919 case MSM_MADV_DONTNEED: 920 case MSM_MADV_WILLNEED: 921 break; 922 default: 923 return -EINVAL; 924 } 925 926 obj = drm_gem_object_lookup(file, args->handle); 927 if (!obj) { 928 return -ENOENT; 929 } 930 931 ret = msm_gem_madvise(obj, args->madv); 932 if (ret >= 0) { 933 args->retained = ret; 934 ret = 0; 935 } 936 937 drm_gem_object_put(obj); 938 939 return ret; 940 } 941 942 943 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data, 944 struct drm_file *file) 945 { 946 struct drm_msm_submitqueue *args = data; 947 948 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS) 949 return -EINVAL; 950 951 return msm_submitqueue_create(dev, file->driver_priv, args->prio, 952 args->flags, &args->id); 953 } 954 955 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data, 956 struct drm_file *file) 957 { 958 return msm_submitqueue_query(dev, file->driver_priv, data); 959 } 960 961 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data, 962 struct drm_file *file) 963 { 964 u32 id = *(u32 *) data; 965 966 return msm_submitqueue_remove(file->driver_priv, id); 967 } 968 969 static const struct drm_ioctl_desc msm_ioctls[] = { 970 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW), 971 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW), 972 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW), 973 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW), 974 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW), 975 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW), 976 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW), 977 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW), 978 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW), 979 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW), 980 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW), 981 }; 982 983 static const struct file_operations fops = { 984 .owner = THIS_MODULE, 985 .open = drm_open, 986 .release = drm_release, 987 .unlocked_ioctl = drm_ioctl, 988 .compat_ioctl = drm_compat_ioctl, 989 .poll = drm_poll, 990 .read = drm_read, 991 .llseek = no_llseek, 992 .mmap = msm_gem_mmap, 993 }; 994 995 static const struct drm_driver msm_driver = { 996 .driver_features = DRIVER_GEM | 997 DRIVER_RENDER | 998 DRIVER_ATOMIC | 999 DRIVER_MODESET | 1000 DRIVER_SYNCOBJ, 1001 .open = msm_open, 1002 .postclose = msm_postclose, 1003 .lastclose = drm_fb_helper_lastclose, 1004 .irq_handler = msm_irq, 1005 .irq_preinstall = msm_irq_preinstall, 1006 .irq_postinstall = msm_irq_postinstall, 1007 .irq_uninstall = msm_irq_uninstall, 1008 .dumb_create = msm_gem_dumb_create, 1009 .dumb_map_offset = msm_gem_dumb_map_offset, 1010 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1011 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1012 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, 1013 .gem_prime_mmap = msm_gem_prime_mmap, 1014 #ifdef CONFIG_DEBUG_FS 1015 .debugfs_init = msm_debugfs_init, 1016 #endif 1017 .ioctls = msm_ioctls, 1018 .num_ioctls = ARRAY_SIZE(msm_ioctls), 1019 .fops = &fops, 1020 .name = "msm", 1021 .desc = "MSM Snapdragon DRM", 1022 .date = "20130625", 1023 .major = MSM_VERSION_MAJOR, 1024 .minor = MSM_VERSION_MINOR, 1025 .patchlevel = MSM_VERSION_PATCHLEVEL, 1026 }; 1027 1028 static int __maybe_unused msm_runtime_suspend(struct device *dev) 1029 { 1030 struct drm_device *ddev = dev_get_drvdata(dev); 1031 struct msm_drm_private *priv = ddev->dev_private; 1032 struct msm_mdss *mdss = priv->mdss; 1033 1034 DBG(""); 1035 1036 if (mdss && mdss->funcs) 1037 return mdss->funcs->disable(mdss); 1038 1039 return 0; 1040 } 1041 1042 static int __maybe_unused msm_runtime_resume(struct device *dev) 1043 { 1044 struct drm_device *ddev = dev_get_drvdata(dev); 1045 struct msm_drm_private *priv = ddev->dev_private; 1046 struct msm_mdss *mdss = priv->mdss; 1047 1048 DBG(""); 1049 1050 if (mdss && mdss->funcs) 1051 return mdss->funcs->enable(mdss); 1052 1053 return 0; 1054 } 1055 1056 static int __maybe_unused msm_pm_suspend(struct device *dev) 1057 { 1058 1059 if (pm_runtime_suspended(dev)) 1060 return 0; 1061 1062 return msm_runtime_suspend(dev); 1063 } 1064 1065 static int __maybe_unused msm_pm_resume(struct device *dev) 1066 { 1067 if (pm_runtime_suspended(dev)) 1068 return 0; 1069 1070 return msm_runtime_resume(dev); 1071 } 1072 1073 static int __maybe_unused msm_pm_prepare(struct device *dev) 1074 { 1075 struct drm_device *ddev = dev_get_drvdata(dev); 1076 struct msm_drm_private *priv = ddev ? ddev->dev_private : NULL; 1077 1078 if (!priv || !priv->kms) 1079 return 0; 1080 1081 return drm_mode_config_helper_suspend(ddev); 1082 } 1083 1084 static void __maybe_unused msm_pm_complete(struct device *dev) 1085 { 1086 struct drm_device *ddev = dev_get_drvdata(dev); 1087 struct msm_drm_private *priv = ddev ? ddev->dev_private : NULL; 1088 1089 if (!priv || !priv->kms) 1090 return; 1091 1092 drm_mode_config_helper_resume(ddev); 1093 } 1094 1095 static const struct dev_pm_ops msm_pm_ops = { 1096 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume) 1097 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL) 1098 .prepare = msm_pm_prepare, 1099 .complete = msm_pm_complete, 1100 }; 1101 1102 /* 1103 * Componentized driver support: 1104 */ 1105 1106 /* 1107 * NOTE: duplication of the same code as exynos or imx (or probably any other). 1108 * so probably some room for some helpers 1109 */ 1110 static int compare_of(struct device *dev, void *data) 1111 { 1112 return dev->of_node == data; 1113 } 1114 1115 /* 1116 * Identify what components need to be added by parsing what remote-endpoints 1117 * our MDP output ports are connected to. In the case of LVDS on MDP4, there 1118 * is no external component that we need to add since LVDS is within MDP4 1119 * itself. 1120 */ 1121 static int add_components_mdp(struct device *mdp_dev, 1122 struct component_match **matchptr) 1123 { 1124 struct device_node *np = mdp_dev->of_node; 1125 struct device_node *ep_node; 1126 struct device *master_dev; 1127 1128 /* 1129 * on MDP4 based platforms, the MDP platform device is the component 1130 * master that adds other display interface components to itself. 1131 * 1132 * on MDP5 based platforms, the MDSS platform device is the component 1133 * master that adds MDP5 and other display interface components to 1134 * itself. 1135 */ 1136 if (of_device_is_compatible(np, "qcom,mdp4")) 1137 master_dev = mdp_dev; 1138 else 1139 master_dev = mdp_dev->parent; 1140 1141 for_each_endpoint_of_node(np, ep_node) { 1142 struct device_node *intf; 1143 struct of_endpoint ep; 1144 int ret; 1145 1146 ret = of_graph_parse_endpoint(ep_node, &ep); 1147 if (ret) { 1148 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n"); 1149 of_node_put(ep_node); 1150 return ret; 1151 } 1152 1153 /* 1154 * The LCDC/LVDS port on MDP4 is a speacial case where the 1155 * remote-endpoint isn't a component that we need to add 1156 */ 1157 if (of_device_is_compatible(np, "qcom,mdp4") && 1158 ep.port == 0) 1159 continue; 1160 1161 /* 1162 * It's okay if some of the ports don't have a remote endpoint 1163 * specified. It just means that the port isn't connected to 1164 * any external interface. 1165 */ 1166 intf = of_graph_get_remote_port_parent(ep_node); 1167 if (!intf) 1168 continue; 1169 1170 if (of_device_is_available(intf)) 1171 drm_of_component_match_add(master_dev, matchptr, 1172 compare_of, intf); 1173 1174 of_node_put(intf); 1175 } 1176 1177 return 0; 1178 } 1179 1180 static int compare_name_mdp(struct device *dev, void *data) 1181 { 1182 return (strstr(dev_name(dev), "mdp") != NULL); 1183 } 1184 1185 static int add_display_components(struct device *dev, 1186 struct component_match **matchptr) 1187 { 1188 struct device *mdp_dev; 1189 int ret; 1190 1191 /* 1192 * MDP5/DPU based devices don't have a flat hierarchy. There is a top 1193 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc. 1194 * Populate the children devices, find the MDP5/DPU node, and then add 1195 * the interfaces to our components list. 1196 */ 1197 if (of_device_is_compatible(dev->of_node, "qcom,mdss") || 1198 of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss") || 1199 of_device_is_compatible(dev->of_node, "qcom,sc7180-mdss")) { 1200 ret = of_platform_populate(dev->of_node, NULL, NULL, dev); 1201 if (ret) { 1202 DRM_DEV_ERROR(dev, "failed to populate children devices\n"); 1203 return ret; 1204 } 1205 1206 mdp_dev = device_find_child(dev, NULL, compare_name_mdp); 1207 if (!mdp_dev) { 1208 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n"); 1209 of_platform_depopulate(dev); 1210 return -ENODEV; 1211 } 1212 1213 put_device(mdp_dev); 1214 1215 /* add the MDP component itself */ 1216 drm_of_component_match_add(dev, matchptr, compare_of, 1217 mdp_dev->of_node); 1218 } else { 1219 /* MDP4 */ 1220 mdp_dev = dev; 1221 } 1222 1223 ret = add_components_mdp(mdp_dev, matchptr); 1224 if (ret) 1225 of_platform_depopulate(dev); 1226 1227 return ret; 1228 } 1229 1230 /* 1231 * We don't know what's the best binding to link the gpu with the drm device. 1232 * Fow now, we just hunt for all the possible gpus that we support, and add them 1233 * as components. 1234 */ 1235 static const struct of_device_id msm_gpu_match[] = { 1236 { .compatible = "qcom,adreno" }, 1237 { .compatible = "qcom,adreno-3xx" }, 1238 { .compatible = "amd,imageon" }, 1239 { .compatible = "qcom,kgsl-3d0" }, 1240 { }, 1241 }; 1242 1243 static int add_gpu_components(struct device *dev, 1244 struct component_match **matchptr) 1245 { 1246 struct device_node *np; 1247 1248 np = of_find_matching_node(NULL, msm_gpu_match); 1249 if (!np) 1250 return 0; 1251 1252 if (of_device_is_available(np)) 1253 drm_of_component_match_add(dev, matchptr, compare_of, np); 1254 1255 of_node_put(np); 1256 1257 return 0; 1258 } 1259 1260 static int msm_drm_bind(struct device *dev) 1261 { 1262 return msm_drm_init(dev, &msm_driver); 1263 } 1264 1265 static void msm_drm_unbind(struct device *dev) 1266 { 1267 msm_drm_uninit(dev); 1268 } 1269 1270 static const struct component_master_ops msm_drm_ops = { 1271 .bind = msm_drm_bind, 1272 .unbind = msm_drm_unbind, 1273 }; 1274 1275 /* 1276 * Platform driver: 1277 */ 1278 1279 static int msm_pdev_probe(struct platform_device *pdev) 1280 { 1281 struct component_match *match = NULL; 1282 int ret; 1283 1284 if (get_mdp_ver(pdev)) { 1285 ret = add_display_components(&pdev->dev, &match); 1286 if (ret) 1287 return ret; 1288 } 1289 1290 ret = add_gpu_components(&pdev->dev, &match); 1291 if (ret) 1292 goto fail; 1293 1294 /* on all devices that I am aware of, iommu's which can map 1295 * any address the cpu can see are used: 1296 */ 1297 ret = dma_set_mask_and_coherent(&pdev->dev, ~0); 1298 if (ret) 1299 goto fail; 1300 1301 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match); 1302 if (ret) 1303 goto fail; 1304 1305 return 0; 1306 1307 fail: 1308 of_platform_depopulate(&pdev->dev); 1309 return ret; 1310 } 1311 1312 static int msm_pdev_remove(struct platform_device *pdev) 1313 { 1314 component_master_del(&pdev->dev, &msm_drm_ops); 1315 of_platform_depopulate(&pdev->dev); 1316 1317 return 0; 1318 } 1319 1320 static void msm_pdev_shutdown(struct platform_device *pdev) 1321 { 1322 struct drm_device *drm = platform_get_drvdata(pdev); 1323 struct msm_drm_private *priv = drm ? drm->dev_private : NULL; 1324 1325 if (!priv || !priv->kms) 1326 return; 1327 1328 drm_atomic_helper_shutdown(drm); 1329 } 1330 1331 static const struct of_device_id dt_match[] = { 1332 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 }, 1333 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 }, 1334 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU }, 1335 { .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU }, 1336 {} 1337 }; 1338 MODULE_DEVICE_TABLE(of, dt_match); 1339 1340 static struct platform_driver msm_platform_driver = { 1341 .probe = msm_pdev_probe, 1342 .remove = msm_pdev_remove, 1343 .shutdown = msm_pdev_shutdown, 1344 .driver = { 1345 .name = "msm", 1346 .of_match_table = dt_match, 1347 .pm = &msm_pm_ops, 1348 }, 1349 }; 1350 1351 static int __init msm_drm_register(void) 1352 { 1353 if (!modeset) 1354 return -EINVAL; 1355 1356 DBG("init"); 1357 msm_mdp_register(); 1358 msm_dpu_register(); 1359 msm_dsi_register(); 1360 msm_edp_register(); 1361 msm_hdmi_register(); 1362 msm_dp_register(); 1363 adreno_register(); 1364 return platform_driver_register(&msm_platform_driver); 1365 } 1366 1367 static void __exit msm_drm_unregister(void) 1368 { 1369 DBG("fini"); 1370 platform_driver_unregister(&msm_platform_driver); 1371 msm_dp_unregister(); 1372 msm_hdmi_unregister(); 1373 adreno_unregister(); 1374 msm_edp_unregister(); 1375 msm_dsi_unregister(); 1376 msm_mdp_unregister(); 1377 msm_dpu_unregister(); 1378 } 1379 1380 module_init(msm_drm_register); 1381 module_exit(msm_drm_unregister); 1382 1383 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 1384 MODULE_DESCRIPTION("MSM DRM Driver"); 1385 MODULE_LICENSE("GPL"); 1386