1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "hdmi.h" 19 20 struct hdmi_bridge { 21 struct drm_bridge base; 22 struct hdmi *hdmi; 23 }; 24 #define to_hdmi_bridge(x) container_of(x, struct hdmi_bridge, base) 25 26 void msm_hdmi_bridge_destroy(struct drm_bridge *bridge) 27 { 28 } 29 30 static void msm_hdmi_power_on(struct drm_bridge *bridge) 31 { 32 struct drm_device *dev = bridge->dev; 33 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 34 struct hdmi *hdmi = hdmi_bridge->hdmi; 35 const struct hdmi_platform_config *config = hdmi->config; 36 int i, ret; 37 38 for (i = 0; i < config->pwr_reg_cnt; i++) { 39 ret = regulator_enable(hdmi->pwr_regs[i]); 40 if (ret) { 41 dev_err(dev->dev, "failed to enable pwr regulator: %s (%d)\n", 42 config->pwr_reg_names[i], ret); 43 } 44 } 45 46 if (config->pwr_clk_cnt > 0) { 47 DBG("pixclock: %lu", hdmi->pixclock); 48 ret = clk_set_rate(hdmi->pwr_clks[0], hdmi->pixclock); 49 if (ret) { 50 dev_err(dev->dev, "failed to set pixel clk: %s (%d)\n", 51 config->pwr_clk_names[0], ret); 52 } 53 } 54 55 for (i = 0; i < config->pwr_clk_cnt; i++) { 56 ret = clk_prepare_enable(hdmi->pwr_clks[i]); 57 if (ret) { 58 dev_err(dev->dev, "failed to enable pwr clk: %s (%d)\n", 59 config->pwr_clk_names[i], ret); 60 } 61 } 62 } 63 64 static void power_off(struct drm_bridge *bridge) 65 { 66 struct drm_device *dev = bridge->dev; 67 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 68 struct hdmi *hdmi = hdmi_bridge->hdmi; 69 const struct hdmi_platform_config *config = hdmi->config; 70 int i, ret; 71 72 /* TODO do we need to wait for final vblank somewhere before 73 * cutting the clocks? 74 */ 75 mdelay(16 + 4); 76 77 for (i = 0; i < config->pwr_clk_cnt; i++) 78 clk_disable_unprepare(hdmi->pwr_clks[i]); 79 80 for (i = 0; i < config->pwr_reg_cnt; i++) { 81 ret = regulator_disable(hdmi->pwr_regs[i]); 82 if (ret) { 83 dev_err(dev->dev, "failed to disable pwr regulator: %s (%d)\n", 84 config->pwr_reg_names[i], ret); 85 } 86 } 87 } 88 89 #define AVI_IFRAME_LINE_NUMBER 1 90 91 static void msm_hdmi_config_avi_infoframe(struct hdmi *hdmi) 92 { 93 struct drm_crtc *crtc = hdmi->encoder->crtc; 94 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 95 union hdmi_infoframe frame; 96 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; 97 u32 val; 98 int len; 99 100 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode); 101 102 len = hdmi_infoframe_pack(&frame, buffer, sizeof(buffer)); 103 if (len < 0) { 104 dev_err(&hdmi->pdev->dev, 105 "failed to configure avi infoframe\n"); 106 return; 107 } 108 109 /* 110 * the AVI_INFOx registers don't map exactly to how the AVI infoframes 111 * are packed according to the spec. The checksum from the header is 112 * written to the LSB byte of AVI_INFO0 and the version is written to 113 * the third byte from the LSB of AVI_INFO3 114 */ 115 hdmi_write(hdmi, REG_HDMI_AVI_INFO(0), 116 buffer[3] | 117 buffer[4] << 8 | 118 buffer[5] << 16 | 119 buffer[6] << 24); 120 121 hdmi_write(hdmi, REG_HDMI_AVI_INFO(1), 122 buffer[7] | 123 buffer[8] << 8 | 124 buffer[9] << 16 | 125 buffer[10] << 24); 126 127 hdmi_write(hdmi, REG_HDMI_AVI_INFO(2), 128 buffer[11] | 129 buffer[12] << 8 | 130 buffer[13] << 16 | 131 buffer[14] << 24); 132 133 hdmi_write(hdmi, REG_HDMI_AVI_INFO(3), 134 buffer[15] | 135 buffer[16] << 8 | 136 buffer[1] << 24); 137 138 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL0, 139 HDMI_INFOFRAME_CTRL0_AVI_SEND | 140 HDMI_INFOFRAME_CTRL0_AVI_CONT); 141 142 val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL1); 143 val &= ~HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK; 144 val |= HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(AVI_IFRAME_LINE_NUMBER); 145 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL1, val); 146 } 147 148 static void msm_hdmi_bridge_pre_enable(struct drm_bridge *bridge) 149 { 150 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 151 struct hdmi *hdmi = hdmi_bridge->hdmi; 152 struct hdmi_phy *phy = hdmi->phy; 153 154 DBG("power up"); 155 156 if (!hdmi->power_on) { 157 msm_hdmi_phy_resource_enable(phy); 158 msm_hdmi_power_on(bridge); 159 hdmi->power_on = true; 160 if (hdmi->hdmi_mode) { 161 msm_hdmi_config_avi_infoframe(hdmi); 162 msm_hdmi_audio_update(hdmi); 163 } 164 } 165 166 msm_hdmi_phy_powerup(phy, hdmi->pixclock); 167 168 msm_hdmi_set_mode(hdmi, true); 169 170 if (hdmi->hdcp_ctrl) 171 msm_hdmi_hdcp_on(hdmi->hdcp_ctrl); 172 } 173 174 static void msm_hdmi_bridge_enable(struct drm_bridge *bridge) 175 { 176 } 177 178 static void msm_hdmi_bridge_disable(struct drm_bridge *bridge) 179 { 180 } 181 182 static void msm_hdmi_bridge_post_disable(struct drm_bridge *bridge) 183 { 184 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 185 struct hdmi *hdmi = hdmi_bridge->hdmi; 186 struct hdmi_phy *phy = hdmi->phy; 187 188 if (hdmi->hdcp_ctrl) 189 msm_hdmi_hdcp_off(hdmi->hdcp_ctrl); 190 191 DBG("power down"); 192 msm_hdmi_set_mode(hdmi, false); 193 194 msm_hdmi_phy_powerdown(phy); 195 196 if (hdmi->power_on) { 197 power_off(bridge); 198 hdmi->power_on = false; 199 if (hdmi->hdmi_mode) 200 msm_hdmi_audio_update(hdmi); 201 msm_hdmi_phy_resource_disable(phy); 202 } 203 } 204 205 static void msm_hdmi_bridge_mode_set(struct drm_bridge *bridge, 206 struct drm_display_mode *mode, 207 struct drm_display_mode *adjusted_mode) 208 { 209 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 210 struct hdmi *hdmi = hdmi_bridge->hdmi; 211 int hstart, hend, vstart, vend; 212 uint32_t frame_ctrl; 213 214 mode = adjusted_mode; 215 216 hdmi->pixclock = mode->clock * 1000; 217 218 hstart = mode->htotal - mode->hsync_start; 219 hend = mode->htotal - mode->hsync_start + mode->hdisplay; 220 221 vstart = mode->vtotal - mode->vsync_start - 1; 222 vend = mode->vtotal - mode->vsync_start + mode->vdisplay - 1; 223 224 DBG("htotal=%d, vtotal=%d, hstart=%d, hend=%d, vstart=%d, vend=%d", 225 mode->htotal, mode->vtotal, hstart, hend, vstart, vend); 226 227 hdmi_write(hdmi, REG_HDMI_TOTAL, 228 HDMI_TOTAL_H_TOTAL(mode->htotal - 1) | 229 HDMI_TOTAL_V_TOTAL(mode->vtotal - 1)); 230 231 hdmi_write(hdmi, REG_HDMI_ACTIVE_HSYNC, 232 HDMI_ACTIVE_HSYNC_START(hstart) | 233 HDMI_ACTIVE_HSYNC_END(hend)); 234 hdmi_write(hdmi, REG_HDMI_ACTIVE_VSYNC, 235 HDMI_ACTIVE_VSYNC_START(vstart) | 236 HDMI_ACTIVE_VSYNC_END(vend)); 237 238 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 239 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2, 240 HDMI_VSYNC_TOTAL_F2_V_TOTAL(mode->vtotal)); 241 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2, 242 HDMI_VSYNC_ACTIVE_F2_START(vstart + 1) | 243 HDMI_VSYNC_ACTIVE_F2_END(vend + 1)); 244 } else { 245 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2, 246 HDMI_VSYNC_TOTAL_F2_V_TOTAL(0)); 247 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2, 248 HDMI_VSYNC_ACTIVE_F2_START(0) | 249 HDMI_VSYNC_ACTIVE_F2_END(0)); 250 } 251 252 frame_ctrl = 0; 253 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 254 frame_ctrl |= HDMI_FRAME_CTRL_HSYNC_LOW; 255 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 256 frame_ctrl |= HDMI_FRAME_CTRL_VSYNC_LOW; 257 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 258 frame_ctrl |= HDMI_FRAME_CTRL_INTERLACED_EN; 259 DBG("frame_ctrl=%08x", frame_ctrl); 260 hdmi_write(hdmi, REG_HDMI_FRAME_CTRL, frame_ctrl); 261 262 if (hdmi->hdmi_mode) 263 msm_hdmi_audio_update(hdmi); 264 } 265 266 static const struct drm_bridge_funcs msm_hdmi_bridge_funcs = { 267 .pre_enable = msm_hdmi_bridge_pre_enable, 268 .enable = msm_hdmi_bridge_enable, 269 .disable = msm_hdmi_bridge_disable, 270 .post_disable = msm_hdmi_bridge_post_disable, 271 .mode_set = msm_hdmi_bridge_mode_set, 272 }; 273 274 275 /* initialize bridge */ 276 struct drm_bridge *msm_hdmi_bridge_init(struct hdmi *hdmi) 277 { 278 struct drm_bridge *bridge = NULL; 279 struct hdmi_bridge *hdmi_bridge; 280 int ret; 281 282 hdmi_bridge = devm_kzalloc(hdmi->dev->dev, 283 sizeof(*hdmi_bridge), GFP_KERNEL); 284 if (!hdmi_bridge) { 285 ret = -ENOMEM; 286 goto fail; 287 } 288 289 hdmi_bridge->hdmi = hdmi; 290 291 bridge = &hdmi_bridge->base; 292 bridge->funcs = &msm_hdmi_bridge_funcs; 293 294 ret = drm_bridge_attach(hdmi->encoder, bridge, NULL); 295 if (ret) 296 goto fail; 297 298 return bridge; 299 300 fail: 301 if (bridge) 302 msm_hdmi_bridge_destroy(bridge); 303 304 return ERR_PTR(ret); 305 } 306