1 #ifndef HDMI_XML 2 #define HDMI_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20136 bytes, from 2014-10-31 16:51:39) 14 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1940 bytes, from 2014-10-31 16:51:39) 15 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 23963 bytes, from 2014-10-31 16:51:46) 16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 17 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 18 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) 19 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 20 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-07-17 15:33:30) 21 22 Copyright (C) 2013-2014 by the following authors: 23 - Rob Clark <robdclark@gmail.com> (robclark) 24 25 Permission is hereby granted, free of charge, to any person obtaining 26 a copy of this software and associated documentation files (the 27 "Software"), to deal in the Software without restriction, including 28 without limitation the rights to use, copy, modify, merge, publish, 29 distribute, sublicense, and/or sell copies of the Software, and to 30 permit persons to whom the Software is furnished to do so, subject to 31 the following conditions: 32 33 The above copyright notice and this permission notice (including the 34 next paragraph) shall be included in all copies or substantial 35 portions of the Software. 36 37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46 47 enum hdmi_hdcp_key_state { 48 NO_KEYS = 0, 49 NOT_CHECKED = 1, 50 CHECKING = 2, 51 KEYS_VALID = 3, 52 AKSV_INVALID = 4, 53 CHECKSUM_MISMATCH = 5, 54 }; 55 56 enum hdmi_ddc_read_write { 57 DDC_WRITE = 0, 58 DDC_READ = 1, 59 }; 60 61 enum hdmi_acr_cts { 62 ACR_NONE = 0, 63 ACR_32 = 1, 64 ACR_44 = 2, 65 ACR_48 = 3, 66 }; 67 68 #define REG_HDMI_CTRL 0x00000000 69 #define HDMI_CTRL_ENABLE 0x00000001 70 #define HDMI_CTRL_HDMI 0x00000002 71 #define HDMI_CTRL_ENCRYPTED 0x00000004 72 73 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020 74 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001 75 76 #define REG_HDMI_ACR_PKT_CTRL 0x00000024 77 #define HDMI_ACR_PKT_CTRL_CONT 0x00000001 78 #define HDMI_ACR_PKT_CTRL_SEND 0x00000002 79 #define HDMI_ACR_PKT_CTRL_SELECT__MASK 0x00000030 80 #define HDMI_ACR_PKT_CTRL_SELECT__SHIFT 4 81 static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val) 82 { 83 return ((val) << HDMI_ACR_PKT_CTRL_SELECT__SHIFT) & HDMI_ACR_PKT_CTRL_SELECT__MASK; 84 } 85 #define HDMI_ACR_PKT_CTRL_SOURCE 0x00000100 86 #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK 0x00070000 87 #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT 16 88 static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val) 89 { 90 return ((val) << HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT) & HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK; 91 } 92 #define HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY 0x80000000 93 94 #define REG_HDMI_VBI_PKT_CTRL 0x00000028 95 #define HDMI_VBI_PKT_CTRL_GC_ENABLE 0x00000010 96 #define HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME 0x00000020 97 #define HDMI_VBI_PKT_CTRL_ISRC_SEND 0x00000100 98 #define HDMI_VBI_PKT_CTRL_ISRC_CONTINUOUS 0x00000200 99 #define HDMI_VBI_PKT_CTRL_ACP_SEND 0x00001000 100 #define HDMI_VBI_PKT_CTRL_ACP_SRC_SW 0x00002000 101 102 #define REG_HDMI_INFOFRAME_CTRL0 0x0000002c 103 #define HDMI_INFOFRAME_CTRL0_AVI_SEND 0x00000001 104 #define HDMI_INFOFRAME_CTRL0_AVI_CONT 0x00000002 105 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND 0x00000010 106 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT 0x00000020 107 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE 0x00000040 108 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE 0x00000080 109 110 #define REG_HDMI_GEN_PKT_CTRL 0x00000034 111 #define HDMI_GEN_PKT_CTRL_GENERIC0_SEND 0x00000001 112 #define HDMI_GEN_PKT_CTRL_GENERIC0_CONT 0x00000002 113 #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK 0x0000000c 114 #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT 2 115 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val) 116 { 117 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK; 118 } 119 #define HDMI_GEN_PKT_CTRL_GENERIC1_SEND 0x00000010 120 #define HDMI_GEN_PKT_CTRL_GENERIC1_CONT 0x00000020 121 #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK 0x003f0000 122 #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT 16 123 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val) 124 { 125 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK; 126 } 127 #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK 0x3f000000 128 #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT 24 129 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val) 130 { 131 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK; 132 } 133 134 #define REG_HDMI_GC 0x00000040 135 #define HDMI_GC_MUTE 0x00000001 136 137 #define REG_HDMI_AUDIO_PKT_CTRL2 0x00000044 138 #define HDMI_AUDIO_PKT_CTRL2_OVERRIDE 0x00000001 139 #define HDMI_AUDIO_PKT_CTRL2_LAYOUT 0x00000002 140 141 static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; } 142 143 #define REG_HDMI_GENERIC0_HDR 0x00000084 144 145 static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; } 146 147 #define REG_HDMI_GENERIC1_HDR 0x000000a4 148 149 static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; } 150 151 static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } 152 153 static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } 154 #define HDMI_ACR_0_CTS__MASK 0xfffff000 155 #define HDMI_ACR_0_CTS__SHIFT 12 156 static inline uint32_t HDMI_ACR_0_CTS(uint32_t val) 157 { 158 return ((val) << HDMI_ACR_0_CTS__SHIFT) & HDMI_ACR_0_CTS__MASK; 159 } 160 161 static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; } 162 #define HDMI_ACR_1_N__MASK 0xffffffff 163 #define HDMI_ACR_1_N__SHIFT 0 164 static inline uint32_t HDMI_ACR_1_N(uint32_t val) 165 { 166 return ((val) << HDMI_ACR_1_N__SHIFT) & HDMI_ACR_1_N__MASK; 167 } 168 169 #define REG_HDMI_AUDIO_INFO0 0x000000e4 170 #define HDMI_AUDIO_INFO0_CHECKSUM__MASK 0x000000ff 171 #define HDMI_AUDIO_INFO0_CHECKSUM__SHIFT 0 172 static inline uint32_t HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val) 173 { 174 return ((val) << HDMI_AUDIO_INFO0_CHECKSUM__SHIFT) & HDMI_AUDIO_INFO0_CHECKSUM__MASK; 175 } 176 #define HDMI_AUDIO_INFO0_CC__MASK 0x00000700 177 #define HDMI_AUDIO_INFO0_CC__SHIFT 8 178 static inline uint32_t HDMI_AUDIO_INFO0_CC(uint32_t val) 179 { 180 return ((val) << HDMI_AUDIO_INFO0_CC__SHIFT) & HDMI_AUDIO_INFO0_CC__MASK; 181 } 182 183 #define REG_HDMI_AUDIO_INFO1 0x000000e8 184 #define HDMI_AUDIO_INFO1_CA__MASK 0x000000ff 185 #define HDMI_AUDIO_INFO1_CA__SHIFT 0 186 static inline uint32_t HDMI_AUDIO_INFO1_CA(uint32_t val) 187 { 188 return ((val) << HDMI_AUDIO_INFO1_CA__SHIFT) & HDMI_AUDIO_INFO1_CA__MASK; 189 } 190 #define HDMI_AUDIO_INFO1_LSV__MASK 0x00007800 191 #define HDMI_AUDIO_INFO1_LSV__SHIFT 11 192 static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val) 193 { 194 return ((val) << HDMI_AUDIO_INFO1_LSV__SHIFT) & HDMI_AUDIO_INFO1_LSV__MASK; 195 } 196 #define HDMI_AUDIO_INFO1_DM_INH 0x00008000 197 198 #define REG_HDMI_HDCP_CTRL 0x00000110 199 #define HDMI_HDCP_CTRL_ENABLE 0x00000001 200 #define HDMI_HDCP_CTRL_ENCRYPTION_ENABLE 0x00000100 201 202 #define REG_HDMI_HDCP_INT_CTRL 0x00000118 203 204 #define REG_HDMI_HDCP_LINK0_STATUS 0x0000011c 205 #define HDMI_HDCP_LINK0_STATUS_AN_0_READY 0x00000100 206 #define HDMI_HDCP_LINK0_STATUS_AN_1_READY 0x00000200 207 #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK 0x70000000 208 #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT 28 209 static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val) 210 { 211 return ((val) << HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT) & HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK; 212 } 213 214 #define REG_HDMI_HDCP_RESET 0x00000130 215 #define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE 0x00000001 216 217 #define REG_HDMI_VENSPEC_INFO0 0x0000016c 218 219 #define REG_HDMI_VENSPEC_INFO1 0x00000170 220 221 #define REG_HDMI_VENSPEC_INFO2 0x00000174 222 223 #define REG_HDMI_VENSPEC_INFO3 0x00000178 224 225 #define REG_HDMI_VENSPEC_INFO4 0x0000017c 226 227 #define REG_HDMI_VENSPEC_INFO5 0x00000180 228 229 #define REG_HDMI_VENSPEC_INFO6 0x00000184 230 231 #define REG_HDMI_AUDIO_CFG 0x000001d0 232 #define HDMI_AUDIO_CFG_ENGINE_ENABLE 0x00000001 233 #define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK 0x000000f0 234 #define HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT 4 235 static inline uint32_t HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val) 236 { 237 return ((val) << HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT) & HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK; 238 } 239 240 #define REG_HDMI_USEC_REFTIMER 0x00000208 241 242 #define REG_HDMI_DDC_CTRL 0x0000020c 243 #define HDMI_DDC_CTRL_GO 0x00000001 244 #define HDMI_DDC_CTRL_SOFT_RESET 0x00000002 245 #define HDMI_DDC_CTRL_SEND_RESET 0x00000004 246 #define HDMI_DDC_CTRL_SW_STATUS_RESET 0x00000008 247 #define HDMI_DDC_CTRL_TRANSACTION_CNT__MASK 0x00300000 248 #define HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT 20 249 static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val) 250 { 251 return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK; 252 } 253 254 #define REG_HDMI_DDC_ARBITRATION 0x00000210 255 #define HDMI_DDC_ARBITRATION_HW_ARBITRATION 0x00000010 256 257 #define REG_HDMI_DDC_INT_CTRL 0x00000214 258 #define HDMI_DDC_INT_CTRL_SW_DONE_INT 0x00000001 259 #define HDMI_DDC_INT_CTRL_SW_DONE_ACK 0x00000002 260 #define HDMI_DDC_INT_CTRL_SW_DONE_MASK 0x00000004 261 262 #define REG_HDMI_DDC_SW_STATUS 0x00000218 263 #define HDMI_DDC_SW_STATUS_NACK0 0x00001000 264 #define HDMI_DDC_SW_STATUS_NACK1 0x00002000 265 #define HDMI_DDC_SW_STATUS_NACK2 0x00004000 266 #define HDMI_DDC_SW_STATUS_NACK3 0x00008000 267 268 #define REG_HDMI_DDC_HW_STATUS 0x0000021c 269 270 #define REG_HDMI_DDC_SPEED 0x00000220 271 #define HDMI_DDC_SPEED_THRESHOLD__MASK 0x00000003 272 #define HDMI_DDC_SPEED_THRESHOLD__SHIFT 0 273 static inline uint32_t HDMI_DDC_SPEED_THRESHOLD(uint32_t val) 274 { 275 return ((val) << HDMI_DDC_SPEED_THRESHOLD__SHIFT) & HDMI_DDC_SPEED_THRESHOLD__MASK; 276 } 277 #define HDMI_DDC_SPEED_PRESCALE__MASK 0xffff0000 278 #define HDMI_DDC_SPEED_PRESCALE__SHIFT 16 279 static inline uint32_t HDMI_DDC_SPEED_PRESCALE(uint32_t val) 280 { 281 return ((val) << HDMI_DDC_SPEED_PRESCALE__SHIFT) & HDMI_DDC_SPEED_PRESCALE__MASK; 282 } 283 284 #define REG_HDMI_DDC_SETUP 0x00000224 285 #define HDMI_DDC_SETUP_TIMEOUT__MASK 0xff000000 286 #define HDMI_DDC_SETUP_TIMEOUT__SHIFT 24 287 static inline uint32_t HDMI_DDC_SETUP_TIMEOUT(uint32_t val) 288 { 289 return ((val) << HDMI_DDC_SETUP_TIMEOUT__SHIFT) & HDMI_DDC_SETUP_TIMEOUT__MASK; 290 } 291 292 static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; } 293 294 static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; } 295 #define HDMI_I2C_TRANSACTION_REG_RW__MASK 0x00000001 296 #define HDMI_I2C_TRANSACTION_REG_RW__SHIFT 0 297 static inline uint32_t HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val) 298 { 299 return ((val) << HDMI_I2C_TRANSACTION_REG_RW__SHIFT) & HDMI_I2C_TRANSACTION_REG_RW__MASK; 300 } 301 #define HDMI_I2C_TRANSACTION_REG_STOP_ON_NACK 0x00000100 302 #define HDMI_I2C_TRANSACTION_REG_START 0x00001000 303 #define HDMI_I2C_TRANSACTION_REG_STOP 0x00002000 304 #define HDMI_I2C_TRANSACTION_REG_CNT__MASK 0x00ff0000 305 #define HDMI_I2C_TRANSACTION_REG_CNT__SHIFT 16 306 static inline uint32_t HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val) 307 { 308 return ((val) << HDMI_I2C_TRANSACTION_REG_CNT__SHIFT) & HDMI_I2C_TRANSACTION_REG_CNT__MASK; 309 } 310 311 #define REG_HDMI_DDC_DATA 0x00000238 312 #define HDMI_DDC_DATA_DATA_RW__MASK 0x00000001 313 #define HDMI_DDC_DATA_DATA_RW__SHIFT 0 314 static inline uint32_t HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val) 315 { 316 return ((val) << HDMI_DDC_DATA_DATA_RW__SHIFT) & HDMI_DDC_DATA_DATA_RW__MASK; 317 } 318 #define HDMI_DDC_DATA_DATA__MASK 0x0000ff00 319 #define HDMI_DDC_DATA_DATA__SHIFT 8 320 static inline uint32_t HDMI_DDC_DATA_DATA(uint32_t val) 321 { 322 return ((val) << HDMI_DDC_DATA_DATA__SHIFT) & HDMI_DDC_DATA_DATA__MASK; 323 } 324 #define HDMI_DDC_DATA_INDEX__MASK 0x00ff0000 325 #define HDMI_DDC_DATA_INDEX__SHIFT 16 326 static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val) 327 { 328 return ((val) << HDMI_DDC_DATA_INDEX__SHIFT) & HDMI_DDC_DATA_INDEX__MASK; 329 } 330 #define HDMI_DDC_DATA_INDEX_WRITE 0x80000000 331 332 #define REG_HDMI_HPD_INT_STATUS 0x00000250 333 #define HDMI_HPD_INT_STATUS_INT 0x00000001 334 #define HDMI_HPD_INT_STATUS_CABLE_DETECTED 0x00000002 335 336 #define REG_HDMI_HPD_INT_CTRL 0x00000254 337 #define HDMI_HPD_INT_CTRL_INT_ACK 0x00000001 338 #define HDMI_HPD_INT_CTRL_INT_CONNECT 0x00000002 339 #define HDMI_HPD_INT_CTRL_INT_EN 0x00000004 340 #define HDMI_HPD_INT_CTRL_RX_INT_ACK 0x00000010 341 #define HDMI_HPD_INT_CTRL_RX_INT_EN 0x00000020 342 #define HDMI_HPD_INT_CTRL_RCV_PLUGIN_DET_MASK 0x00000200 343 344 #define REG_HDMI_HPD_CTRL 0x00000258 345 #define HDMI_HPD_CTRL_TIMEOUT__MASK 0x00001fff 346 #define HDMI_HPD_CTRL_TIMEOUT__SHIFT 0 347 static inline uint32_t HDMI_HPD_CTRL_TIMEOUT(uint32_t val) 348 { 349 return ((val) << HDMI_HPD_CTRL_TIMEOUT__SHIFT) & HDMI_HPD_CTRL_TIMEOUT__MASK; 350 } 351 #define HDMI_HPD_CTRL_ENABLE 0x10000000 352 353 #define REG_HDMI_DDC_REF 0x0000027c 354 #define HDMI_DDC_REF_REFTIMER_ENABLE 0x00010000 355 #define HDMI_DDC_REF_REFTIMER__MASK 0x0000ffff 356 #define HDMI_DDC_REF_REFTIMER__SHIFT 0 357 static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val) 358 { 359 return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK; 360 } 361 362 #define REG_HDMI_CEC_STATUS 0x00000298 363 364 #define REG_HDMI_CEC_INT 0x0000029c 365 366 #define REG_HDMI_CEC_ADDR 0x000002a0 367 368 #define REG_HDMI_CEC_TIME 0x000002a4 369 370 #define REG_HDMI_CEC_REFTIMER 0x000002a8 371 372 #define REG_HDMI_CEC_RD_DATA 0x000002ac 373 374 #define REG_HDMI_CEC_RD_FILTER 0x000002b0 375 376 #define REG_HDMI_ACTIVE_HSYNC 0x000002b4 377 #define HDMI_ACTIVE_HSYNC_START__MASK 0x00000fff 378 #define HDMI_ACTIVE_HSYNC_START__SHIFT 0 379 static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val) 380 { 381 return ((val) << HDMI_ACTIVE_HSYNC_START__SHIFT) & HDMI_ACTIVE_HSYNC_START__MASK; 382 } 383 #define HDMI_ACTIVE_HSYNC_END__MASK 0x0fff0000 384 #define HDMI_ACTIVE_HSYNC_END__SHIFT 16 385 static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val) 386 { 387 return ((val) << HDMI_ACTIVE_HSYNC_END__SHIFT) & HDMI_ACTIVE_HSYNC_END__MASK; 388 } 389 390 #define REG_HDMI_ACTIVE_VSYNC 0x000002b8 391 #define HDMI_ACTIVE_VSYNC_START__MASK 0x00000fff 392 #define HDMI_ACTIVE_VSYNC_START__SHIFT 0 393 static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val) 394 { 395 return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK; 396 } 397 #define HDMI_ACTIVE_VSYNC_END__MASK 0x0fff0000 398 #define HDMI_ACTIVE_VSYNC_END__SHIFT 16 399 static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val) 400 { 401 return ((val) << HDMI_ACTIVE_VSYNC_END__SHIFT) & HDMI_ACTIVE_VSYNC_END__MASK; 402 } 403 404 #define REG_HDMI_VSYNC_ACTIVE_F2 0x000002bc 405 #define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00000fff 406 #define HDMI_VSYNC_ACTIVE_F2_START__SHIFT 0 407 static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val) 408 { 409 return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK; 410 } 411 #define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x0fff0000 412 #define HDMI_VSYNC_ACTIVE_F2_END__SHIFT 16 413 static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val) 414 { 415 return ((val) << HDMI_VSYNC_ACTIVE_F2_END__SHIFT) & HDMI_VSYNC_ACTIVE_F2_END__MASK; 416 } 417 418 #define REG_HDMI_TOTAL 0x000002c0 419 #define HDMI_TOTAL_H_TOTAL__MASK 0x00000fff 420 #define HDMI_TOTAL_H_TOTAL__SHIFT 0 421 static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val) 422 { 423 return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK; 424 } 425 #define HDMI_TOTAL_V_TOTAL__MASK 0x0fff0000 426 #define HDMI_TOTAL_V_TOTAL__SHIFT 16 427 static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val) 428 { 429 return ((val) << HDMI_TOTAL_V_TOTAL__SHIFT) & HDMI_TOTAL_V_TOTAL__MASK; 430 } 431 432 #define REG_HDMI_VSYNC_TOTAL_F2 0x000002c4 433 #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00000fff 434 #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT 0 435 static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val) 436 { 437 return ((val) << HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT) & HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK; 438 } 439 440 #define REG_HDMI_FRAME_CTRL 0x000002c8 441 #define HDMI_FRAME_CTRL_RGB_MUX_SEL_BGR 0x00001000 442 #define HDMI_FRAME_CTRL_VSYNC_LOW 0x10000000 443 #define HDMI_FRAME_CTRL_HSYNC_LOW 0x20000000 444 #define HDMI_FRAME_CTRL_INTERLACED_EN 0x80000000 445 446 #define REG_HDMI_AUD_INT 0x000002cc 447 #define HDMI_AUD_INT_AUD_FIFO_URUN_INT 0x00000001 448 #define HDMI_AUD_INT_AUD_FIFO_URAN_MASK 0x00000002 449 #define HDMI_AUD_INT_AUD_SAM_DROP_INT 0x00000004 450 #define HDMI_AUD_INT_AUD_SAM_DROP_MASK 0x00000008 451 452 #define REG_HDMI_PHY_CTRL 0x000002d4 453 #define HDMI_PHY_CTRL_SW_RESET_PLL 0x00000001 454 #define HDMI_PHY_CTRL_SW_RESET_PLL_LOW 0x00000002 455 #define HDMI_PHY_CTRL_SW_RESET 0x00000004 456 #define HDMI_PHY_CTRL_SW_RESET_LOW 0x00000008 457 458 #define REG_HDMI_CEC_WR_RANGE 0x000002dc 459 460 #define REG_HDMI_CEC_RD_RANGE 0x000002e0 461 462 #define REG_HDMI_VERSION 0x000002e4 463 464 #define REG_HDMI_CEC_COMPL_CTL 0x00000360 465 466 #define REG_HDMI_CEC_RD_START_RANGE 0x00000364 467 468 #define REG_HDMI_CEC_RD_TOTAL_RANGE 0x00000368 469 470 #define REG_HDMI_CEC_RD_ERR_RESP_LO 0x0000036c 471 472 #define REG_HDMI_CEC_WR_CHECK_CONFIG 0x00000370 473 474 #define REG_HDMI_8x60_PHY_REG0 0x00000300 475 #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c 476 #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT 2 477 static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val) 478 { 479 return ((val) << HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT) & HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK; 480 } 481 482 #define REG_HDMI_8x60_PHY_REG1 0x00000304 483 #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK 0x000000f0 484 #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT 4 485 static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val) 486 { 487 return ((val) << HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT) & HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK; 488 } 489 #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK 0x0000000f 490 #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT 0 491 static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val) 492 { 493 return ((val) << HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT) & HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK; 494 } 495 496 #define REG_HDMI_8x60_PHY_REG2 0x00000308 497 #define HDMI_8x60_PHY_REG2_PD_DESER 0x00000001 498 #define HDMI_8x60_PHY_REG2_PD_DRIVE_1 0x00000002 499 #define HDMI_8x60_PHY_REG2_PD_DRIVE_2 0x00000004 500 #define HDMI_8x60_PHY_REG2_PD_DRIVE_3 0x00000008 501 #define HDMI_8x60_PHY_REG2_PD_DRIVE_4 0x00000010 502 #define HDMI_8x60_PHY_REG2_PD_PLL 0x00000020 503 #define HDMI_8x60_PHY_REG2_PD_PWRGEN 0x00000040 504 #define HDMI_8x60_PHY_REG2_RCV_SENSE_EN 0x00000080 505 506 #define REG_HDMI_8x60_PHY_REG3 0x0000030c 507 #define HDMI_8x60_PHY_REG3_PLL_ENABLE 0x00000001 508 509 #define REG_HDMI_8x60_PHY_REG4 0x00000310 510 511 #define REG_HDMI_8x60_PHY_REG5 0x00000314 512 513 #define REG_HDMI_8x60_PHY_REG6 0x00000318 514 515 #define REG_HDMI_8x60_PHY_REG7 0x0000031c 516 517 #define REG_HDMI_8x60_PHY_REG8 0x00000320 518 519 #define REG_HDMI_8x60_PHY_REG9 0x00000324 520 521 #define REG_HDMI_8x60_PHY_REG10 0x00000328 522 523 #define REG_HDMI_8x60_PHY_REG11 0x0000032c 524 525 #define REG_HDMI_8x60_PHY_REG12 0x00000330 526 #define HDMI_8x60_PHY_REG12_RETIMING_EN 0x00000001 527 #define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN 0x00000002 528 #define HDMI_8x60_PHY_REG12_FORCE_LOCK 0x00000010 529 530 #define REG_HDMI_8960_PHY_REG0 0x00000400 531 532 #define REG_HDMI_8960_PHY_REG1 0x00000404 533 534 #define REG_HDMI_8960_PHY_REG2 0x00000408 535 536 #define REG_HDMI_8960_PHY_REG3 0x0000040c 537 538 #define REG_HDMI_8960_PHY_REG4 0x00000410 539 540 #define REG_HDMI_8960_PHY_REG5 0x00000414 541 542 #define REG_HDMI_8960_PHY_REG6 0x00000418 543 544 #define REG_HDMI_8960_PHY_REG7 0x0000041c 545 546 #define REG_HDMI_8960_PHY_REG8 0x00000420 547 548 #define REG_HDMI_8960_PHY_REG9 0x00000424 549 550 #define REG_HDMI_8960_PHY_REG10 0x00000428 551 552 #define REG_HDMI_8960_PHY_REG11 0x0000042c 553 554 #define REG_HDMI_8960_PHY_REG12 0x00000430 555 #define HDMI_8960_PHY_REG12_SW_RESET 0x00000020 556 #define HDMI_8960_PHY_REG12_PWRDN_B 0x00000080 557 558 #define REG_HDMI_8960_PHY_REG_BIST_CFG 0x00000434 559 560 #define REG_HDMI_8960_PHY_DEBUG_BUS_SEL 0x00000438 561 562 #define REG_HDMI_8960_PHY_REG_MISC0 0x0000043c 563 564 #define REG_HDMI_8960_PHY_REG13 0x00000440 565 566 #define REG_HDMI_8960_PHY_REG14 0x00000444 567 568 #define REG_HDMI_8960_PHY_REG15 0x00000448 569 570 #define REG_HDMI_8960_PHY_PLL_REFCLK_CFG 0x00000500 571 572 #define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG 0x00000504 573 574 #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 0x00000508 575 576 #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 0x0000050c 577 578 #define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG 0x00000510 579 580 #define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG 0x00000514 581 582 #define REG_HDMI_8960_PHY_PLL_PWRDN_B 0x00000518 583 #define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL 0x00000002 584 #define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B 0x00000008 585 586 #define REG_HDMI_8960_PHY_PLL_SDM_CFG0 0x0000051c 587 588 #define REG_HDMI_8960_PHY_PLL_SDM_CFG1 0x00000520 589 590 #define REG_HDMI_8960_PHY_PLL_SDM_CFG2 0x00000524 591 592 #define REG_HDMI_8960_PHY_PLL_SDM_CFG3 0x00000528 593 594 #define REG_HDMI_8960_PHY_PLL_SDM_CFG4 0x0000052c 595 596 #define REG_HDMI_8960_PHY_PLL_SSC_CFG0 0x00000530 597 598 #define REG_HDMI_8960_PHY_PLL_SSC_CFG1 0x00000534 599 600 #define REG_HDMI_8960_PHY_PLL_SSC_CFG2 0x00000538 601 602 #define REG_HDMI_8960_PHY_PLL_SSC_CFG3 0x0000053c 603 604 #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 0x00000540 605 606 #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 0x00000544 607 608 #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 0x00000548 609 610 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 0x0000054c 611 612 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 0x00000550 613 614 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 0x00000554 615 616 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 0x00000558 617 618 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 0x0000055c 619 620 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 0x00000560 621 622 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 0x00000564 623 624 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 0x00000568 625 626 #define REG_HDMI_8960_PHY_PLL_DEBUG_SEL 0x0000056c 627 628 #define REG_HDMI_8960_PHY_PLL_MISC0 0x00000570 629 630 #define REG_HDMI_8960_PHY_PLL_MISC1 0x00000574 631 632 #define REG_HDMI_8960_PHY_PLL_MISC2 0x00000578 633 634 #define REG_HDMI_8960_PHY_PLL_MISC3 0x0000057c 635 636 #define REG_HDMI_8960_PHY_PLL_MISC4 0x00000580 637 638 #define REG_HDMI_8960_PHY_PLL_MISC5 0x00000584 639 640 #define REG_HDMI_8960_PHY_PLL_MISC6 0x00000588 641 642 #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0 0x0000058c 643 644 #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1 0x00000590 645 646 #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2 0x00000594 647 648 #define REG_HDMI_8960_PHY_PLL_STATUS0 0x00000598 649 #define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK 0x00000001 650 651 #define REG_HDMI_8960_PHY_PLL_STATUS1 0x0000059c 652 653 #define REG_HDMI_8x74_ANA_CFG0 0x00000000 654 655 #define REG_HDMI_8x74_ANA_CFG1 0x00000004 656 657 #define REG_HDMI_8x74_PD_CTRL0 0x00000010 658 659 #define REG_HDMI_8x74_PD_CTRL1 0x00000014 660 661 #define REG_HDMI_8x74_BIST_CFG0 0x00000034 662 663 #define REG_HDMI_8x74_BIST_PATN0 0x0000003c 664 665 #define REG_HDMI_8x74_BIST_PATN1 0x00000040 666 667 #define REG_HDMI_8x74_BIST_PATN2 0x00000044 668 669 #define REG_HDMI_8x74_BIST_PATN3 0x00000048 670 671 672 #endif /* HDMI_XML */ 673