1 #ifndef HDMI_XML 2 #define HDMI_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00) 14 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00) 15 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11) 16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 17 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 18 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) 19 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 20 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57) 21 - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00) 22 23 Copyright (C) 2013-2015 by the following authors: 24 - Rob Clark <robdclark@gmail.com> (robclark) 25 26 Permission is hereby granted, free of charge, to any person obtaining 27 a copy of this software and associated documentation files (the 28 "Software"), to deal in the Software without restriction, including 29 without limitation the rights to use, copy, modify, merge, publish, 30 distribute, sublicense, and/or sell copies of the Software, and to 31 permit persons to whom the Software is furnished to do so, subject to 32 the following conditions: 33 34 The above copyright notice and this permission notice (including the 35 next paragraph) shall be included in all copies or substantial 36 portions of the Software. 37 38 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 40 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 41 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 42 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 43 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 44 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 45 */ 46 47 48 enum hdmi_hdcp_key_state { 49 HDCP_KEYS_STATE_NO_KEYS = 0, 50 HDCP_KEYS_STATE_NOT_CHECKED = 1, 51 HDCP_KEYS_STATE_CHECKING = 2, 52 HDCP_KEYS_STATE_VALID = 3, 53 HDCP_KEYS_STATE_AKSV_NOT_VALID = 4, 54 HDCP_KEYS_STATE_CHKSUM_MISMATCH = 5, 55 HDCP_KEYS_STATE_PROD_AKSV = 6, 56 HDCP_KEYS_STATE_RESERVED = 7, 57 }; 58 59 enum hdmi_ddc_read_write { 60 DDC_WRITE = 0, 61 DDC_READ = 1, 62 }; 63 64 enum hdmi_acr_cts { 65 ACR_NONE = 0, 66 ACR_32 = 1, 67 ACR_44 = 2, 68 ACR_48 = 3, 69 }; 70 71 #define REG_HDMI_CTRL 0x00000000 72 #define HDMI_CTRL_ENABLE 0x00000001 73 #define HDMI_CTRL_HDMI 0x00000002 74 #define HDMI_CTRL_ENCRYPTED 0x00000004 75 76 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020 77 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001 78 79 #define REG_HDMI_ACR_PKT_CTRL 0x00000024 80 #define HDMI_ACR_PKT_CTRL_CONT 0x00000001 81 #define HDMI_ACR_PKT_CTRL_SEND 0x00000002 82 #define HDMI_ACR_PKT_CTRL_SELECT__MASK 0x00000030 83 #define HDMI_ACR_PKT_CTRL_SELECT__SHIFT 4 84 static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val) 85 { 86 return ((val) << HDMI_ACR_PKT_CTRL_SELECT__SHIFT) & HDMI_ACR_PKT_CTRL_SELECT__MASK; 87 } 88 #define HDMI_ACR_PKT_CTRL_SOURCE 0x00000100 89 #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK 0x00070000 90 #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT 16 91 static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val) 92 { 93 return ((val) << HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT) & HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK; 94 } 95 #define HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY 0x80000000 96 97 #define REG_HDMI_VBI_PKT_CTRL 0x00000028 98 #define HDMI_VBI_PKT_CTRL_GC_ENABLE 0x00000010 99 #define HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME 0x00000020 100 #define HDMI_VBI_PKT_CTRL_ISRC_SEND 0x00000100 101 #define HDMI_VBI_PKT_CTRL_ISRC_CONTINUOUS 0x00000200 102 #define HDMI_VBI_PKT_CTRL_ACP_SEND 0x00001000 103 #define HDMI_VBI_PKT_CTRL_ACP_SRC_SW 0x00002000 104 105 #define REG_HDMI_INFOFRAME_CTRL0 0x0000002c 106 #define HDMI_INFOFRAME_CTRL0_AVI_SEND 0x00000001 107 #define HDMI_INFOFRAME_CTRL0_AVI_CONT 0x00000002 108 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND 0x00000010 109 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT 0x00000020 110 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE 0x00000040 111 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE 0x00000080 112 113 #define REG_HDMI_GEN_PKT_CTRL 0x00000034 114 #define HDMI_GEN_PKT_CTRL_GENERIC0_SEND 0x00000001 115 #define HDMI_GEN_PKT_CTRL_GENERIC0_CONT 0x00000002 116 #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK 0x0000000c 117 #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT 2 118 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val) 119 { 120 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK; 121 } 122 #define HDMI_GEN_PKT_CTRL_GENERIC1_SEND 0x00000010 123 #define HDMI_GEN_PKT_CTRL_GENERIC1_CONT 0x00000020 124 #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK 0x003f0000 125 #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT 16 126 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val) 127 { 128 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK; 129 } 130 #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK 0x3f000000 131 #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT 24 132 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val) 133 { 134 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK; 135 } 136 137 #define REG_HDMI_GC 0x00000040 138 #define HDMI_GC_MUTE 0x00000001 139 140 #define REG_HDMI_AUDIO_PKT_CTRL2 0x00000044 141 #define HDMI_AUDIO_PKT_CTRL2_OVERRIDE 0x00000001 142 #define HDMI_AUDIO_PKT_CTRL2_LAYOUT 0x00000002 143 144 static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; } 145 146 #define REG_HDMI_GENERIC0_HDR 0x00000084 147 148 static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; } 149 150 #define REG_HDMI_GENERIC1_HDR 0x000000a4 151 152 static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; } 153 154 static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } 155 156 static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } 157 #define HDMI_ACR_0_CTS__MASK 0xfffff000 158 #define HDMI_ACR_0_CTS__SHIFT 12 159 static inline uint32_t HDMI_ACR_0_CTS(uint32_t val) 160 { 161 return ((val) << HDMI_ACR_0_CTS__SHIFT) & HDMI_ACR_0_CTS__MASK; 162 } 163 164 static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; } 165 #define HDMI_ACR_1_N__MASK 0xffffffff 166 #define HDMI_ACR_1_N__SHIFT 0 167 static inline uint32_t HDMI_ACR_1_N(uint32_t val) 168 { 169 return ((val) << HDMI_ACR_1_N__SHIFT) & HDMI_ACR_1_N__MASK; 170 } 171 172 #define REG_HDMI_AUDIO_INFO0 0x000000e4 173 #define HDMI_AUDIO_INFO0_CHECKSUM__MASK 0x000000ff 174 #define HDMI_AUDIO_INFO0_CHECKSUM__SHIFT 0 175 static inline uint32_t HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val) 176 { 177 return ((val) << HDMI_AUDIO_INFO0_CHECKSUM__SHIFT) & HDMI_AUDIO_INFO0_CHECKSUM__MASK; 178 } 179 #define HDMI_AUDIO_INFO0_CC__MASK 0x00000700 180 #define HDMI_AUDIO_INFO0_CC__SHIFT 8 181 static inline uint32_t HDMI_AUDIO_INFO0_CC(uint32_t val) 182 { 183 return ((val) << HDMI_AUDIO_INFO0_CC__SHIFT) & HDMI_AUDIO_INFO0_CC__MASK; 184 } 185 186 #define REG_HDMI_AUDIO_INFO1 0x000000e8 187 #define HDMI_AUDIO_INFO1_CA__MASK 0x000000ff 188 #define HDMI_AUDIO_INFO1_CA__SHIFT 0 189 static inline uint32_t HDMI_AUDIO_INFO1_CA(uint32_t val) 190 { 191 return ((val) << HDMI_AUDIO_INFO1_CA__SHIFT) & HDMI_AUDIO_INFO1_CA__MASK; 192 } 193 #define HDMI_AUDIO_INFO1_LSV__MASK 0x00007800 194 #define HDMI_AUDIO_INFO1_LSV__SHIFT 11 195 static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val) 196 { 197 return ((val) << HDMI_AUDIO_INFO1_LSV__SHIFT) & HDMI_AUDIO_INFO1_LSV__MASK; 198 } 199 #define HDMI_AUDIO_INFO1_DM_INH 0x00008000 200 201 #define REG_HDMI_HDCP_CTRL 0x00000110 202 #define HDMI_HDCP_CTRL_ENABLE 0x00000001 203 #define HDMI_HDCP_CTRL_ENCRYPTION_ENABLE 0x00000100 204 205 #define REG_HDMI_HDCP_DEBUG_CTRL 0x00000114 206 #define HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER 0x00000004 207 208 #define REG_HDMI_HDCP_INT_CTRL 0x00000118 209 #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT 0x00000001 210 #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_ACK 0x00000002 211 #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_MASK 0x00000004 212 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT 0x00000010 213 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_ACK 0x00000020 214 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_MASK 0x00000040 215 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK 0x00000080 216 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_INT 0x00000100 217 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_ACK 0x00000200 218 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_MASK 0x00000400 219 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_INT 0x00001000 220 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_ACK 0x00002000 221 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_MASK 0x00004000 222 223 #define REG_HDMI_HDCP_LINK0_STATUS 0x0000011c 224 #define HDMI_HDCP_LINK0_STATUS_AN_0_READY 0x00000100 225 #define HDMI_HDCP_LINK0_STATUS_AN_1_READY 0x00000200 226 #define HDMI_HDCP_LINK0_STATUS_RI_MATCHES 0x00001000 227 #define HDMI_HDCP_LINK0_STATUS_V_MATCHES 0x00100000 228 #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK 0x70000000 229 #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT 28 230 static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val) 231 { 232 return ((val) << HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT) & HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK; 233 } 234 235 #define REG_HDMI_HDCP_DDC_CTRL_0 0x00000120 236 #define HDMI_HDCP_DDC_CTRL_0_DISABLE 0x00000001 237 238 #define REG_HDMI_HDCP_DDC_CTRL_1 0x00000124 239 #define HDMI_HDCP_DDC_CTRL_1_FAILED_ACK 0x00000001 240 241 #define REG_HDMI_HDCP_DDC_STATUS 0x00000128 242 #define HDMI_HDCP_DDC_STATUS_XFER_REQ 0x00000010 243 #define HDMI_HDCP_DDC_STATUS_XFER_DONE 0x00000400 244 #define HDMI_HDCP_DDC_STATUS_ABORTED 0x00001000 245 #define HDMI_HDCP_DDC_STATUS_TIMEOUT 0x00002000 246 #define HDMI_HDCP_DDC_STATUS_NACK0 0x00004000 247 #define HDMI_HDCP_DDC_STATUS_NACK1 0x00008000 248 #define HDMI_HDCP_DDC_STATUS_FAILED 0x00010000 249 250 #define REG_HDMI_HDCP_ENTROPY_CTRL0 0x0000012c 251 252 #define REG_HDMI_HDCP_ENTROPY_CTRL1 0x0000025c 253 254 #define REG_HDMI_HDCP_RESET 0x00000130 255 #define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE 0x00000001 256 257 #define REG_HDMI_HDCP_RCVPORT_DATA0 0x00000134 258 259 #define REG_HDMI_HDCP_RCVPORT_DATA1 0x00000138 260 261 #define REG_HDMI_HDCP_RCVPORT_DATA2_0 0x0000013c 262 263 #define REG_HDMI_HDCP_RCVPORT_DATA2_1 0x00000140 264 265 #define REG_HDMI_HDCP_RCVPORT_DATA3 0x00000144 266 267 #define REG_HDMI_HDCP_RCVPORT_DATA4 0x00000148 268 269 #define REG_HDMI_HDCP_RCVPORT_DATA5 0x0000014c 270 271 #define REG_HDMI_HDCP_RCVPORT_DATA6 0x00000150 272 273 #define REG_HDMI_HDCP_RCVPORT_DATA7 0x00000154 274 275 #define REG_HDMI_HDCP_RCVPORT_DATA8 0x00000158 276 277 #define REG_HDMI_HDCP_RCVPORT_DATA9 0x0000015c 278 279 #define REG_HDMI_HDCP_RCVPORT_DATA10 0x00000160 280 281 #define REG_HDMI_HDCP_RCVPORT_DATA11 0x00000164 282 283 #define REG_HDMI_HDCP_RCVPORT_DATA12 0x00000168 284 285 #define REG_HDMI_VENSPEC_INFO0 0x0000016c 286 287 #define REG_HDMI_VENSPEC_INFO1 0x00000170 288 289 #define REG_HDMI_VENSPEC_INFO2 0x00000174 290 291 #define REG_HDMI_VENSPEC_INFO3 0x00000178 292 293 #define REG_HDMI_VENSPEC_INFO4 0x0000017c 294 295 #define REG_HDMI_VENSPEC_INFO5 0x00000180 296 297 #define REG_HDMI_VENSPEC_INFO6 0x00000184 298 299 #define REG_HDMI_AUDIO_CFG 0x000001d0 300 #define HDMI_AUDIO_CFG_ENGINE_ENABLE 0x00000001 301 #define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK 0x000000f0 302 #define HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT 4 303 static inline uint32_t HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val) 304 { 305 return ((val) << HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT) & HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK; 306 } 307 308 #define REG_HDMI_USEC_REFTIMER 0x00000208 309 310 #define REG_HDMI_DDC_CTRL 0x0000020c 311 #define HDMI_DDC_CTRL_GO 0x00000001 312 #define HDMI_DDC_CTRL_SOFT_RESET 0x00000002 313 #define HDMI_DDC_CTRL_SEND_RESET 0x00000004 314 #define HDMI_DDC_CTRL_SW_STATUS_RESET 0x00000008 315 #define HDMI_DDC_CTRL_TRANSACTION_CNT__MASK 0x00300000 316 #define HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT 20 317 static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val) 318 { 319 return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK; 320 } 321 322 #define REG_HDMI_DDC_ARBITRATION 0x00000210 323 #define HDMI_DDC_ARBITRATION_HW_ARBITRATION 0x00000010 324 325 #define REG_HDMI_DDC_INT_CTRL 0x00000214 326 #define HDMI_DDC_INT_CTRL_SW_DONE_INT 0x00000001 327 #define HDMI_DDC_INT_CTRL_SW_DONE_ACK 0x00000002 328 #define HDMI_DDC_INT_CTRL_SW_DONE_MASK 0x00000004 329 330 #define REG_HDMI_DDC_SW_STATUS 0x00000218 331 #define HDMI_DDC_SW_STATUS_NACK0 0x00001000 332 #define HDMI_DDC_SW_STATUS_NACK1 0x00002000 333 #define HDMI_DDC_SW_STATUS_NACK2 0x00004000 334 #define HDMI_DDC_SW_STATUS_NACK3 0x00008000 335 336 #define REG_HDMI_DDC_HW_STATUS 0x0000021c 337 #define HDMI_DDC_HW_STATUS_DONE 0x00000008 338 339 #define REG_HDMI_DDC_SPEED 0x00000220 340 #define HDMI_DDC_SPEED_THRESHOLD__MASK 0x00000003 341 #define HDMI_DDC_SPEED_THRESHOLD__SHIFT 0 342 static inline uint32_t HDMI_DDC_SPEED_THRESHOLD(uint32_t val) 343 { 344 return ((val) << HDMI_DDC_SPEED_THRESHOLD__SHIFT) & HDMI_DDC_SPEED_THRESHOLD__MASK; 345 } 346 #define HDMI_DDC_SPEED_PRESCALE__MASK 0xffff0000 347 #define HDMI_DDC_SPEED_PRESCALE__SHIFT 16 348 static inline uint32_t HDMI_DDC_SPEED_PRESCALE(uint32_t val) 349 { 350 return ((val) << HDMI_DDC_SPEED_PRESCALE__SHIFT) & HDMI_DDC_SPEED_PRESCALE__MASK; 351 } 352 353 #define REG_HDMI_DDC_SETUP 0x00000224 354 #define HDMI_DDC_SETUP_TIMEOUT__MASK 0xff000000 355 #define HDMI_DDC_SETUP_TIMEOUT__SHIFT 24 356 static inline uint32_t HDMI_DDC_SETUP_TIMEOUT(uint32_t val) 357 { 358 return ((val) << HDMI_DDC_SETUP_TIMEOUT__SHIFT) & HDMI_DDC_SETUP_TIMEOUT__MASK; 359 } 360 361 static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; } 362 363 static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; } 364 #define HDMI_I2C_TRANSACTION_REG_RW__MASK 0x00000001 365 #define HDMI_I2C_TRANSACTION_REG_RW__SHIFT 0 366 static inline uint32_t HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val) 367 { 368 return ((val) << HDMI_I2C_TRANSACTION_REG_RW__SHIFT) & HDMI_I2C_TRANSACTION_REG_RW__MASK; 369 } 370 #define HDMI_I2C_TRANSACTION_REG_STOP_ON_NACK 0x00000100 371 #define HDMI_I2C_TRANSACTION_REG_START 0x00001000 372 #define HDMI_I2C_TRANSACTION_REG_STOP 0x00002000 373 #define HDMI_I2C_TRANSACTION_REG_CNT__MASK 0x00ff0000 374 #define HDMI_I2C_TRANSACTION_REG_CNT__SHIFT 16 375 static inline uint32_t HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val) 376 { 377 return ((val) << HDMI_I2C_TRANSACTION_REG_CNT__SHIFT) & HDMI_I2C_TRANSACTION_REG_CNT__MASK; 378 } 379 380 #define REG_HDMI_DDC_DATA 0x00000238 381 #define HDMI_DDC_DATA_DATA_RW__MASK 0x00000001 382 #define HDMI_DDC_DATA_DATA_RW__SHIFT 0 383 static inline uint32_t HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val) 384 { 385 return ((val) << HDMI_DDC_DATA_DATA_RW__SHIFT) & HDMI_DDC_DATA_DATA_RW__MASK; 386 } 387 #define HDMI_DDC_DATA_DATA__MASK 0x0000ff00 388 #define HDMI_DDC_DATA_DATA__SHIFT 8 389 static inline uint32_t HDMI_DDC_DATA_DATA(uint32_t val) 390 { 391 return ((val) << HDMI_DDC_DATA_DATA__SHIFT) & HDMI_DDC_DATA_DATA__MASK; 392 } 393 #define HDMI_DDC_DATA_INDEX__MASK 0x00ff0000 394 #define HDMI_DDC_DATA_INDEX__SHIFT 16 395 static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val) 396 { 397 return ((val) << HDMI_DDC_DATA_INDEX__SHIFT) & HDMI_DDC_DATA_INDEX__MASK; 398 } 399 #define HDMI_DDC_DATA_INDEX_WRITE 0x80000000 400 401 #define REG_HDMI_HDCP_SHA_CTRL 0x0000023c 402 403 #define REG_HDMI_HDCP_SHA_STATUS 0x00000240 404 #define HDMI_HDCP_SHA_STATUS_BLOCK_DONE 0x00000001 405 #define HDMI_HDCP_SHA_STATUS_COMP_DONE 0x00000010 406 407 #define REG_HDMI_HDCP_SHA_DATA 0x00000244 408 #define HDMI_HDCP_SHA_DATA_DONE 0x00000001 409 410 #define REG_HDMI_HPD_INT_STATUS 0x00000250 411 #define HDMI_HPD_INT_STATUS_INT 0x00000001 412 #define HDMI_HPD_INT_STATUS_CABLE_DETECTED 0x00000002 413 414 #define REG_HDMI_HPD_INT_CTRL 0x00000254 415 #define HDMI_HPD_INT_CTRL_INT_ACK 0x00000001 416 #define HDMI_HPD_INT_CTRL_INT_CONNECT 0x00000002 417 #define HDMI_HPD_INT_CTRL_INT_EN 0x00000004 418 #define HDMI_HPD_INT_CTRL_RX_INT_ACK 0x00000010 419 #define HDMI_HPD_INT_CTRL_RX_INT_EN 0x00000020 420 #define HDMI_HPD_INT_CTRL_RCV_PLUGIN_DET_MASK 0x00000200 421 422 #define REG_HDMI_HPD_CTRL 0x00000258 423 #define HDMI_HPD_CTRL_TIMEOUT__MASK 0x00001fff 424 #define HDMI_HPD_CTRL_TIMEOUT__SHIFT 0 425 static inline uint32_t HDMI_HPD_CTRL_TIMEOUT(uint32_t val) 426 { 427 return ((val) << HDMI_HPD_CTRL_TIMEOUT__SHIFT) & HDMI_HPD_CTRL_TIMEOUT__MASK; 428 } 429 #define HDMI_HPD_CTRL_ENABLE 0x10000000 430 431 #define REG_HDMI_DDC_REF 0x0000027c 432 #define HDMI_DDC_REF_REFTIMER_ENABLE 0x00010000 433 #define HDMI_DDC_REF_REFTIMER__MASK 0x0000ffff 434 #define HDMI_DDC_REF_REFTIMER__SHIFT 0 435 static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val) 436 { 437 return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK; 438 } 439 440 #define REG_HDMI_HDCP_SW_UPPER_AKSV 0x00000284 441 442 #define REG_HDMI_HDCP_SW_LOWER_AKSV 0x00000288 443 444 #define REG_HDMI_CEC_STATUS 0x00000298 445 446 #define REG_HDMI_CEC_INT 0x0000029c 447 448 #define REG_HDMI_CEC_ADDR 0x000002a0 449 450 #define REG_HDMI_CEC_TIME 0x000002a4 451 452 #define REG_HDMI_CEC_REFTIMER 0x000002a8 453 454 #define REG_HDMI_CEC_RD_DATA 0x000002ac 455 456 #define REG_HDMI_CEC_RD_FILTER 0x000002b0 457 458 #define REG_HDMI_ACTIVE_HSYNC 0x000002b4 459 #define HDMI_ACTIVE_HSYNC_START__MASK 0x00000fff 460 #define HDMI_ACTIVE_HSYNC_START__SHIFT 0 461 static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val) 462 { 463 return ((val) << HDMI_ACTIVE_HSYNC_START__SHIFT) & HDMI_ACTIVE_HSYNC_START__MASK; 464 } 465 #define HDMI_ACTIVE_HSYNC_END__MASK 0x0fff0000 466 #define HDMI_ACTIVE_HSYNC_END__SHIFT 16 467 static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val) 468 { 469 return ((val) << HDMI_ACTIVE_HSYNC_END__SHIFT) & HDMI_ACTIVE_HSYNC_END__MASK; 470 } 471 472 #define REG_HDMI_ACTIVE_VSYNC 0x000002b8 473 #define HDMI_ACTIVE_VSYNC_START__MASK 0x00000fff 474 #define HDMI_ACTIVE_VSYNC_START__SHIFT 0 475 static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val) 476 { 477 return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK; 478 } 479 #define HDMI_ACTIVE_VSYNC_END__MASK 0x0fff0000 480 #define HDMI_ACTIVE_VSYNC_END__SHIFT 16 481 static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val) 482 { 483 return ((val) << HDMI_ACTIVE_VSYNC_END__SHIFT) & HDMI_ACTIVE_VSYNC_END__MASK; 484 } 485 486 #define REG_HDMI_VSYNC_ACTIVE_F2 0x000002bc 487 #define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00000fff 488 #define HDMI_VSYNC_ACTIVE_F2_START__SHIFT 0 489 static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val) 490 { 491 return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK; 492 } 493 #define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x0fff0000 494 #define HDMI_VSYNC_ACTIVE_F2_END__SHIFT 16 495 static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val) 496 { 497 return ((val) << HDMI_VSYNC_ACTIVE_F2_END__SHIFT) & HDMI_VSYNC_ACTIVE_F2_END__MASK; 498 } 499 500 #define REG_HDMI_TOTAL 0x000002c0 501 #define HDMI_TOTAL_H_TOTAL__MASK 0x00000fff 502 #define HDMI_TOTAL_H_TOTAL__SHIFT 0 503 static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val) 504 { 505 return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK; 506 } 507 #define HDMI_TOTAL_V_TOTAL__MASK 0x0fff0000 508 #define HDMI_TOTAL_V_TOTAL__SHIFT 16 509 static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val) 510 { 511 return ((val) << HDMI_TOTAL_V_TOTAL__SHIFT) & HDMI_TOTAL_V_TOTAL__MASK; 512 } 513 514 #define REG_HDMI_VSYNC_TOTAL_F2 0x000002c4 515 #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00000fff 516 #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT 0 517 static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val) 518 { 519 return ((val) << HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT) & HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK; 520 } 521 522 #define REG_HDMI_FRAME_CTRL 0x000002c8 523 #define HDMI_FRAME_CTRL_RGB_MUX_SEL_BGR 0x00001000 524 #define HDMI_FRAME_CTRL_VSYNC_LOW 0x10000000 525 #define HDMI_FRAME_CTRL_HSYNC_LOW 0x20000000 526 #define HDMI_FRAME_CTRL_INTERLACED_EN 0x80000000 527 528 #define REG_HDMI_AUD_INT 0x000002cc 529 #define HDMI_AUD_INT_AUD_FIFO_URUN_INT 0x00000001 530 #define HDMI_AUD_INT_AUD_FIFO_URAN_MASK 0x00000002 531 #define HDMI_AUD_INT_AUD_SAM_DROP_INT 0x00000004 532 #define HDMI_AUD_INT_AUD_SAM_DROP_MASK 0x00000008 533 534 #define REG_HDMI_PHY_CTRL 0x000002d4 535 #define HDMI_PHY_CTRL_SW_RESET_PLL 0x00000001 536 #define HDMI_PHY_CTRL_SW_RESET_PLL_LOW 0x00000002 537 #define HDMI_PHY_CTRL_SW_RESET 0x00000004 538 #define HDMI_PHY_CTRL_SW_RESET_LOW 0x00000008 539 540 #define REG_HDMI_CEC_WR_RANGE 0x000002dc 541 542 #define REG_HDMI_CEC_RD_RANGE 0x000002e0 543 544 #define REG_HDMI_VERSION 0x000002e4 545 546 #define REG_HDMI_CEC_COMPL_CTL 0x00000360 547 548 #define REG_HDMI_CEC_RD_START_RANGE 0x00000364 549 550 #define REG_HDMI_CEC_RD_TOTAL_RANGE 0x00000368 551 552 #define REG_HDMI_CEC_RD_ERR_RESP_LO 0x0000036c 553 554 #define REG_HDMI_CEC_WR_CHECK_CONFIG 0x00000370 555 556 #define REG_HDMI_8x60_PHY_REG0 0x00000300 557 #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c 558 #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT 2 559 static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val) 560 { 561 return ((val) << HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT) & HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK; 562 } 563 564 #define REG_HDMI_8x60_PHY_REG1 0x00000304 565 #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK 0x000000f0 566 #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT 4 567 static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val) 568 { 569 return ((val) << HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT) & HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK; 570 } 571 #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK 0x0000000f 572 #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT 0 573 static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val) 574 { 575 return ((val) << HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT) & HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK; 576 } 577 578 #define REG_HDMI_8x60_PHY_REG2 0x00000308 579 #define HDMI_8x60_PHY_REG2_PD_DESER 0x00000001 580 #define HDMI_8x60_PHY_REG2_PD_DRIVE_1 0x00000002 581 #define HDMI_8x60_PHY_REG2_PD_DRIVE_2 0x00000004 582 #define HDMI_8x60_PHY_REG2_PD_DRIVE_3 0x00000008 583 #define HDMI_8x60_PHY_REG2_PD_DRIVE_4 0x00000010 584 #define HDMI_8x60_PHY_REG2_PD_PLL 0x00000020 585 #define HDMI_8x60_PHY_REG2_PD_PWRGEN 0x00000040 586 #define HDMI_8x60_PHY_REG2_RCV_SENSE_EN 0x00000080 587 588 #define REG_HDMI_8x60_PHY_REG3 0x0000030c 589 #define HDMI_8x60_PHY_REG3_PLL_ENABLE 0x00000001 590 591 #define REG_HDMI_8x60_PHY_REG4 0x00000310 592 593 #define REG_HDMI_8x60_PHY_REG5 0x00000314 594 595 #define REG_HDMI_8x60_PHY_REG6 0x00000318 596 597 #define REG_HDMI_8x60_PHY_REG7 0x0000031c 598 599 #define REG_HDMI_8x60_PHY_REG8 0x00000320 600 601 #define REG_HDMI_8x60_PHY_REG9 0x00000324 602 603 #define REG_HDMI_8x60_PHY_REG10 0x00000328 604 605 #define REG_HDMI_8x60_PHY_REG11 0x0000032c 606 607 #define REG_HDMI_8x60_PHY_REG12 0x00000330 608 #define HDMI_8x60_PHY_REG12_RETIMING_EN 0x00000001 609 #define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN 0x00000002 610 #define HDMI_8x60_PHY_REG12_FORCE_LOCK 0x00000010 611 612 #define REG_HDMI_8960_PHY_REG0 0x00000400 613 614 #define REG_HDMI_8960_PHY_REG1 0x00000404 615 616 #define REG_HDMI_8960_PHY_REG2 0x00000408 617 618 #define REG_HDMI_8960_PHY_REG3 0x0000040c 619 620 #define REG_HDMI_8960_PHY_REG4 0x00000410 621 622 #define REG_HDMI_8960_PHY_REG5 0x00000414 623 624 #define REG_HDMI_8960_PHY_REG6 0x00000418 625 626 #define REG_HDMI_8960_PHY_REG7 0x0000041c 627 628 #define REG_HDMI_8960_PHY_REG8 0x00000420 629 630 #define REG_HDMI_8960_PHY_REG9 0x00000424 631 632 #define REG_HDMI_8960_PHY_REG10 0x00000428 633 634 #define REG_HDMI_8960_PHY_REG11 0x0000042c 635 636 #define REG_HDMI_8960_PHY_REG12 0x00000430 637 #define HDMI_8960_PHY_REG12_SW_RESET 0x00000020 638 #define HDMI_8960_PHY_REG12_PWRDN_B 0x00000080 639 640 #define REG_HDMI_8960_PHY_REG_BIST_CFG 0x00000434 641 642 #define REG_HDMI_8960_PHY_DEBUG_BUS_SEL 0x00000438 643 644 #define REG_HDMI_8960_PHY_REG_MISC0 0x0000043c 645 646 #define REG_HDMI_8960_PHY_REG13 0x00000440 647 648 #define REG_HDMI_8960_PHY_REG14 0x00000444 649 650 #define REG_HDMI_8960_PHY_REG15 0x00000448 651 652 #define REG_HDMI_8960_PHY_PLL_REFCLK_CFG 0x00000500 653 654 #define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG 0x00000504 655 656 #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 0x00000508 657 658 #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 0x0000050c 659 660 #define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG 0x00000510 661 662 #define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG 0x00000514 663 664 #define REG_HDMI_8960_PHY_PLL_PWRDN_B 0x00000518 665 #define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL 0x00000002 666 #define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B 0x00000008 667 668 #define REG_HDMI_8960_PHY_PLL_SDM_CFG0 0x0000051c 669 670 #define REG_HDMI_8960_PHY_PLL_SDM_CFG1 0x00000520 671 672 #define REG_HDMI_8960_PHY_PLL_SDM_CFG2 0x00000524 673 674 #define REG_HDMI_8960_PHY_PLL_SDM_CFG3 0x00000528 675 676 #define REG_HDMI_8960_PHY_PLL_SDM_CFG4 0x0000052c 677 678 #define REG_HDMI_8960_PHY_PLL_SSC_CFG0 0x00000530 679 680 #define REG_HDMI_8960_PHY_PLL_SSC_CFG1 0x00000534 681 682 #define REG_HDMI_8960_PHY_PLL_SSC_CFG2 0x00000538 683 684 #define REG_HDMI_8960_PHY_PLL_SSC_CFG3 0x0000053c 685 686 #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 0x00000540 687 688 #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 0x00000544 689 690 #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 0x00000548 691 692 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 0x0000054c 693 694 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 0x00000550 695 696 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 0x00000554 697 698 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 0x00000558 699 700 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 0x0000055c 701 702 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 0x00000560 703 704 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 0x00000564 705 706 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 0x00000568 707 708 #define REG_HDMI_8960_PHY_PLL_DEBUG_SEL 0x0000056c 709 710 #define REG_HDMI_8960_PHY_PLL_MISC0 0x00000570 711 712 #define REG_HDMI_8960_PHY_PLL_MISC1 0x00000574 713 714 #define REG_HDMI_8960_PHY_PLL_MISC2 0x00000578 715 716 #define REG_HDMI_8960_PHY_PLL_MISC3 0x0000057c 717 718 #define REG_HDMI_8960_PHY_PLL_MISC4 0x00000580 719 720 #define REG_HDMI_8960_PHY_PLL_MISC5 0x00000584 721 722 #define REG_HDMI_8960_PHY_PLL_MISC6 0x00000588 723 724 #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0 0x0000058c 725 726 #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1 0x00000590 727 728 #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2 0x00000594 729 730 #define REG_HDMI_8960_PHY_PLL_STATUS0 0x00000598 731 #define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK 0x00000001 732 733 #define REG_HDMI_8960_PHY_PLL_STATUS1 0x0000059c 734 735 #define REG_HDMI_8x74_ANA_CFG0 0x00000000 736 737 #define REG_HDMI_8x74_ANA_CFG1 0x00000004 738 739 #define REG_HDMI_8x74_PD_CTRL0 0x00000010 740 741 #define REG_HDMI_8x74_PD_CTRL1 0x00000014 742 743 #define REG_HDMI_8x74_BIST_CFG0 0x00000034 744 745 #define REG_HDMI_8x74_BIST_PATN0 0x0000003c 746 747 #define REG_HDMI_8x74_BIST_PATN1 0x00000040 748 749 #define REG_HDMI_8x74_BIST_PATN2 0x00000044 750 751 #define REG_HDMI_8x74_BIST_PATN3 0x00000048 752 753 754 #endif /* HDMI_XML */ 755