1 #ifndef HDMI_XML 2 #define HDMI_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48) 14 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 15 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05) 17 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 18 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 19288 bytes, from 2013-08-11 18:14:15) 19 20 Copyright (C) 2013 by the following authors: 21 - Rob Clark <robdclark@gmail.com> (robclark) 22 23 Permission is hereby granted, free of charge, to any person obtaining 24 a copy of this software and associated documentation files (the 25 "Software"), to deal in the Software without restriction, including 26 without limitation the rights to use, copy, modify, merge, publish, 27 distribute, sublicense, and/or sell copies of the Software, and to 28 permit persons to whom the Software is furnished to do so, subject to 29 the following conditions: 30 31 The above copyright notice and this permission notice (including the 32 next paragraph) shall be included in all copies or substantial 33 portions of the Software. 34 35 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 37 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 38 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 39 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 40 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 41 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44 45 enum hdmi_hdcp_key_state { 46 NO_KEYS = 0, 47 NOT_CHECKED = 1, 48 CHECKING = 2, 49 KEYS_VALID = 3, 50 AKSV_INVALID = 4, 51 CHECKSUM_MISMATCH = 5, 52 }; 53 54 enum hdmi_ddc_read_write { 55 DDC_WRITE = 0, 56 DDC_READ = 1, 57 }; 58 59 enum hdmi_acr_cts { 60 ACR_NONE = 0, 61 ACR_32 = 1, 62 ACR_44 = 2, 63 ACR_48 = 3, 64 }; 65 66 #define REG_HDMI_CTRL 0x00000000 67 #define HDMI_CTRL_ENABLE 0x00000001 68 #define HDMI_CTRL_HDMI 0x00000002 69 #define HDMI_CTRL_ENCRYPTED 0x00000004 70 71 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020 72 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001 73 74 #define REG_HDMI_ACR_PKT_CTRL 0x00000024 75 #define HDMI_ACR_PKT_CTRL_CONT 0x00000001 76 #define HDMI_ACR_PKT_CTRL_SEND 0x00000002 77 #define HDMI_ACR_PKT_CTRL_SELECT__MASK 0x00000030 78 #define HDMI_ACR_PKT_CTRL_SELECT__SHIFT 4 79 static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val) 80 { 81 return ((val) << HDMI_ACR_PKT_CTRL_SELECT__SHIFT) & HDMI_ACR_PKT_CTRL_SELECT__MASK; 82 } 83 #define HDMI_ACR_PKT_CTRL_SOURCE 0x00000100 84 #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK 0x00070000 85 #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT 16 86 static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val) 87 { 88 return ((val) << HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT) & HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK; 89 } 90 #define HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY 0x80000000 91 92 #define REG_HDMI_VBI_PKT_CTRL 0x00000028 93 #define HDMI_VBI_PKT_CTRL_GC_ENABLE 0x00000010 94 #define HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME 0x00000020 95 #define HDMI_VBI_PKT_CTRL_ISRC_SEND 0x00000100 96 #define HDMI_VBI_PKT_CTRL_ISRC_CONTINUOUS 0x00000200 97 #define HDMI_VBI_PKT_CTRL_ACP_SEND 0x00001000 98 #define HDMI_VBI_PKT_CTRL_ACP_SRC_SW 0x00002000 99 100 #define REG_HDMI_INFOFRAME_CTRL0 0x0000002c 101 #define HDMI_INFOFRAME_CTRL0_AVI_SEND 0x00000001 102 #define HDMI_INFOFRAME_CTRL0_AVI_CONT 0x00000002 103 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND 0x00000010 104 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT 0x00000020 105 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE 0x00000040 106 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE 0x00000080 107 108 #define REG_HDMI_GEN_PKT_CTRL 0x00000034 109 #define HDMI_GEN_PKT_CTRL_GENERIC0_SEND 0x00000001 110 #define HDMI_GEN_PKT_CTRL_GENERIC0_CONT 0x00000002 111 #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK 0x0000000c 112 #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT 2 113 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val) 114 { 115 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK; 116 } 117 #define HDMI_GEN_PKT_CTRL_GENERIC1_SEND 0x00000010 118 #define HDMI_GEN_PKT_CTRL_GENERIC1_CONT 0x00000020 119 #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK 0x003f0000 120 #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT 16 121 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val) 122 { 123 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK; 124 } 125 #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK 0x3f000000 126 #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT 24 127 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val) 128 { 129 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK; 130 } 131 132 #define REG_HDMI_GC 0x00000040 133 #define HDMI_GC_MUTE 0x00000001 134 135 #define REG_HDMI_AUDIO_PKT_CTRL2 0x00000044 136 #define HDMI_AUDIO_PKT_CTRL2_OVERRIDE 0x00000001 137 #define HDMI_AUDIO_PKT_CTRL2_LAYOUT 0x00000002 138 139 static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; } 140 141 #define REG_HDMI_GENERIC0_HDR 0x00000084 142 143 static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; } 144 145 #define REG_HDMI_GENERIC1_HDR 0x000000a4 146 147 static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; } 148 149 static inline uint32_t REG_HDMI_ACR(uint32_t i0) { return 0x000000c4 + 0x8*i0; } 150 151 static inline uint32_t REG_HDMI_ACR_0(uint32_t i0) { return 0x000000c4 + 0x8*i0; } 152 #define HDMI_ACR_0_CTS__MASK 0xfffff000 153 #define HDMI_ACR_0_CTS__SHIFT 12 154 static inline uint32_t HDMI_ACR_0_CTS(uint32_t val) 155 { 156 return ((val) << HDMI_ACR_0_CTS__SHIFT) & HDMI_ACR_0_CTS__MASK; 157 } 158 159 static inline uint32_t REG_HDMI_ACR_1(uint32_t i0) { return 0x000000c8 + 0x8*i0; } 160 #define HDMI_ACR_1_N__MASK 0xffffffff 161 #define HDMI_ACR_1_N__SHIFT 0 162 static inline uint32_t HDMI_ACR_1_N(uint32_t val) 163 { 164 return ((val) << HDMI_ACR_1_N__SHIFT) & HDMI_ACR_1_N__MASK; 165 } 166 167 #define REG_HDMI_AUDIO_INFO0 0x000000e4 168 #define HDMI_AUDIO_INFO0_CHECKSUM__MASK 0x000000ff 169 #define HDMI_AUDIO_INFO0_CHECKSUM__SHIFT 0 170 static inline uint32_t HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val) 171 { 172 return ((val) << HDMI_AUDIO_INFO0_CHECKSUM__SHIFT) & HDMI_AUDIO_INFO0_CHECKSUM__MASK; 173 } 174 #define HDMI_AUDIO_INFO0_CC__MASK 0x00000700 175 #define HDMI_AUDIO_INFO0_CC__SHIFT 8 176 static inline uint32_t HDMI_AUDIO_INFO0_CC(uint32_t val) 177 { 178 return ((val) << HDMI_AUDIO_INFO0_CC__SHIFT) & HDMI_AUDIO_INFO0_CC__MASK; 179 } 180 181 #define REG_HDMI_AUDIO_INFO1 0x000000e8 182 #define HDMI_AUDIO_INFO1_CA__MASK 0x000000ff 183 #define HDMI_AUDIO_INFO1_CA__SHIFT 0 184 static inline uint32_t HDMI_AUDIO_INFO1_CA(uint32_t val) 185 { 186 return ((val) << HDMI_AUDIO_INFO1_CA__SHIFT) & HDMI_AUDIO_INFO1_CA__MASK; 187 } 188 #define HDMI_AUDIO_INFO1_LSV__MASK 0x00007800 189 #define HDMI_AUDIO_INFO1_LSV__SHIFT 11 190 static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val) 191 { 192 return ((val) << HDMI_AUDIO_INFO1_LSV__SHIFT) & HDMI_AUDIO_INFO1_LSV__MASK; 193 } 194 #define HDMI_AUDIO_INFO1_DM_INH 0x00008000 195 196 #define REG_HDMI_HDCP_CTRL 0x00000110 197 #define HDMI_HDCP_CTRL_ENABLE 0x00000001 198 #define HDMI_HDCP_CTRL_ENCRYPTION_ENABLE 0x00000100 199 200 #define REG_HDMI_HDCP_INT_CTRL 0x00000118 201 202 #define REG_HDMI_HDCP_LINK0_STATUS 0x0000011c 203 #define HDMI_HDCP_LINK0_STATUS_AN_0_READY 0x00000100 204 #define HDMI_HDCP_LINK0_STATUS_AN_1_READY 0x00000200 205 #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK 0x70000000 206 #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT 28 207 static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val) 208 { 209 return ((val) << HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT) & HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK; 210 } 211 212 #define REG_HDMI_HDCP_RESET 0x00000130 213 #define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE 0x00000001 214 215 #define REG_HDMI_AUDIO_CFG 0x000001d0 216 #define HDMI_AUDIO_CFG_ENGINE_ENABLE 0x00000001 217 #define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK 0x000000f0 218 #define HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT 4 219 static inline uint32_t HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val) 220 { 221 return ((val) << HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT) & HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK; 222 } 223 224 #define REG_HDMI_USEC_REFTIMER 0x00000208 225 226 #define REG_HDMI_DDC_CTRL 0x0000020c 227 #define HDMI_DDC_CTRL_GO 0x00000001 228 #define HDMI_DDC_CTRL_SOFT_RESET 0x00000002 229 #define HDMI_DDC_CTRL_SEND_RESET 0x00000004 230 #define HDMI_DDC_CTRL_SW_STATUS_RESET 0x00000008 231 #define HDMI_DDC_CTRL_TRANSACTION_CNT__MASK 0x00300000 232 #define HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT 20 233 static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val) 234 { 235 return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK; 236 } 237 238 #define REG_HDMI_DDC_INT_CTRL 0x00000214 239 #define HDMI_DDC_INT_CTRL_SW_DONE_INT 0x00000001 240 #define HDMI_DDC_INT_CTRL_SW_DONE_ACK 0x00000002 241 #define HDMI_DDC_INT_CTRL_SW_DONE_MASK 0x00000004 242 243 #define REG_HDMI_DDC_SW_STATUS 0x00000218 244 #define HDMI_DDC_SW_STATUS_NACK0 0x00001000 245 #define HDMI_DDC_SW_STATUS_NACK1 0x00002000 246 #define HDMI_DDC_SW_STATUS_NACK2 0x00004000 247 #define HDMI_DDC_SW_STATUS_NACK3 0x00008000 248 249 #define REG_HDMI_DDC_HW_STATUS 0x0000021c 250 251 #define REG_HDMI_DDC_SPEED 0x00000220 252 #define HDMI_DDC_SPEED_THRESHOLD__MASK 0x00000003 253 #define HDMI_DDC_SPEED_THRESHOLD__SHIFT 0 254 static inline uint32_t HDMI_DDC_SPEED_THRESHOLD(uint32_t val) 255 { 256 return ((val) << HDMI_DDC_SPEED_THRESHOLD__SHIFT) & HDMI_DDC_SPEED_THRESHOLD__MASK; 257 } 258 #define HDMI_DDC_SPEED_PRESCALE__MASK 0xffff0000 259 #define HDMI_DDC_SPEED_PRESCALE__SHIFT 16 260 static inline uint32_t HDMI_DDC_SPEED_PRESCALE(uint32_t val) 261 { 262 return ((val) << HDMI_DDC_SPEED_PRESCALE__SHIFT) & HDMI_DDC_SPEED_PRESCALE__MASK; 263 } 264 265 #define REG_HDMI_DDC_SETUP 0x00000224 266 #define HDMI_DDC_SETUP_TIMEOUT__MASK 0xff000000 267 #define HDMI_DDC_SETUP_TIMEOUT__SHIFT 24 268 static inline uint32_t HDMI_DDC_SETUP_TIMEOUT(uint32_t val) 269 { 270 return ((val) << HDMI_DDC_SETUP_TIMEOUT__SHIFT) & HDMI_DDC_SETUP_TIMEOUT__MASK; 271 } 272 273 static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; } 274 275 static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; } 276 #define HDMI_I2C_TRANSACTION_REG_RW__MASK 0x00000001 277 #define HDMI_I2C_TRANSACTION_REG_RW__SHIFT 0 278 static inline uint32_t HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val) 279 { 280 return ((val) << HDMI_I2C_TRANSACTION_REG_RW__SHIFT) & HDMI_I2C_TRANSACTION_REG_RW__MASK; 281 } 282 #define HDMI_I2C_TRANSACTION_REG_STOP_ON_NACK 0x00000100 283 #define HDMI_I2C_TRANSACTION_REG_START 0x00001000 284 #define HDMI_I2C_TRANSACTION_REG_STOP 0x00002000 285 #define HDMI_I2C_TRANSACTION_REG_CNT__MASK 0x00ff0000 286 #define HDMI_I2C_TRANSACTION_REG_CNT__SHIFT 16 287 static inline uint32_t HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val) 288 { 289 return ((val) << HDMI_I2C_TRANSACTION_REG_CNT__SHIFT) & HDMI_I2C_TRANSACTION_REG_CNT__MASK; 290 } 291 292 #define REG_HDMI_DDC_DATA 0x00000238 293 #define HDMI_DDC_DATA_DATA_RW__MASK 0x00000001 294 #define HDMI_DDC_DATA_DATA_RW__SHIFT 0 295 static inline uint32_t HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val) 296 { 297 return ((val) << HDMI_DDC_DATA_DATA_RW__SHIFT) & HDMI_DDC_DATA_DATA_RW__MASK; 298 } 299 #define HDMI_DDC_DATA_DATA__MASK 0x0000ff00 300 #define HDMI_DDC_DATA_DATA__SHIFT 8 301 static inline uint32_t HDMI_DDC_DATA_DATA(uint32_t val) 302 { 303 return ((val) << HDMI_DDC_DATA_DATA__SHIFT) & HDMI_DDC_DATA_DATA__MASK; 304 } 305 #define HDMI_DDC_DATA_INDEX__MASK 0x00ff0000 306 #define HDMI_DDC_DATA_INDEX__SHIFT 16 307 static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val) 308 { 309 return ((val) << HDMI_DDC_DATA_INDEX__SHIFT) & HDMI_DDC_DATA_INDEX__MASK; 310 } 311 #define HDMI_DDC_DATA_INDEX_WRITE 0x80000000 312 313 #define REG_HDMI_HPD_INT_STATUS 0x00000250 314 #define HDMI_HPD_INT_STATUS_INT 0x00000001 315 #define HDMI_HPD_INT_STATUS_CABLE_DETECTED 0x00000002 316 317 #define REG_HDMI_HPD_INT_CTRL 0x00000254 318 #define HDMI_HPD_INT_CTRL_INT_ACK 0x00000001 319 #define HDMI_HPD_INT_CTRL_INT_CONNECT 0x00000002 320 #define HDMI_HPD_INT_CTRL_INT_EN 0x00000004 321 #define HDMI_HPD_INT_CTRL_RX_INT_ACK 0x00000010 322 #define HDMI_HPD_INT_CTRL_RX_INT_EN 0x00000020 323 #define HDMI_HPD_INT_CTRL_RCV_PLUGIN_DET_MASK 0x00000200 324 325 #define REG_HDMI_HPD_CTRL 0x00000258 326 #define HDMI_HPD_CTRL_TIMEOUT__MASK 0x00001fff 327 #define HDMI_HPD_CTRL_TIMEOUT__SHIFT 0 328 static inline uint32_t HDMI_HPD_CTRL_TIMEOUT(uint32_t val) 329 { 330 return ((val) << HDMI_HPD_CTRL_TIMEOUT__SHIFT) & HDMI_HPD_CTRL_TIMEOUT__MASK; 331 } 332 #define HDMI_HPD_CTRL_ENABLE 0x10000000 333 334 #define REG_HDMI_DDC_REF 0x0000027c 335 #define HDMI_DDC_REF_REFTIMER_ENABLE 0x00010000 336 #define HDMI_DDC_REF_REFTIMER__MASK 0x0000ffff 337 #define HDMI_DDC_REF_REFTIMER__SHIFT 0 338 static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val) 339 { 340 return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK; 341 } 342 343 #define REG_HDMI_ACTIVE_HSYNC 0x000002b4 344 #define HDMI_ACTIVE_HSYNC_START__MASK 0x00000fff 345 #define HDMI_ACTIVE_HSYNC_START__SHIFT 0 346 static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val) 347 { 348 return ((val) << HDMI_ACTIVE_HSYNC_START__SHIFT) & HDMI_ACTIVE_HSYNC_START__MASK; 349 } 350 #define HDMI_ACTIVE_HSYNC_END__MASK 0x0fff0000 351 #define HDMI_ACTIVE_HSYNC_END__SHIFT 16 352 static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val) 353 { 354 return ((val) << HDMI_ACTIVE_HSYNC_END__SHIFT) & HDMI_ACTIVE_HSYNC_END__MASK; 355 } 356 357 #define REG_HDMI_ACTIVE_VSYNC 0x000002b8 358 #define HDMI_ACTIVE_VSYNC_START__MASK 0x00000fff 359 #define HDMI_ACTIVE_VSYNC_START__SHIFT 0 360 static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val) 361 { 362 return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK; 363 } 364 #define HDMI_ACTIVE_VSYNC_END__MASK 0x0fff0000 365 #define HDMI_ACTIVE_VSYNC_END__SHIFT 16 366 static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val) 367 { 368 return ((val) << HDMI_ACTIVE_VSYNC_END__SHIFT) & HDMI_ACTIVE_VSYNC_END__MASK; 369 } 370 371 #define REG_HDMI_VSYNC_ACTIVE_F2 0x000002bc 372 #define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00000fff 373 #define HDMI_VSYNC_ACTIVE_F2_START__SHIFT 0 374 static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val) 375 { 376 return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK; 377 } 378 #define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x0fff0000 379 #define HDMI_VSYNC_ACTIVE_F2_END__SHIFT 16 380 static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val) 381 { 382 return ((val) << HDMI_VSYNC_ACTIVE_F2_END__SHIFT) & HDMI_VSYNC_ACTIVE_F2_END__MASK; 383 } 384 385 #define REG_HDMI_TOTAL 0x000002c0 386 #define HDMI_TOTAL_H_TOTAL__MASK 0x00000fff 387 #define HDMI_TOTAL_H_TOTAL__SHIFT 0 388 static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val) 389 { 390 return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK; 391 } 392 #define HDMI_TOTAL_V_TOTAL__MASK 0x0fff0000 393 #define HDMI_TOTAL_V_TOTAL__SHIFT 16 394 static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val) 395 { 396 return ((val) << HDMI_TOTAL_V_TOTAL__SHIFT) & HDMI_TOTAL_V_TOTAL__MASK; 397 } 398 399 #define REG_HDMI_VSYNC_TOTAL_F2 0x000002c4 400 #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00000fff 401 #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT 0 402 static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val) 403 { 404 return ((val) << HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT) & HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK; 405 } 406 407 #define REG_HDMI_FRAME_CTRL 0x000002c8 408 #define HDMI_FRAME_CTRL_RGB_MUX_SEL_BGR 0x00001000 409 #define HDMI_FRAME_CTRL_VSYNC_LOW 0x10000000 410 #define HDMI_FRAME_CTRL_HSYNC_LOW 0x20000000 411 #define HDMI_FRAME_CTRL_INTERLACED_EN 0x80000000 412 413 #define REG_HDMI_PHY_CTRL 0x000002d4 414 #define HDMI_PHY_CTRL_SW_RESET_PLL 0x00000001 415 #define HDMI_PHY_CTRL_SW_RESET_PLL_LOW 0x00000002 416 #define HDMI_PHY_CTRL_SW_RESET 0x00000004 417 #define HDMI_PHY_CTRL_SW_RESET_LOW 0x00000008 418 419 #define REG_HDMI_AUD_INT 0x000002cc 420 #define HDMI_AUD_INT_AUD_FIFO_URUN_INT 0x00000001 421 #define HDMI_AUD_INT_AUD_FIFO_URAN_MASK 0x00000002 422 #define HDMI_AUD_INT_AUD_SAM_DROP_INT 0x00000004 423 #define HDMI_AUD_INT_AUD_SAM_DROP_MASK 0x00000008 424 425 #define REG_HDMI_8x60_PHY_REG0 0x00000300 426 #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c 427 #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT 2 428 static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val) 429 { 430 return ((val) << HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT) & HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK; 431 } 432 433 #define REG_HDMI_8x60_PHY_REG1 0x00000304 434 #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK 0x000000f0 435 #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT 4 436 static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val) 437 { 438 return ((val) << HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT) & HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK; 439 } 440 #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK 0x0000000f 441 #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT 0 442 static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val) 443 { 444 return ((val) << HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT) & HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK; 445 } 446 447 #define REG_HDMI_8x60_PHY_REG2 0x00000308 448 #define HDMI_8x60_PHY_REG2_PD_DESER 0x00000001 449 #define HDMI_8x60_PHY_REG2_PD_DRIVE_1 0x00000002 450 #define HDMI_8x60_PHY_REG2_PD_DRIVE_2 0x00000004 451 #define HDMI_8x60_PHY_REG2_PD_DRIVE_3 0x00000008 452 #define HDMI_8x60_PHY_REG2_PD_DRIVE_4 0x00000010 453 #define HDMI_8x60_PHY_REG2_PD_PLL 0x00000020 454 #define HDMI_8x60_PHY_REG2_PD_PWRGEN 0x00000040 455 #define HDMI_8x60_PHY_REG2_RCV_SENSE_EN 0x00000080 456 457 #define REG_HDMI_8x60_PHY_REG3 0x0000030c 458 #define HDMI_8x60_PHY_REG3_PLL_ENABLE 0x00000001 459 460 #define REG_HDMI_8x60_PHY_REG4 0x00000310 461 462 #define REG_HDMI_8x60_PHY_REG5 0x00000314 463 464 #define REG_HDMI_8x60_PHY_REG6 0x00000318 465 466 #define REG_HDMI_8x60_PHY_REG7 0x0000031c 467 468 #define REG_HDMI_8x60_PHY_REG8 0x00000320 469 470 #define REG_HDMI_8x60_PHY_REG9 0x00000324 471 472 #define REG_HDMI_8x60_PHY_REG10 0x00000328 473 474 #define REG_HDMI_8x60_PHY_REG11 0x0000032c 475 476 #define REG_HDMI_8x60_PHY_REG12 0x00000330 477 #define HDMI_8x60_PHY_REG12_RETIMING_EN 0x00000001 478 #define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN 0x00000002 479 #define HDMI_8x60_PHY_REG12_FORCE_LOCK 0x00000010 480 481 #define REG_HDMI_8960_PHY_REG0 0x00000400 482 483 #define REG_HDMI_8960_PHY_REG1 0x00000404 484 485 #define REG_HDMI_8960_PHY_REG2 0x00000408 486 487 #define REG_HDMI_8960_PHY_REG3 0x0000040c 488 489 #define REG_HDMI_8960_PHY_REG4 0x00000410 490 491 #define REG_HDMI_8960_PHY_REG5 0x00000414 492 493 #define REG_HDMI_8960_PHY_REG6 0x00000418 494 495 #define REG_HDMI_8960_PHY_REG7 0x0000041c 496 497 #define REG_HDMI_8960_PHY_REG8 0x00000420 498 499 #define REG_HDMI_8960_PHY_REG9 0x00000424 500 501 #define REG_HDMI_8960_PHY_REG10 0x00000428 502 503 #define REG_HDMI_8960_PHY_REG11 0x0000042c 504 505 #define REG_HDMI_8960_PHY_REG12 0x00000430 506 507 508 #endif /* HDMI_XML */ 509