10cf6c71dSRob Clark #ifndef HDMI_XML 20cf6c71dSRob Clark #define HDMI_XML 30cf6c71dSRob Clark 40cf6c71dSRob Clark /* Autogenerated file, DO NOT EDIT manually! 50cf6c71dSRob Clark 60cf6c71dSRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 722ba8b6bSRob Clark http://github.com/freedreno/envytools/ 822ba8b6bSRob Clark git clone https://github.com/freedreno/envytools.git 90cf6c71dSRob Clark 100cf6c71dSRob Clark The rules-ng-ng source files this header was generated from are: 118a264743SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) 120cf6c71dSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13af6cb4c1SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22) 14af6cb4c1SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42) 15af6cb4c1SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03) 16af6cb4c1SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23) 170cf6c71dSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 18bc00ae02SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) 190cf6c71dSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 20af6cb4c1SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23) 21af6cb4c1SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23) 220cf6c71dSRob Clark 238a264743SRob Clark Copyright (C) 2013-2015 by the following authors: 240cf6c71dSRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 250cf6c71dSRob Clark 260cf6c71dSRob Clark Permission is hereby granted, free of charge, to any person obtaining 270cf6c71dSRob Clark a copy of this software and associated documentation files (the 280cf6c71dSRob Clark "Software"), to deal in the Software without restriction, including 290cf6c71dSRob Clark without limitation the rights to use, copy, modify, merge, publish, 300cf6c71dSRob Clark distribute, sublicense, and/or sell copies of the Software, and to 310cf6c71dSRob Clark permit persons to whom the Software is furnished to do so, subject to 320cf6c71dSRob Clark the following conditions: 330cf6c71dSRob Clark 340cf6c71dSRob Clark The above copyright notice and this permission notice (including the 350cf6c71dSRob Clark next paragraph) shall be included in all copies or substantial 360cf6c71dSRob Clark portions of the Software. 370cf6c71dSRob Clark 380cf6c71dSRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 390cf6c71dSRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 400cf6c71dSRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 410cf6c71dSRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 420cf6c71dSRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 430cf6c71dSRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 440cf6c71dSRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 450cf6c71dSRob Clark */ 460cf6c71dSRob Clark 470cf6c71dSRob Clark 480cf6c71dSRob Clark enum hdmi_hdcp_key_state { 498a264743SRob Clark HDCP_KEYS_STATE_NO_KEYS = 0, 508a264743SRob Clark HDCP_KEYS_STATE_NOT_CHECKED = 1, 518a264743SRob Clark HDCP_KEYS_STATE_CHECKING = 2, 528a264743SRob Clark HDCP_KEYS_STATE_VALID = 3, 538a264743SRob Clark HDCP_KEYS_STATE_AKSV_NOT_VALID = 4, 548a264743SRob Clark HDCP_KEYS_STATE_CHKSUM_MISMATCH = 5, 558a264743SRob Clark HDCP_KEYS_STATE_PROD_AKSV = 6, 568a264743SRob Clark HDCP_KEYS_STATE_RESERVED = 7, 570cf6c71dSRob Clark }; 580cf6c71dSRob Clark 590cf6c71dSRob Clark enum hdmi_ddc_read_write { 600cf6c71dSRob Clark DDC_WRITE = 0, 610cf6c71dSRob Clark DDC_READ = 1, 620cf6c71dSRob Clark }; 630cf6c71dSRob Clark 640cf6c71dSRob Clark enum hdmi_acr_cts { 650cf6c71dSRob Clark ACR_NONE = 0, 660cf6c71dSRob Clark ACR_32 = 1, 670cf6c71dSRob Clark ACR_44 = 2, 680cf6c71dSRob Clark ACR_48 = 3, 690cf6c71dSRob Clark }; 700cf6c71dSRob Clark 710cf6c71dSRob Clark #define REG_HDMI_CTRL 0x00000000 720cf6c71dSRob Clark #define HDMI_CTRL_ENABLE 0x00000001 730cf6c71dSRob Clark #define HDMI_CTRL_HDMI 0x00000002 740cf6c71dSRob Clark #define HDMI_CTRL_ENCRYPTED 0x00000004 750cf6c71dSRob Clark 760cf6c71dSRob Clark #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020 770cf6c71dSRob Clark #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001 780cf6c71dSRob Clark 790cf6c71dSRob Clark #define REG_HDMI_ACR_PKT_CTRL 0x00000024 800cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_CONT 0x00000001 810cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_SEND 0x00000002 820cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_SELECT__MASK 0x00000030 830cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_SELECT__SHIFT 4 840cf6c71dSRob Clark static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val) 850cf6c71dSRob Clark { 860cf6c71dSRob Clark return ((val) << HDMI_ACR_PKT_CTRL_SELECT__SHIFT) & HDMI_ACR_PKT_CTRL_SELECT__MASK; 870cf6c71dSRob Clark } 880cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_SOURCE 0x00000100 890cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK 0x00070000 900cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT 16 910cf6c71dSRob Clark static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val) 920cf6c71dSRob Clark { 930cf6c71dSRob Clark return ((val) << HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT) & HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK; 940cf6c71dSRob Clark } 950cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY 0x80000000 960cf6c71dSRob Clark 970cf6c71dSRob Clark #define REG_HDMI_VBI_PKT_CTRL 0x00000028 980cf6c71dSRob Clark #define HDMI_VBI_PKT_CTRL_GC_ENABLE 0x00000010 990cf6c71dSRob Clark #define HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME 0x00000020 1000cf6c71dSRob Clark #define HDMI_VBI_PKT_CTRL_ISRC_SEND 0x00000100 1010cf6c71dSRob Clark #define HDMI_VBI_PKT_CTRL_ISRC_CONTINUOUS 0x00000200 1020cf6c71dSRob Clark #define HDMI_VBI_PKT_CTRL_ACP_SEND 0x00001000 1030cf6c71dSRob Clark #define HDMI_VBI_PKT_CTRL_ACP_SRC_SW 0x00002000 1040cf6c71dSRob Clark 1050cf6c71dSRob Clark #define REG_HDMI_INFOFRAME_CTRL0 0x0000002c 1060cf6c71dSRob Clark #define HDMI_INFOFRAME_CTRL0_AVI_SEND 0x00000001 1070cf6c71dSRob Clark #define HDMI_INFOFRAME_CTRL0_AVI_CONT 0x00000002 1080cf6c71dSRob Clark #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND 0x00000010 1090cf6c71dSRob Clark #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT 0x00000020 1100cf6c71dSRob Clark #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE 0x00000040 1110cf6c71dSRob Clark #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE 0x00000080 1120cf6c71dSRob Clark 1130cf6c71dSRob Clark #define REG_HDMI_GEN_PKT_CTRL 0x00000034 1140cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC0_SEND 0x00000001 1150cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC0_CONT 0x00000002 1160cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK 0x0000000c 1170cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT 2 1180cf6c71dSRob Clark static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val) 1190cf6c71dSRob Clark { 1200cf6c71dSRob Clark return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK; 1210cf6c71dSRob Clark } 1220cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC1_SEND 0x00000010 1230cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC1_CONT 0x00000020 1240cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK 0x003f0000 1250cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT 16 1260cf6c71dSRob Clark static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val) 1270cf6c71dSRob Clark { 1280cf6c71dSRob Clark return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK; 1290cf6c71dSRob Clark } 1300cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK 0x3f000000 1310cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT 24 1320cf6c71dSRob Clark static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val) 1330cf6c71dSRob Clark { 1340cf6c71dSRob Clark return ((val) << HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK; 1350cf6c71dSRob Clark } 1360cf6c71dSRob Clark 1370cf6c71dSRob Clark #define REG_HDMI_GC 0x00000040 1380cf6c71dSRob Clark #define HDMI_GC_MUTE 0x00000001 1390cf6c71dSRob Clark 1400cf6c71dSRob Clark #define REG_HDMI_AUDIO_PKT_CTRL2 0x00000044 1410cf6c71dSRob Clark #define HDMI_AUDIO_PKT_CTRL2_OVERRIDE 0x00000001 1420cf6c71dSRob Clark #define HDMI_AUDIO_PKT_CTRL2_LAYOUT 0x00000002 1430cf6c71dSRob Clark 1440cf6c71dSRob Clark static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; } 1450cf6c71dSRob Clark 1460cf6c71dSRob Clark #define REG_HDMI_GENERIC0_HDR 0x00000084 1470cf6c71dSRob Clark 1480cf6c71dSRob Clark static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; } 1490cf6c71dSRob Clark 1500cf6c71dSRob Clark #define REG_HDMI_GENERIC1_HDR 0x000000a4 1510cf6c71dSRob Clark 1520cf6c71dSRob Clark static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; } 1530cf6c71dSRob Clark 15489301471SRob Clark static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } 1550cf6c71dSRob Clark 15689301471SRob Clark static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } 1570cf6c71dSRob Clark #define HDMI_ACR_0_CTS__MASK 0xfffff000 1580cf6c71dSRob Clark #define HDMI_ACR_0_CTS__SHIFT 12 1590cf6c71dSRob Clark static inline uint32_t HDMI_ACR_0_CTS(uint32_t val) 1600cf6c71dSRob Clark { 1610cf6c71dSRob Clark return ((val) << HDMI_ACR_0_CTS__SHIFT) & HDMI_ACR_0_CTS__MASK; 1620cf6c71dSRob Clark } 1630cf6c71dSRob Clark 16489301471SRob Clark static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; } 1650cf6c71dSRob Clark #define HDMI_ACR_1_N__MASK 0xffffffff 1660cf6c71dSRob Clark #define HDMI_ACR_1_N__SHIFT 0 1670cf6c71dSRob Clark static inline uint32_t HDMI_ACR_1_N(uint32_t val) 1680cf6c71dSRob Clark { 1690cf6c71dSRob Clark return ((val) << HDMI_ACR_1_N__SHIFT) & HDMI_ACR_1_N__MASK; 1700cf6c71dSRob Clark } 1710cf6c71dSRob Clark 1720cf6c71dSRob Clark #define REG_HDMI_AUDIO_INFO0 0x000000e4 1730cf6c71dSRob Clark #define HDMI_AUDIO_INFO0_CHECKSUM__MASK 0x000000ff 1740cf6c71dSRob Clark #define HDMI_AUDIO_INFO0_CHECKSUM__SHIFT 0 1750cf6c71dSRob Clark static inline uint32_t HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val) 1760cf6c71dSRob Clark { 1770cf6c71dSRob Clark return ((val) << HDMI_AUDIO_INFO0_CHECKSUM__SHIFT) & HDMI_AUDIO_INFO0_CHECKSUM__MASK; 1780cf6c71dSRob Clark } 1790cf6c71dSRob Clark #define HDMI_AUDIO_INFO0_CC__MASK 0x00000700 1800cf6c71dSRob Clark #define HDMI_AUDIO_INFO0_CC__SHIFT 8 1810cf6c71dSRob Clark static inline uint32_t HDMI_AUDIO_INFO0_CC(uint32_t val) 1820cf6c71dSRob Clark { 1830cf6c71dSRob Clark return ((val) << HDMI_AUDIO_INFO0_CC__SHIFT) & HDMI_AUDIO_INFO0_CC__MASK; 1840cf6c71dSRob Clark } 1850cf6c71dSRob Clark 1860cf6c71dSRob Clark #define REG_HDMI_AUDIO_INFO1 0x000000e8 1870cf6c71dSRob Clark #define HDMI_AUDIO_INFO1_CA__MASK 0x000000ff 1880cf6c71dSRob Clark #define HDMI_AUDIO_INFO1_CA__SHIFT 0 1890cf6c71dSRob Clark static inline uint32_t HDMI_AUDIO_INFO1_CA(uint32_t val) 1900cf6c71dSRob Clark { 1910cf6c71dSRob Clark return ((val) << HDMI_AUDIO_INFO1_CA__SHIFT) & HDMI_AUDIO_INFO1_CA__MASK; 1920cf6c71dSRob Clark } 1930cf6c71dSRob Clark #define HDMI_AUDIO_INFO1_LSV__MASK 0x00007800 1940cf6c71dSRob Clark #define HDMI_AUDIO_INFO1_LSV__SHIFT 11 1950cf6c71dSRob Clark static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val) 1960cf6c71dSRob Clark { 1970cf6c71dSRob Clark return ((val) << HDMI_AUDIO_INFO1_LSV__SHIFT) & HDMI_AUDIO_INFO1_LSV__MASK; 1980cf6c71dSRob Clark } 1990cf6c71dSRob Clark #define HDMI_AUDIO_INFO1_DM_INH 0x00008000 2000cf6c71dSRob Clark 2010cf6c71dSRob Clark #define REG_HDMI_HDCP_CTRL 0x00000110 2020cf6c71dSRob Clark #define HDMI_HDCP_CTRL_ENABLE 0x00000001 2030cf6c71dSRob Clark #define HDMI_HDCP_CTRL_ENCRYPTION_ENABLE 0x00000100 2040cf6c71dSRob Clark 2058a264743SRob Clark #define REG_HDMI_HDCP_DEBUG_CTRL 0x00000114 2068a264743SRob Clark #define HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER 0x00000004 2078a264743SRob Clark 2080cf6c71dSRob Clark #define REG_HDMI_HDCP_INT_CTRL 0x00000118 2098a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT 0x00000001 2108a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_ACK 0x00000002 2118a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_MASK 0x00000004 2128a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT 0x00000010 2138a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_ACK 0x00000020 2148a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_MASK 0x00000040 2158a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK 0x00000080 2168a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_INT 0x00000100 2178a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_ACK 0x00000200 2188a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_MASK 0x00000400 2198a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_INT 0x00001000 2208a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_ACK 0x00002000 2218a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_MASK 0x00004000 2220cf6c71dSRob Clark 2230cf6c71dSRob Clark #define REG_HDMI_HDCP_LINK0_STATUS 0x0000011c 2240cf6c71dSRob Clark #define HDMI_HDCP_LINK0_STATUS_AN_0_READY 0x00000100 2250cf6c71dSRob Clark #define HDMI_HDCP_LINK0_STATUS_AN_1_READY 0x00000200 2268a264743SRob Clark #define HDMI_HDCP_LINK0_STATUS_RI_MATCHES 0x00001000 2278a264743SRob Clark #define HDMI_HDCP_LINK0_STATUS_V_MATCHES 0x00100000 2280cf6c71dSRob Clark #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK 0x70000000 2290cf6c71dSRob Clark #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT 28 2300cf6c71dSRob Clark static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val) 2310cf6c71dSRob Clark { 2320cf6c71dSRob Clark return ((val) << HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT) & HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK; 2330cf6c71dSRob Clark } 2340cf6c71dSRob Clark 2358a264743SRob Clark #define REG_HDMI_HDCP_DDC_CTRL_0 0x00000120 2368a264743SRob Clark #define HDMI_HDCP_DDC_CTRL_0_DISABLE 0x00000001 2378a264743SRob Clark 2388a264743SRob Clark #define REG_HDMI_HDCP_DDC_CTRL_1 0x00000124 2398a264743SRob Clark #define HDMI_HDCP_DDC_CTRL_1_FAILED_ACK 0x00000001 2408a264743SRob Clark 2418a264743SRob Clark #define REG_HDMI_HDCP_DDC_STATUS 0x00000128 2428a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_XFER_REQ 0x00000010 2438a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_XFER_DONE 0x00000400 2448a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_ABORTED 0x00001000 2458a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_TIMEOUT 0x00002000 2468a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_NACK0 0x00004000 2478a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_NACK1 0x00008000 2488a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_FAILED 0x00010000 2498a264743SRob Clark 2508a264743SRob Clark #define REG_HDMI_HDCP_ENTROPY_CTRL0 0x0000012c 2518a264743SRob Clark 2528a264743SRob Clark #define REG_HDMI_HDCP_ENTROPY_CTRL1 0x0000025c 2538a264743SRob Clark 2540cf6c71dSRob Clark #define REG_HDMI_HDCP_RESET 0x00000130 2550cf6c71dSRob Clark #define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE 0x00000001 2560cf6c71dSRob Clark 2578a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA0 0x00000134 2588a264743SRob Clark 2598a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA1 0x00000138 2608a264743SRob Clark 2618a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA2_0 0x0000013c 2628a264743SRob Clark 2638a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA2_1 0x00000140 2648a264743SRob Clark 2658a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA3 0x00000144 2668a264743SRob Clark 2678a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA4 0x00000148 2688a264743SRob Clark 2698a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA5 0x0000014c 2708a264743SRob Clark 2718a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA6 0x00000150 2728a264743SRob Clark 2738a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA7 0x00000154 2748a264743SRob Clark 2758a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA8 0x00000158 2768a264743SRob Clark 2778a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA9 0x0000015c 2788a264743SRob Clark 2798a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA10 0x00000160 2808a264743SRob Clark 2818a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA11 0x00000164 2828a264743SRob Clark 2838a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA12 0x00000168 2848a264743SRob Clark 285facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO0 0x0000016c 286facb4f4eSRob Clark 287facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO1 0x00000170 288facb4f4eSRob Clark 289facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO2 0x00000174 290facb4f4eSRob Clark 291facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO3 0x00000178 292facb4f4eSRob Clark 293facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO4 0x0000017c 294facb4f4eSRob Clark 295facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO5 0x00000180 296facb4f4eSRob Clark 297facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO6 0x00000184 298facb4f4eSRob Clark 2990cf6c71dSRob Clark #define REG_HDMI_AUDIO_CFG 0x000001d0 3000cf6c71dSRob Clark #define HDMI_AUDIO_CFG_ENGINE_ENABLE 0x00000001 3010cf6c71dSRob Clark #define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK 0x000000f0 3020cf6c71dSRob Clark #define HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT 4 3030cf6c71dSRob Clark static inline uint32_t HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val) 3040cf6c71dSRob Clark { 3050cf6c71dSRob Clark return ((val) << HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT) & HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK; 3060cf6c71dSRob Clark } 3070cf6c71dSRob Clark 3080cf6c71dSRob Clark #define REG_HDMI_USEC_REFTIMER 0x00000208 3090cf6c71dSRob Clark 3100cf6c71dSRob Clark #define REG_HDMI_DDC_CTRL 0x0000020c 3110cf6c71dSRob Clark #define HDMI_DDC_CTRL_GO 0x00000001 3120cf6c71dSRob Clark #define HDMI_DDC_CTRL_SOFT_RESET 0x00000002 3130cf6c71dSRob Clark #define HDMI_DDC_CTRL_SEND_RESET 0x00000004 3140cf6c71dSRob Clark #define HDMI_DDC_CTRL_SW_STATUS_RESET 0x00000008 3150cf6c71dSRob Clark #define HDMI_DDC_CTRL_TRANSACTION_CNT__MASK 0x00300000 3160cf6c71dSRob Clark #define HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT 20 3170cf6c71dSRob Clark static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val) 3180cf6c71dSRob Clark { 3190cf6c71dSRob Clark return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK; 3200cf6c71dSRob Clark } 3210cf6c71dSRob Clark 322facb4f4eSRob Clark #define REG_HDMI_DDC_ARBITRATION 0x00000210 323facb4f4eSRob Clark #define HDMI_DDC_ARBITRATION_HW_ARBITRATION 0x00000010 324facb4f4eSRob Clark 3250cf6c71dSRob Clark #define REG_HDMI_DDC_INT_CTRL 0x00000214 3260cf6c71dSRob Clark #define HDMI_DDC_INT_CTRL_SW_DONE_INT 0x00000001 3270cf6c71dSRob Clark #define HDMI_DDC_INT_CTRL_SW_DONE_ACK 0x00000002 3280cf6c71dSRob Clark #define HDMI_DDC_INT_CTRL_SW_DONE_MASK 0x00000004 3290cf6c71dSRob Clark 3300cf6c71dSRob Clark #define REG_HDMI_DDC_SW_STATUS 0x00000218 3310cf6c71dSRob Clark #define HDMI_DDC_SW_STATUS_NACK0 0x00001000 3320cf6c71dSRob Clark #define HDMI_DDC_SW_STATUS_NACK1 0x00002000 3330cf6c71dSRob Clark #define HDMI_DDC_SW_STATUS_NACK2 0x00004000 3340cf6c71dSRob Clark #define HDMI_DDC_SW_STATUS_NACK3 0x00008000 3350cf6c71dSRob Clark 3360cf6c71dSRob Clark #define REG_HDMI_DDC_HW_STATUS 0x0000021c 3378a264743SRob Clark #define HDMI_DDC_HW_STATUS_DONE 0x00000008 3380cf6c71dSRob Clark 3390cf6c71dSRob Clark #define REG_HDMI_DDC_SPEED 0x00000220 3400cf6c71dSRob Clark #define HDMI_DDC_SPEED_THRESHOLD__MASK 0x00000003 3410cf6c71dSRob Clark #define HDMI_DDC_SPEED_THRESHOLD__SHIFT 0 3420cf6c71dSRob Clark static inline uint32_t HDMI_DDC_SPEED_THRESHOLD(uint32_t val) 3430cf6c71dSRob Clark { 3440cf6c71dSRob Clark return ((val) << HDMI_DDC_SPEED_THRESHOLD__SHIFT) & HDMI_DDC_SPEED_THRESHOLD__MASK; 3450cf6c71dSRob Clark } 3460cf6c71dSRob Clark #define HDMI_DDC_SPEED_PRESCALE__MASK 0xffff0000 3470cf6c71dSRob Clark #define HDMI_DDC_SPEED_PRESCALE__SHIFT 16 3480cf6c71dSRob Clark static inline uint32_t HDMI_DDC_SPEED_PRESCALE(uint32_t val) 3490cf6c71dSRob Clark { 3500cf6c71dSRob Clark return ((val) << HDMI_DDC_SPEED_PRESCALE__SHIFT) & HDMI_DDC_SPEED_PRESCALE__MASK; 3510cf6c71dSRob Clark } 3520cf6c71dSRob Clark 3530cf6c71dSRob Clark #define REG_HDMI_DDC_SETUP 0x00000224 3540cf6c71dSRob Clark #define HDMI_DDC_SETUP_TIMEOUT__MASK 0xff000000 3550cf6c71dSRob Clark #define HDMI_DDC_SETUP_TIMEOUT__SHIFT 24 3560cf6c71dSRob Clark static inline uint32_t HDMI_DDC_SETUP_TIMEOUT(uint32_t val) 3570cf6c71dSRob Clark { 3580cf6c71dSRob Clark return ((val) << HDMI_DDC_SETUP_TIMEOUT__SHIFT) & HDMI_DDC_SETUP_TIMEOUT__MASK; 3590cf6c71dSRob Clark } 3600cf6c71dSRob Clark 3610cf6c71dSRob Clark static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; } 3620cf6c71dSRob Clark 3630cf6c71dSRob Clark static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; } 3640cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_RW__MASK 0x00000001 3650cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_RW__SHIFT 0 3660cf6c71dSRob Clark static inline uint32_t HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val) 3670cf6c71dSRob Clark { 3680cf6c71dSRob Clark return ((val) << HDMI_I2C_TRANSACTION_REG_RW__SHIFT) & HDMI_I2C_TRANSACTION_REG_RW__MASK; 3690cf6c71dSRob Clark } 3700cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_STOP_ON_NACK 0x00000100 3710cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_START 0x00001000 3720cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_STOP 0x00002000 3730cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_CNT__MASK 0x00ff0000 3740cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_CNT__SHIFT 16 3750cf6c71dSRob Clark static inline uint32_t HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val) 3760cf6c71dSRob Clark { 3770cf6c71dSRob Clark return ((val) << HDMI_I2C_TRANSACTION_REG_CNT__SHIFT) & HDMI_I2C_TRANSACTION_REG_CNT__MASK; 3780cf6c71dSRob Clark } 3790cf6c71dSRob Clark 3800cf6c71dSRob Clark #define REG_HDMI_DDC_DATA 0x00000238 3810cf6c71dSRob Clark #define HDMI_DDC_DATA_DATA_RW__MASK 0x00000001 3820cf6c71dSRob Clark #define HDMI_DDC_DATA_DATA_RW__SHIFT 0 3830cf6c71dSRob Clark static inline uint32_t HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val) 3840cf6c71dSRob Clark { 3850cf6c71dSRob Clark return ((val) << HDMI_DDC_DATA_DATA_RW__SHIFT) & HDMI_DDC_DATA_DATA_RW__MASK; 3860cf6c71dSRob Clark } 3870cf6c71dSRob Clark #define HDMI_DDC_DATA_DATA__MASK 0x0000ff00 3880cf6c71dSRob Clark #define HDMI_DDC_DATA_DATA__SHIFT 8 3890cf6c71dSRob Clark static inline uint32_t HDMI_DDC_DATA_DATA(uint32_t val) 3900cf6c71dSRob Clark { 3910cf6c71dSRob Clark return ((val) << HDMI_DDC_DATA_DATA__SHIFT) & HDMI_DDC_DATA_DATA__MASK; 3920cf6c71dSRob Clark } 3930cf6c71dSRob Clark #define HDMI_DDC_DATA_INDEX__MASK 0x00ff0000 3940cf6c71dSRob Clark #define HDMI_DDC_DATA_INDEX__SHIFT 16 3950cf6c71dSRob Clark static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val) 3960cf6c71dSRob Clark { 3970cf6c71dSRob Clark return ((val) << HDMI_DDC_DATA_INDEX__SHIFT) & HDMI_DDC_DATA_INDEX__MASK; 3980cf6c71dSRob Clark } 3990cf6c71dSRob Clark #define HDMI_DDC_DATA_INDEX_WRITE 0x80000000 4000cf6c71dSRob Clark 4018a264743SRob Clark #define REG_HDMI_HDCP_SHA_CTRL 0x0000023c 4028a264743SRob Clark 4038a264743SRob Clark #define REG_HDMI_HDCP_SHA_STATUS 0x00000240 4048a264743SRob Clark #define HDMI_HDCP_SHA_STATUS_BLOCK_DONE 0x00000001 4058a264743SRob Clark #define HDMI_HDCP_SHA_STATUS_COMP_DONE 0x00000010 4068a264743SRob Clark 4078a264743SRob Clark #define REG_HDMI_HDCP_SHA_DATA 0x00000244 4088a264743SRob Clark #define HDMI_HDCP_SHA_DATA_DONE 0x00000001 4098a264743SRob Clark 4100cf6c71dSRob Clark #define REG_HDMI_HPD_INT_STATUS 0x00000250 4110cf6c71dSRob Clark #define HDMI_HPD_INT_STATUS_INT 0x00000001 4120cf6c71dSRob Clark #define HDMI_HPD_INT_STATUS_CABLE_DETECTED 0x00000002 4130cf6c71dSRob Clark 4140cf6c71dSRob Clark #define REG_HDMI_HPD_INT_CTRL 0x00000254 4150cf6c71dSRob Clark #define HDMI_HPD_INT_CTRL_INT_ACK 0x00000001 4160cf6c71dSRob Clark #define HDMI_HPD_INT_CTRL_INT_CONNECT 0x00000002 4170cf6c71dSRob Clark #define HDMI_HPD_INT_CTRL_INT_EN 0x00000004 4180cf6c71dSRob Clark #define HDMI_HPD_INT_CTRL_RX_INT_ACK 0x00000010 4190cf6c71dSRob Clark #define HDMI_HPD_INT_CTRL_RX_INT_EN 0x00000020 4200cf6c71dSRob Clark #define HDMI_HPD_INT_CTRL_RCV_PLUGIN_DET_MASK 0x00000200 4210cf6c71dSRob Clark 4220cf6c71dSRob Clark #define REG_HDMI_HPD_CTRL 0x00000258 4230cf6c71dSRob Clark #define HDMI_HPD_CTRL_TIMEOUT__MASK 0x00001fff 4240cf6c71dSRob Clark #define HDMI_HPD_CTRL_TIMEOUT__SHIFT 0 4250cf6c71dSRob Clark static inline uint32_t HDMI_HPD_CTRL_TIMEOUT(uint32_t val) 4260cf6c71dSRob Clark { 4270cf6c71dSRob Clark return ((val) << HDMI_HPD_CTRL_TIMEOUT__SHIFT) & HDMI_HPD_CTRL_TIMEOUT__MASK; 4280cf6c71dSRob Clark } 4290cf6c71dSRob Clark #define HDMI_HPD_CTRL_ENABLE 0x10000000 4300cf6c71dSRob Clark 4310cf6c71dSRob Clark #define REG_HDMI_DDC_REF 0x0000027c 4320cf6c71dSRob Clark #define HDMI_DDC_REF_REFTIMER_ENABLE 0x00010000 4330cf6c71dSRob Clark #define HDMI_DDC_REF_REFTIMER__MASK 0x0000ffff 4340cf6c71dSRob Clark #define HDMI_DDC_REF_REFTIMER__SHIFT 0 4350cf6c71dSRob Clark static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val) 4360cf6c71dSRob Clark { 4370cf6c71dSRob Clark return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK; 4380cf6c71dSRob Clark } 4390cf6c71dSRob Clark 4408a264743SRob Clark #define REG_HDMI_HDCP_SW_UPPER_AKSV 0x00000284 4418a264743SRob Clark 4428a264743SRob Clark #define REG_HDMI_HDCP_SW_LOWER_AKSV 0x00000288 4438a264743SRob Clark 444facb4f4eSRob Clark #define REG_HDMI_CEC_STATUS 0x00000298 445facb4f4eSRob Clark 446facb4f4eSRob Clark #define REG_HDMI_CEC_INT 0x0000029c 447facb4f4eSRob Clark 448facb4f4eSRob Clark #define REG_HDMI_CEC_ADDR 0x000002a0 449facb4f4eSRob Clark 450facb4f4eSRob Clark #define REG_HDMI_CEC_TIME 0x000002a4 451facb4f4eSRob Clark 452facb4f4eSRob Clark #define REG_HDMI_CEC_REFTIMER 0x000002a8 453facb4f4eSRob Clark 454facb4f4eSRob Clark #define REG_HDMI_CEC_RD_DATA 0x000002ac 455facb4f4eSRob Clark 456facb4f4eSRob Clark #define REG_HDMI_CEC_RD_FILTER 0x000002b0 457facb4f4eSRob Clark 4580cf6c71dSRob Clark #define REG_HDMI_ACTIVE_HSYNC 0x000002b4 4590cf6c71dSRob Clark #define HDMI_ACTIVE_HSYNC_START__MASK 0x00000fff 4600cf6c71dSRob Clark #define HDMI_ACTIVE_HSYNC_START__SHIFT 0 4610cf6c71dSRob Clark static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val) 4620cf6c71dSRob Clark { 4630cf6c71dSRob Clark return ((val) << HDMI_ACTIVE_HSYNC_START__SHIFT) & HDMI_ACTIVE_HSYNC_START__MASK; 4640cf6c71dSRob Clark } 4650cf6c71dSRob Clark #define HDMI_ACTIVE_HSYNC_END__MASK 0x0fff0000 4660cf6c71dSRob Clark #define HDMI_ACTIVE_HSYNC_END__SHIFT 16 4670cf6c71dSRob Clark static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val) 4680cf6c71dSRob Clark { 4690cf6c71dSRob Clark return ((val) << HDMI_ACTIVE_HSYNC_END__SHIFT) & HDMI_ACTIVE_HSYNC_END__MASK; 4700cf6c71dSRob Clark } 4710cf6c71dSRob Clark 4720cf6c71dSRob Clark #define REG_HDMI_ACTIVE_VSYNC 0x000002b8 4730cf6c71dSRob Clark #define HDMI_ACTIVE_VSYNC_START__MASK 0x00000fff 4740cf6c71dSRob Clark #define HDMI_ACTIVE_VSYNC_START__SHIFT 0 4750cf6c71dSRob Clark static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val) 4760cf6c71dSRob Clark { 4770cf6c71dSRob Clark return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK; 4780cf6c71dSRob Clark } 4790cf6c71dSRob Clark #define HDMI_ACTIVE_VSYNC_END__MASK 0x0fff0000 4800cf6c71dSRob Clark #define HDMI_ACTIVE_VSYNC_END__SHIFT 16 4810cf6c71dSRob Clark static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val) 4820cf6c71dSRob Clark { 4830cf6c71dSRob Clark return ((val) << HDMI_ACTIVE_VSYNC_END__SHIFT) & HDMI_ACTIVE_VSYNC_END__MASK; 4840cf6c71dSRob Clark } 4850cf6c71dSRob Clark 4860cf6c71dSRob Clark #define REG_HDMI_VSYNC_ACTIVE_F2 0x000002bc 4870cf6c71dSRob Clark #define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00000fff 4880cf6c71dSRob Clark #define HDMI_VSYNC_ACTIVE_F2_START__SHIFT 0 4890cf6c71dSRob Clark static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val) 4900cf6c71dSRob Clark { 4910cf6c71dSRob Clark return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK; 4920cf6c71dSRob Clark } 4930cf6c71dSRob Clark #define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x0fff0000 4940cf6c71dSRob Clark #define HDMI_VSYNC_ACTIVE_F2_END__SHIFT 16 4950cf6c71dSRob Clark static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val) 4960cf6c71dSRob Clark { 4970cf6c71dSRob Clark return ((val) << HDMI_VSYNC_ACTIVE_F2_END__SHIFT) & HDMI_VSYNC_ACTIVE_F2_END__MASK; 4980cf6c71dSRob Clark } 4990cf6c71dSRob Clark 5000cf6c71dSRob Clark #define REG_HDMI_TOTAL 0x000002c0 5010cf6c71dSRob Clark #define HDMI_TOTAL_H_TOTAL__MASK 0x00000fff 5020cf6c71dSRob Clark #define HDMI_TOTAL_H_TOTAL__SHIFT 0 5030cf6c71dSRob Clark static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val) 5040cf6c71dSRob Clark { 5050cf6c71dSRob Clark return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK; 5060cf6c71dSRob Clark } 5070cf6c71dSRob Clark #define HDMI_TOTAL_V_TOTAL__MASK 0x0fff0000 5080cf6c71dSRob Clark #define HDMI_TOTAL_V_TOTAL__SHIFT 16 5090cf6c71dSRob Clark static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val) 5100cf6c71dSRob Clark { 5110cf6c71dSRob Clark return ((val) << HDMI_TOTAL_V_TOTAL__SHIFT) & HDMI_TOTAL_V_TOTAL__MASK; 5120cf6c71dSRob Clark } 5130cf6c71dSRob Clark 5140cf6c71dSRob Clark #define REG_HDMI_VSYNC_TOTAL_F2 0x000002c4 5150cf6c71dSRob Clark #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00000fff 5160cf6c71dSRob Clark #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT 0 5170cf6c71dSRob Clark static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val) 5180cf6c71dSRob Clark { 5190cf6c71dSRob Clark return ((val) << HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT) & HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK; 5200cf6c71dSRob Clark } 5210cf6c71dSRob Clark 5220cf6c71dSRob Clark #define REG_HDMI_FRAME_CTRL 0x000002c8 5230cf6c71dSRob Clark #define HDMI_FRAME_CTRL_RGB_MUX_SEL_BGR 0x00001000 5240cf6c71dSRob Clark #define HDMI_FRAME_CTRL_VSYNC_LOW 0x10000000 5250cf6c71dSRob Clark #define HDMI_FRAME_CTRL_HSYNC_LOW 0x20000000 5260cf6c71dSRob Clark #define HDMI_FRAME_CTRL_INTERLACED_EN 0x80000000 5270cf6c71dSRob Clark 528facb4f4eSRob Clark #define REG_HDMI_AUD_INT 0x000002cc 529facb4f4eSRob Clark #define HDMI_AUD_INT_AUD_FIFO_URUN_INT 0x00000001 530facb4f4eSRob Clark #define HDMI_AUD_INT_AUD_FIFO_URAN_MASK 0x00000002 531facb4f4eSRob Clark #define HDMI_AUD_INT_AUD_SAM_DROP_INT 0x00000004 532facb4f4eSRob Clark #define HDMI_AUD_INT_AUD_SAM_DROP_MASK 0x00000008 533facb4f4eSRob Clark 5340cf6c71dSRob Clark #define REG_HDMI_PHY_CTRL 0x000002d4 5350cf6c71dSRob Clark #define HDMI_PHY_CTRL_SW_RESET_PLL 0x00000001 5360cf6c71dSRob Clark #define HDMI_PHY_CTRL_SW_RESET_PLL_LOW 0x00000002 5370cf6c71dSRob Clark #define HDMI_PHY_CTRL_SW_RESET 0x00000004 5380cf6c71dSRob Clark #define HDMI_PHY_CTRL_SW_RESET_LOW 0x00000008 5390cf6c71dSRob Clark 540facb4f4eSRob Clark #define REG_HDMI_CEC_WR_RANGE 0x000002dc 541facb4f4eSRob Clark 542facb4f4eSRob Clark #define REG_HDMI_CEC_RD_RANGE 0x000002e0 543facb4f4eSRob Clark 544facb4f4eSRob Clark #define REG_HDMI_VERSION 0x000002e4 545facb4f4eSRob Clark 546facb4f4eSRob Clark #define REG_HDMI_CEC_COMPL_CTL 0x00000360 547facb4f4eSRob Clark 548facb4f4eSRob Clark #define REG_HDMI_CEC_RD_START_RANGE 0x00000364 549facb4f4eSRob Clark 550facb4f4eSRob Clark #define REG_HDMI_CEC_RD_TOTAL_RANGE 0x00000368 551facb4f4eSRob Clark 552facb4f4eSRob Clark #define REG_HDMI_CEC_RD_ERR_RESP_LO 0x0000036c 553facb4f4eSRob Clark 554facb4f4eSRob Clark #define REG_HDMI_CEC_WR_CHECK_CONFIG 0x00000370 5550cf6c71dSRob Clark 5560cf6c71dSRob Clark #define REG_HDMI_8x60_PHY_REG0 0x00000300 5570cf6c71dSRob Clark #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c 5580cf6c71dSRob Clark #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT 2 5590cf6c71dSRob Clark static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val) 5600cf6c71dSRob Clark { 5610cf6c71dSRob Clark return ((val) << HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT) & HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK; 5620cf6c71dSRob Clark } 5630cf6c71dSRob Clark 5640cf6c71dSRob Clark #define REG_HDMI_8x60_PHY_REG1 0x00000304 5650cf6c71dSRob Clark #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK 0x000000f0 5660cf6c71dSRob Clark #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT 4 5670cf6c71dSRob Clark static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val) 5680cf6c71dSRob Clark { 5690cf6c71dSRob Clark return ((val) << HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT) & HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK; 5700cf6c71dSRob Clark } 5710cf6c71dSRob Clark #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK 0x0000000f 5720cf6c71dSRob Clark #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT 0 5730cf6c71dSRob Clark static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val) 5740cf6c71dSRob Clark { 5750cf6c71dSRob Clark return ((val) << HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT) & HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK; 5760cf6c71dSRob Clark } 5770cf6c71dSRob Clark 5780cf6c71dSRob Clark #define REG_HDMI_8x60_PHY_REG2 0x00000308 5790cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_DESER 0x00000001 5800cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_DRIVE_1 0x00000002 5810cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_DRIVE_2 0x00000004 5820cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_DRIVE_3 0x00000008 5830cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_DRIVE_4 0x00000010 5840cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_PLL 0x00000020 5850cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_PWRGEN 0x00000040 5860cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_RCV_SENSE_EN 0x00000080 5870cf6c71dSRob Clark 5880cf6c71dSRob Clark #define REG_HDMI_8x60_PHY_REG3 0x0000030c 5890cf6c71dSRob Clark #define HDMI_8x60_PHY_REG3_PLL_ENABLE 0x00000001 5900cf6c71dSRob Clark 5910cf6c71dSRob Clark #define REG_HDMI_8x60_PHY_REG4 0x00000310 5920cf6c71dSRob Clark 5930cf6c71dSRob Clark #define REG_HDMI_8x60_PHY_REG5 0x00000314 5940cf6c71dSRob Clark 5950cf6c71dSRob Clark #define REG_HDMI_8x60_PHY_REG6 0x00000318 5960cf6c71dSRob Clark 5970cf6c71dSRob Clark #define REG_HDMI_8x60_PHY_REG7 0x0000031c 5980cf6c71dSRob Clark 5990cf6c71dSRob Clark #define REG_HDMI_8x60_PHY_REG8 0x00000320 6000cf6c71dSRob Clark 6010cf6c71dSRob Clark #define REG_HDMI_8x60_PHY_REG9 0x00000324 6020cf6c71dSRob Clark 6030cf6c71dSRob Clark #define REG_HDMI_8x60_PHY_REG10 0x00000328 6040cf6c71dSRob Clark 6050cf6c71dSRob Clark #define REG_HDMI_8x60_PHY_REG11 0x0000032c 6060cf6c71dSRob Clark 6070cf6c71dSRob Clark #define REG_HDMI_8x60_PHY_REG12 0x00000330 6080cf6c71dSRob Clark #define HDMI_8x60_PHY_REG12_RETIMING_EN 0x00000001 6090cf6c71dSRob Clark #define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN 0x00000002 6100cf6c71dSRob Clark #define HDMI_8x60_PHY_REG12_FORCE_LOCK 0x00000010 6110cf6c71dSRob Clark 6120cf6c71dSRob Clark #define REG_HDMI_8960_PHY_REG0 0x00000400 6130cf6c71dSRob Clark 6140cf6c71dSRob Clark #define REG_HDMI_8960_PHY_REG1 0x00000404 6150cf6c71dSRob Clark 6160cf6c71dSRob Clark #define REG_HDMI_8960_PHY_REG2 0x00000408 6170cf6c71dSRob Clark 6180cf6c71dSRob Clark #define REG_HDMI_8960_PHY_REG3 0x0000040c 6190cf6c71dSRob Clark 6200cf6c71dSRob Clark #define REG_HDMI_8960_PHY_REG4 0x00000410 6210cf6c71dSRob Clark 6220cf6c71dSRob Clark #define REG_HDMI_8960_PHY_REG5 0x00000414 6230cf6c71dSRob Clark 6240cf6c71dSRob Clark #define REG_HDMI_8960_PHY_REG6 0x00000418 6250cf6c71dSRob Clark 6260cf6c71dSRob Clark #define REG_HDMI_8960_PHY_REG7 0x0000041c 6270cf6c71dSRob Clark 6280cf6c71dSRob Clark #define REG_HDMI_8960_PHY_REG8 0x00000420 6290cf6c71dSRob Clark 6300cf6c71dSRob Clark #define REG_HDMI_8960_PHY_REG9 0x00000424 6310cf6c71dSRob Clark 6320cf6c71dSRob Clark #define REG_HDMI_8960_PHY_REG10 0x00000428 6330cf6c71dSRob Clark 6340cf6c71dSRob Clark #define REG_HDMI_8960_PHY_REG11 0x0000042c 6350cf6c71dSRob Clark 6360cf6c71dSRob Clark #define REG_HDMI_8960_PHY_REG12 0x00000430 63789301471SRob Clark #define HDMI_8960_PHY_REG12_SW_RESET 0x00000020 63889301471SRob Clark #define HDMI_8960_PHY_REG12_PWRDN_B 0x00000080 63989301471SRob Clark 64089301471SRob Clark #define REG_HDMI_8960_PHY_REG_BIST_CFG 0x00000434 64189301471SRob Clark 64289301471SRob Clark #define REG_HDMI_8960_PHY_DEBUG_BUS_SEL 0x00000438 64389301471SRob Clark 64489301471SRob Clark #define REG_HDMI_8960_PHY_REG_MISC0 0x0000043c 64589301471SRob Clark 64689301471SRob Clark #define REG_HDMI_8960_PHY_REG13 0x00000440 64789301471SRob Clark 64889301471SRob Clark #define REG_HDMI_8960_PHY_REG14 0x00000444 64989301471SRob Clark 65089301471SRob Clark #define REG_HDMI_8960_PHY_REG15 0x00000448 65189301471SRob Clark 65289301471SRob Clark #define REG_HDMI_8960_PHY_PLL_REFCLK_CFG 0x00000500 65389301471SRob Clark 65489301471SRob Clark #define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG 0x00000504 65589301471SRob Clark 65689301471SRob Clark #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 0x00000508 65789301471SRob Clark 65889301471SRob Clark #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 0x0000050c 65989301471SRob Clark 66089301471SRob Clark #define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG 0x00000510 66189301471SRob Clark 66289301471SRob Clark #define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG 0x00000514 66389301471SRob Clark 66489301471SRob Clark #define REG_HDMI_8960_PHY_PLL_PWRDN_B 0x00000518 66589301471SRob Clark #define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL 0x00000002 66689301471SRob Clark #define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B 0x00000008 66789301471SRob Clark 66889301471SRob Clark #define REG_HDMI_8960_PHY_PLL_SDM_CFG0 0x0000051c 66989301471SRob Clark 67089301471SRob Clark #define REG_HDMI_8960_PHY_PLL_SDM_CFG1 0x00000520 67189301471SRob Clark 67289301471SRob Clark #define REG_HDMI_8960_PHY_PLL_SDM_CFG2 0x00000524 67389301471SRob Clark 67489301471SRob Clark #define REG_HDMI_8960_PHY_PLL_SDM_CFG3 0x00000528 67589301471SRob Clark 67689301471SRob Clark #define REG_HDMI_8960_PHY_PLL_SDM_CFG4 0x0000052c 67789301471SRob Clark 67889301471SRob Clark #define REG_HDMI_8960_PHY_PLL_SSC_CFG0 0x00000530 67989301471SRob Clark 68089301471SRob Clark #define REG_HDMI_8960_PHY_PLL_SSC_CFG1 0x00000534 68189301471SRob Clark 68289301471SRob Clark #define REG_HDMI_8960_PHY_PLL_SSC_CFG2 0x00000538 68389301471SRob Clark 68489301471SRob Clark #define REG_HDMI_8960_PHY_PLL_SSC_CFG3 0x0000053c 68589301471SRob Clark 68689301471SRob Clark #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 0x00000540 68789301471SRob Clark 68889301471SRob Clark #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 0x00000544 68989301471SRob Clark 69089301471SRob Clark #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 0x00000548 69189301471SRob Clark 69289301471SRob Clark #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 0x0000054c 69389301471SRob Clark 69489301471SRob Clark #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 0x00000550 69589301471SRob Clark 69689301471SRob Clark #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 0x00000554 69789301471SRob Clark 69889301471SRob Clark #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 0x00000558 69989301471SRob Clark 70089301471SRob Clark #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 0x0000055c 70189301471SRob Clark 70289301471SRob Clark #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 0x00000560 70389301471SRob Clark 70489301471SRob Clark #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 0x00000564 70589301471SRob Clark 70689301471SRob Clark #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 0x00000568 70789301471SRob Clark 70889301471SRob Clark #define REG_HDMI_8960_PHY_PLL_DEBUG_SEL 0x0000056c 70989301471SRob Clark 71089301471SRob Clark #define REG_HDMI_8960_PHY_PLL_MISC0 0x00000570 71189301471SRob Clark 71289301471SRob Clark #define REG_HDMI_8960_PHY_PLL_MISC1 0x00000574 71389301471SRob Clark 71489301471SRob Clark #define REG_HDMI_8960_PHY_PLL_MISC2 0x00000578 71589301471SRob Clark 71689301471SRob Clark #define REG_HDMI_8960_PHY_PLL_MISC3 0x0000057c 71789301471SRob Clark 71889301471SRob Clark #define REG_HDMI_8960_PHY_PLL_MISC4 0x00000580 71989301471SRob Clark 72089301471SRob Clark #define REG_HDMI_8960_PHY_PLL_MISC5 0x00000584 72189301471SRob Clark 72289301471SRob Clark #define REG_HDMI_8960_PHY_PLL_MISC6 0x00000588 72389301471SRob Clark 72489301471SRob Clark #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0 0x0000058c 72589301471SRob Clark 72689301471SRob Clark #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1 0x00000590 72789301471SRob Clark 72889301471SRob Clark #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2 0x00000594 72989301471SRob Clark 73089301471SRob Clark #define REG_HDMI_8960_PHY_PLL_STATUS0 0x00000598 73189301471SRob Clark #define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK 0x00000001 73289301471SRob Clark 73389301471SRob Clark #define REG_HDMI_8960_PHY_PLL_STATUS1 0x0000059c 7340cf6c71dSRob Clark 735facb4f4eSRob Clark #define REG_HDMI_8x74_ANA_CFG0 0x00000000 736facb4f4eSRob Clark 737facb4f4eSRob Clark #define REG_HDMI_8x74_ANA_CFG1 0x00000004 738facb4f4eSRob Clark 739facb4f4eSRob Clark #define REG_HDMI_8x74_PD_CTRL0 0x00000010 740facb4f4eSRob Clark 741facb4f4eSRob Clark #define REG_HDMI_8x74_PD_CTRL1 0x00000014 742facb4f4eSRob Clark 743facb4f4eSRob Clark #define REG_HDMI_8x74_BIST_CFG0 0x00000034 744facb4f4eSRob Clark 745facb4f4eSRob Clark #define REG_HDMI_8x74_BIST_PATN0 0x0000003c 746facb4f4eSRob Clark 747facb4f4eSRob Clark #define REG_HDMI_8x74_BIST_PATN1 0x00000040 748facb4f4eSRob Clark 749facb4f4eSRob Clark #define REG_HDMI_8x74_BIST_PATN2 0x00000044 750facb4f4eSRob Clark 751facb4f4eSRob Clark #define REG_HDMI_8x74_BIST_PATN3 0x00000048 752facb4f4eSRob Clark 753af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_REFCLK_CFG 0x00000000 754af6cb4c1SRob Clark 755af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004 756af6cb4c1SRob Clark 757af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008 758af6cb4c1SRob Clark 759af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c 760af6cb4c1SRob Clark 761af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_VREG_CFG 0x00000010 762af6cb4c1SRob Clark 763af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014 764af6cb4c1SRob Clark 765af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_DMUX_CFG 0x00000018 766af6cb4c1SRob Clark 767af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_AMUX_CFG 0x0000001c 768af6cb4c1SRob Clark 769af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_GLB_CFG 0x00000020 770af6cb4c1SRob Clark #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001 771af6cb4c1SRob Clark #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002 772af6cb4c1SRob Clark #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004 773af6cb4c1SRob Clark #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008 774af6cb4c1SRob Clark 775af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024 776af6cb4c1SRob Clark 777af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028 778af6cb4c1SRob Clark 779af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_LPFR_CFG 0x0000002c 780af6cb4c1SRob Clark 781af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_LPFC1_CFG 0x00000030 782af6cb4c1SRob Clark 783af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_LPFC2_CFG 0x00000034 784af6cb4c1SRob Clark 785af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SDM_CFG0 0x00000038 786af6cb4c1SRob Clark 787af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SDM_CFG1 0x0000003c 788af6cb4c1SRob Clark 789af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SDM_CFG2 0x00000040 790af6cb4c1SRob Clark 791af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SDM_CFG3 0x00000044 792af6cb4c1SRob Clark 793af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SDM_CFG4 0x00000048 794af6cb4c1SRob Clark 795af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SSC_CFG0 0x0000004c 796af6cb4c1SRob Clark 797af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SSC_CFG1 0x00000050 798af6cb4c1SRob Clark 799af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SSC_CFG2 0x00000054 800af6cb4c1SRob Clark 801af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SSC_CFG3 0x00000058 802af6cb4c1SRob Clark 803af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c 804af6cb4c1SRob Clark 805af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG1 0x00000060 806af6cb4c1SRob Clark 807af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG2 0x00000064 808af6cb4c1SRob Clark 809af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_TEST_CFG 0x00000068 810af6cb4c1SRob Clark #define HDMI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001 811af6cb4c1SRob Clark 812af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG0 0x0000006c 813af6cb4c1SRob Clark 814af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG1 0x00000070 815af6cb4c1SRob Clark 816af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG2 0x00000074 817af6cb4c1SRob Clark 818af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG3 0x00000078 819af6cb4c1SRob Clark 820af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG4 0x0000007c 821af6cb4c1SRob Clark 822af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG5 0x00000080 823af6cb4c1SRob Clark 824af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG6 0x00000084 825af6cb4c1SRob Clark 826af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG7 0x00000088 827af6cb4c1SRob Clark 828af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG8 0x0000008c 829af6cb4c1SRob Clark 830af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG9 0x00000090 831af6cb4c1SRob Clark 832af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG10 0x00000094 833af6cb4c1SRob Clark 834af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG11 0x00000098 835af6cb4c1SRob Clark 836af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c 837af6cb4c1SRob Clark 838af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0 839af6cb4c1SRob Clark 8400cf6c71dSRob Clark 8410cf6c71dSRob Clark #endif /* HDMI_XML */ 842