10cf6c71dSRob Clark #ifndef HDMI_XML 20cf6c71dSRob Clark #define HDMI_XML 30cf6c71dSRob Clark 40cf6c71dSRob Clark /* Autogenerated file, DO NOT EDIT manually! 50cf6c71dSRob Clark 60cf6c71dSRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 722ba8b6bSRob Clark http://github.com/freedreno/envytools/ 822ba8b6bSRob Clark git clone https://github.com/freedreno/envytools.git 90cf6c71dSRob Clark 100cf6c71dSRob Clark The rules-ng-ng source files this header was generated from are: 1152260ae4SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27) 1252260ae4SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27) 1352260ae4SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27) 1452260ae4SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27) 1552260ae4SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27) 1652260ae4SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27) 1752260ae4SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27) 1852260ae4SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27) 1952260ae4SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27) 2052260ae4SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42) 2152260ae4SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27) 220cf6c71dSRob Clark 2352260ae4SRob Clark Copyright (C) 2013-2017 by the following authors: 240cf6c71dSRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 25a2272e48SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 260cf6c71dSRob Clark 270cf6c71dSRob Clark Permission is hereby granted, free of charge, to any person obtaining 280cf6c71dSRob Clark a copy of this software and associated documentation files (the 290cf6c71dSRob Clark "Software"), to deal in the Software without restriction, including 300cf6c71dSRob Clark without limitation the rights to use, copy, modify, merge, publish, 310cf6c71dSRob Clark distribute, sublicense, and/or sell copies of the Software, and to 320cf6c71dSRob Clark permit persons to whom the Software is furnished to do so, subject to 330cf6c71dSRob Clark the following conditions: 340cf6c71dSRob Clark 350cf6c71dSRob Clark The above copyright notice and this permission notice (including the 360cf6c71dSRob Clark next paragraph) shall be included in all copies or substantial 370cf6c71dSRob Clark portions of the Software. 380cf6c71dSRob Clark 390cf6c71dSRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 400cf6c71dSRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 410cf6c71dSRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 420cf6c71dSRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 430cf6c71dSRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 440cf6c71dSRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 450cf6c71dSRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 460cf6c71dSRob Clark */ 470cf6c71dSRob Clark 480cf6c71dSRob Clark 490cf6c71dSRob Clark enum hdmi_hdcp_key_state { 508a264743SRob Clark HDCP_KEYS_STATE_NO_KEYS = 0, 518a264743SRob Clark HDCP_KEYS_STATE_NOT_CHECKED = 1, 528a264743SRob Clark HDCP_KEYS_STATE_CHECKING = 2, 538a264743SRob Clark HDCP_KEYS_STATE_VALID = 3, 548a264743SRob Clark HDCP_KEYS_STATE_AKSV_NOT_VALID = 4, 558a264743SRob Clark HDCP_KEYS_STATE_CHKSUM_MISMATCH = 5, 568a264743SRob Clark HDCP_KEYS_STATE_PROD_AKSV = 6, 578a264743SRob Clark HDCP_KEYS_STATE_RESERVED = 7, 580cf6c71dSRob Clark }; 590cf6c71dSRob Clark 600cf6c71dSRob Clark enum hdmi_ddc_read_write { 610cf6c71dSRob Clark DDC_WRITE = 0, 620cf6c71dSRob Clark DDC_READ = 1, 630cf6c71dSRob Clark }; 640cf6c71dSRob Clark 650cf6c71dSRob Clark enum hdmi_acr_cts { 660cf6c71dSRob Clark ACR_NONE = 0, 670cf6c71dSRob Clark ACR_32 = 1, 680cf6c71dSRob Clark ACR_44 = 2, 690cf6c71dSRob Clark ACR_48 = 3, 700cf6c71dSRob Clark }; 710cf6c71dSRob Clark 720cf6c71dSRob Clark #define REG_HDMI_CTRL 0x00000000 730cf6c71dSRob Clark #define HDMI_CTRL_ENABLE 0x00000001 740cf6c71dSRob Clark #define HDMI_CTRL_HDMI 0x00000002 750cf6c71dSRob Clark #define HDMI_CTRL_ENCRYPTED 0x00000004 760cf6c71dSRob Clark 770cf6c71dSRob Clark #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020 780cf6c71dSRob Clark #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001 790cf6c71dSRob Clark 800cf6c71dSRob Clark #define REG_HDMI_ACR_PKT_CTRL 0x00000024 810cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_CONT 0x00000001 820cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_SEND 0x00000002 830cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_SELECT__MASK 0x00000030 840cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_SELECT__SHIFT 4 850cf6c71dSRob Clark static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val) 860cf6c71dSRob Clark { 870cf6c71dSRob Clark return ((val) << HDMI_ACR_PKT_CTRL_SELECT__SHIFT) & HDMI_ACR_PKT_CTRL_SELECT__MASK; 880cf6c71dSRob Clark } 890cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_SOURCE 0x00000100 900cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK 0x00070000 910cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT 16 920cf6c71dSRob Clark static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val) 930cf6c71dSRob Clark { 940cf6c71dSRob Clark return ((val) << HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT) & HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK; 950cf6c71dSRob Clark } 960cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY 0x80000000 970cf6c71dSRob Clark 980cf6c71dSRob Clark #define REG_HDMI_VBI_PKT_CTRL 0x00000028 990cf6c71dSRob Clark #define HDMI_VBI_PKT_CTRL_GC_ENABLE 0x00000010 1000cf6c71dSRob Clark #define HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME 0x00000020 1010cf6c71dSRob Clark #define HDMI_VBI_PKT_CTRL_ISRC_SEND 0x00000100 1020cf6c71dSRob Clark #define HDMI_VBI_PKT_CTRL_ISRC_CONTINUOUS 0x00000200 1030cf6c71dSRob Clark #define HDMI_VBI_PKT_CTRL_ACP_SEND 0x00001000 1040cf6c71dSRob Clark #define HDMI_VBI_PKT_CTRL_ACP_SRC_SW 0x00002000 1050cf6c71dSRob Clark 1060cf6c71dSRob Clark #define REG_HDMI_INFOFRAME_CTRL0 0x0000002c 1070cf6c71dSRob Clark #define HDMI_INFOFRAME_CTRL0_AVI_SEND 0x00000001 1080cf6c71dSRob Clark #define HDMI_INFOFRAME_CTRL0_AVI_CONT 0x00000002 1090cf6c71dSRob Clark #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND 0x00000010 1100cf6c71dSRob Clark #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT 0x00000020 1110cf6c71dSRob Clark #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE 0x00000040 1120cf6c71dSRob Clark #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE 0x00000080 1130cf6c71dSRob Clark 11452260ae4SRob Clark #define REG_HDMI_INFOFRAME_CTRL1 0x00000030 11552260ae4SRob Clark #define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK 0x0000003f 11652260ae4SRob Clark #define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT 0 11752260ae4SRob Clark static inline uint32_t HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(uint32_t val) 11852260ae4SRob Clark { 11952260ae4SRob Clark return ((val) << HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK; 12052260ae4SRob Clark } 12152260ae4SRob Clark #define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK 0x00003f00 12252260ae4SRob Clark #define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT 8 12352260ae4SRob Clark static inline uint32_t HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE(uint32_t val) 12452260ae4SRob Clark { 12552260ae4SRob Clark return ((val) << HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK; 12652260ae4SRob Clark } 12752260ae4SRob Clark #define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK 0x003f0000 12852260ae4SRob Clark #define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT 16 12952260ae4SRob Clark static inline uint32_t HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE(uint32_t val) 13052260ae4SRob Clark { 13152260ae4SRob Clark return ((val) << HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK; 13252260ae4SRob Clark } 13352260ae4SRob Clark #define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK 0x3f000000 13452260ae4SRob Clark #define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT 24 13552260ae4SRob Clark static inline uint32_t HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE(uint32_t val) 13652260ae4SRob Clark { 13752260ae4SRob Clark return ((val) << HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK; 13852260ae4SRob Clark } 13952260ae4SRob Clark 1400cf6c71dSRob Clark #define REG_HDMI_GEN_PKT_CTRL 0x00000034 1410cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC0_SEND 0x00000001 1420cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC0_CONT 0x00000002 1430cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK 0x0000000c 1440cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT 2 1450cf6c71dSRob Clark static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val) 1460cf6c71dSRob Clark { 1470cf6c71dSRob Clark return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK; 1480cf6c71dSRob Clark } 1490cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC1_SEND 0x00000010 1500cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC1_CONT 0x00000020 1510cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK 0x003f0000 1520cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT 16 1530cf6c71dSRob Clark static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val) 1540cf6c71dSRob Clark { 1550cf6c71dSRob Clark return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK; 1560cf6c71dSRob Clark } 1570cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK 0x3f000000 1580cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT 24 1590cf6c71dSRob Clark static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val) 1600cf6c71dSRob Clark { 1610cf6c71dSRob Clark return ((val) << HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK; 1620cf6c71dSRob Clark } 1630cf6c71dSRob Clark 1640cf6c71dSRob Clark #define REG_HDMI_GC 0x00000040 1650cf6c71dSRob Clark #define HDMI_GC_MUTE 0x00000001 1660cf6c71dSRob Clark 1670cf6c71dSRob Clark #define REG_HDMI_AUDIO_PKT_CTRL2 0x00000044 1680cf6c71dSRob Clark #define HDMI_AUDIO_PKT_CTRL2_OVERRIDE 0x00000001 1690cf6c71dSRob Clark #define HDMI_AUDIO_PKT_CTRL2_LAYOUT 0x00000002 1700cf6c71dSRob Clark 1710cf6c71dSRob Clark static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; } 1720cf6c71dSRob Clark 1730cf6c71dSRob Clark #define REG_HDMI_GENERIC0_HDR 0x00000084 1740cf6c71dSRob Clark 1750cf6c71dSRob Clark static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; } 1760cf6c71dSRob Clark 1770cf6c71dSRob Clark #define REG_HDMI_GENERIC1_HDR 0x000000a4 1780cf6c71dSRob Clark 1790cf6c71dSRob Clark static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; } 1800cf6c71dSRob Clark 18189301471SRob Clark static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } 1820cf6c71dSRob Clark 18389301471SRob Clark static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } 1840cf6c71dSRob Clark #define HDMI_ACR_0_CTS__MASK 0xfffff000 1850cf6c71dSRob Clark #define HDMI_ACR_0_CTS__SHIFT 12 1860cf6c71dSRob Clark static inline uint32_t HDMI_ACR_0_CTS(uint32_t val) 1870cf6c71dSRob Clark { 1880cf6c71dSRob Clark return ((val) << HDMI_ACR_0_CTS__SHIFT) & HDMI_ACR_0_CTS__MASK; 1890cf6c71dSRob Clark } 1900cf6c71dSRob Clark 19189301471SRob Clark static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; } 1920cf6c71dSRob Clark #define HDMI_ACR_1_N__MASK 0xffffffff 1930cf6c71dSRob Clark #define HDMI_ACR_1_N__SHIFT 0 1940cf6c71dSRob Clark static inline uint32_t HDMI_ACR_1_N(uint32_t val) 1950cf6c71dSRob Clark { 1960cf6c71dSRob Clark return ((val) << HDMI_ACR_1_N__SHIFT) & HDMI_ACR_1_N__MASK; 1970cf6c71dSRob Clark } 1980cf6c71dSRob Clark 1990cf6c71dSRob Clark #define REG_HDMI_AUDIO_INFO0 0x000000e4 2000cf6c71dSRob Clark #define HDMI_AUDIO_INFO0_CHECKSUM__MASK 0x000000ff 2010cf6c71dSRob Clark #define HDMI_AUDIO_INFO0_CHECKSUM__SHIFT 0 2020cf6c71dSRob Clark static inline uint32_t HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val) 2030cf6c71dSRob Clark { 2040cf6c71dSRob Clark return ((val) << HDMI_AUDIO_INFO0_CHECKSUM__SHIFT) & HDMI_AUDIO_INFO0_CHECKSUM__MASK; 2050cf6c71dSRob Clark } 2060cf6c71dSRob Clark #define HDMI_AUDIO_INFO0_CC__MASK 0x00000700 2070cf6c71dSRob Clark #define HDMI_AUDIO_INFO0_CC__SHIFT 8 2080cf6c71dSRob Clark static inline uint32_t HDMI_AUDIO_INFO0_CC(uint32_t val) 2090cf6c71dSRob Clark { 2100cf6c71dSRob Clark return ((val) << HDMI_AUDIO_INFO0_CC__SHIFT) & HDMI_AUDIO_INFO0_CC__MASK; 2110cf6c71dSRob Clark } 2120cf6c71dSRob Clark 2130cf6c71dSRob Clark #define REG_HDMI_AUDIO_INFO1 0x000000e8 2140cf6c71dSRob Clark #define HDMI_AUDIO_INFO1_CA__MASK 0x000000ff 2150cf6c71dSRob Clark #define HDMI_AUDIO_INFO1_CA__SHIFT 0 2160cf6c71dSRob Clark static inline uint32_t HDMI_AUDIO_INFO1_CA(uint32_t val) 2170cf6c71dSRob Clark { 2180cf6c71dSRob Clark return ((val) << HDMI_AUDIO_INFO1_CA__SHIFT) & HDMI_AUDIO_INFO1_CA__MASK; 2190cf6c71dSRob Clark } 2200cf6c71dSRob Clark #define HDMI_AUDIO_INFO1_LSV__MASK 0x00007800 2210cf6c71dSRob Clark #define HDMI_AUDIO_INFO1_LSV__SHIFT 11 2220cf6c71dSRob Clark static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val) 2230cf6c71dSRob Clark { 2240cf6c71dSRob Clark return ((val) << HDMI_AUDIO_INFO1_LSV__SHIFT) & HDMI_AUDIO_INFO1_LSV__MASK; 2250cf6c71dSRob Clark } 2260cf6c71dSRob Clark #define HDMI_AUDIO_INFO1_DM_INH 0x00008000 2270cf6c71dSRob Clark 2280cf6c71dSRob Clark #define REG_HDMI_HDCP_CTRL 0x00000110 2290cf6c71dSRob Clark #define HDMI_HDCP_CTRL_ENABLE 0x00000001 2300cf6c71dSRob Clark #define HDMI_HDCP_CTRL_ENCRYPTION_ENABLE 0x00000100 2310cf6c71dSRob Clark 2328a264743SRob Clark #define REG_HDMI_HDCP_DEBUG_CTRL 0x00000114 2338a264743SRob Clark #define HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER 0x00000004 2348a264743SRob Clark 2350cf6c71dSRob Clark #define REG_HDMI_HDCP_INT_CTRL 0x00000118 2368a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT 0x00000001 2378a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_ACK 0x00000002 2388a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_MASK 0x00000004 2398a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT 0x00000010 2408a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_ACK 0x00000020 2418a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_MASK 0x00000040 2428a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK 0x00000080 2438a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_INT 0x00000100 2448a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_ACK 0x00000200 2458a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_MASK 0x00000400 2468a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_INT 0x00001000 2478a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_ACK 0x00002000 2488a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_MASK 0x00004000 2490cf6c71dSRob Clark 2500cf6c71dSRob Clark #define REG_HDMI_HDCP_LINK0_STATUS 0x0000011c 2510cf6c71dSRob Clark #define HDMI_HDCP_LINK0_STATUS_AN_0_READY 0x00000100 2520cf6c71dSRob Clark #define HDMI_HDCP_LINK0_STATUS_AN_1_READY 0x00000200 2538a264743SRob Clark #define HDMI_HDCP_LINK0_STATUS_RI_MATCHES 0x00001000 2548a264743SRob Clark #define HDMI_HDCP_LINK0_STATUS_V_MATCHES 0x00100000 2550cf6c71dSRob Clark #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK 0x70000000 2560cf6c71dSRob Clark #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT 28 2570cf6c71dSRob Clark static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val) 2580cf6c71dSRob Clark { 2590cf6c71dSRob Clark return ((val) << HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT) & HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK; 2600cf6c71dSRob Clark } 2610cf6c71dSRob Clark 2628a264743SRob Clark #define REG_HDMI_HDCP_DDC_CTRL_0 0x00000120 2638a264743SRob Clark #define HDMI_HDCP_DDC_CTRL_0_DISABLE 0x00000001 2648a264743SRob Clark 2658a264743SRob Clark #define REG_HDMI_HDCP_DDC_CTRL_1 0x00000124 2668a264743SRob Clark #define HDMI_HDCP_DDC_CTRL_1_FAILED_ACK 0x00000001 2678a264743SRob Clark 2688a264743SRob Clark #define REG_HDMI_HDCP_DDC_STATUS 0x00000128 2698a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_XFER_REQ 0x00000010 2708a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_XFER_DONE 0x00000400 2718a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_ABORTED 0x00001000 2728a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_TIMEOUT 0x00002000 2738a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_NACK0 0x00004000 2748a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_NACK1 0x00008000 2758a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_FAILED 0x00010000 2768a264743SRob Clark 2778a264743SRob Clark #define REG_HDMI_HDCP_ENTROPY_CTRL0 0x0000012c 2788a264743SRob Clark 2798a264743SRob Clark #define REG_HDMI_HDCP_ENTROPY_CTRL1 0x0000025c 2808a264743SRob Clark 2810cf6c71dSRob Clark #define REG_HDMI_HDCP_RESET 0x00000130 2820cf6c71dSRob Clark #define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE 0x00000001 2830cf6c71dSRob Clark 2848a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA0 0x00000134 2858a264743SRob Clark 2868a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA1 0x00000138 2878a264743SRob Clark 2888a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA2_0 0x0000013c 2898a264743SRob Clark 2908a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA2_1 0x00000140 2918a264743SRob Clark 2928a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA3 0x00000144 2938a264743SRob Clark 2948a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA4 0x00000148 2958a264743SRob Clark 2968a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA5 0x0000014c 2978a264743SRob Clark 2988a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA6 0x00000150 2998a264743SRob Clark 3008a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA7 0x00000154 3018a264743SRob Clark 3028a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA8 0x00000158 3038a264743SRob Clark 3048a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA9 0x0000015c 3058a264743SRob Clark 3068a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA10 0x00000160 3078a264743SRob Clark 3088a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA11 0x00000164 3098a264743SRob Clark 3108a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA12 0x00000168 3118a264743SRob Clark 312facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO0 0x0000016c 313facb4f4eSRob Clark 314facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO1 0x00000170 315facb4f4eSRob Clark 316facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO2 0x00000174 317facb4f4eSRob Clark 318facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO3 0x00000178 319facb4f4eSRob Clark 320facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO4 0x0000017c 321facb4f4eSRob Clark 322facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO5 0x00000180 323facb4f4eSRob Clark 324facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO6 0x00000184 325facb4f4eSRob Clark 3260cf6c71dSRob Clark #define REG_HDMI_AUDIO_CFG 0x000001d0 3270cf6c71dSRob Clark #define HDMI_AUDIO_CFG_ENGINE_ENABLE 0x00000001 3280cf6c71dSRob Clark #define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK 0x000000f0 3290cf6c71dSRob Clark #define HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT 4 3300cf6c71dSRob Clark static inline uint32_t HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val) 3310cf6c71dSRob Clark { 3320cf6c71dSRob Clark return ((val) << HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT) & HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK; 3330cf6c71dSRob Clark } 3340cf6c71dSRob Clark 3350cf6c71dSRob Clark #define REG_HDMI_USEC_REFTIMER 0x00000208 3360cf6c71dSRob Clark 3370cf6c71dSRob Clark #define REG_HDMI_DDC_CTRL 0x0000020c 3380cf6c71dSRob Clark #define HDMI_DDC_CTRL_GO 0x00000001 3390cf6c71dSRob Clark #define HDMI_DDC_CTRL_SOFT_RESET 0x00000002 3400cf6c71dSRob Clark #define HDMI_DDC_CTRL_SEND_RESET 0x00000004 3410cf6c71dSRob Clark #define HDMI_DDC_CTRL_SW_STATUS_RESET 0x00000008 3420cf6c71dSRob Clark #define HDMI_DDC_CTRL_TRANSACTION_CNT__MASK 0x00300000 3430cf6c71dSRob Clark #define HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT 20 3440cf6c71dSRob Clark static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val) 3450cf6c71dSRob Clark { 3460cf6c71dSRob Clark return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK; 3470cf6c71dSRob Clark } 3480cf6c71dSRob Clark 349facb4f4eSRob Clark #define REG_HDMI_DDC_ARBITRATION 0x00000210 350facb4f4eSRob Clark #define HDMI_DDC_ARBITRATION_HW_ARBITRATION 0x00000010 351facb4f4eSRob Clark 3520cf6c71dSRob Clark #define REG_HDMI_DDC_INT_CTRL 0x00000214 3530cf6c71dSRob Clark #define HDMI_DDC_INT_CTRL_SW_DONE_INT 0x00000001 3540cf6c71dSRob Clark #define HDMI_DDC_INT_CTRL_SW_DONE_ACK 0x00000002 3550cf6c71dSRob Clark #define HDMI_DDC_INT_CTRL_SW_DONE_MASK 0x00000004 3560cf6c71dSRob Clark 3570cf6c71dSRob Clark #define REG_HDMI_DDC_SW_STATUS 0x00000218 3580cf6c71dSRob Clark #define HDMI_DDC_SW_STATUS_NACK0 0x00001000 3590cf6c71dSRob Clark #define HDMI_DDC_SW_STATUS_NACK1 0x00002000 3600cf6c71dSRob Clark #define HDMI_DDC_SW_STATUS_NACK2 0x00004000 3610cf6c71dSRob Clark #define HDMI_DDC_SW_STATUS_NACK3 0x00008000 3620cf6c71dSRob Clark 3630cf6c71dSRob Clark #define REG_HDMI_DDC_HW_STATUS 0x0000021c 3648a264743SRob Clark #define HDMI_DDC_HW_STATUS_DONE 0x00000008 3650cf6c71dSRob Clark 3660cf6c71dSRob Clark #define REG_HDMI_DDC_SPEED 0x00000220 3670cf6c71dSRob Clark #define HDMI_DDC_SPEED_THRESHOLD__MASK 0x00000003 3680cf6c71dSRob Clark #define HDMI_DDC_SPEED_THRESHOLD__SHIFT 0 3690cf6c71dSRob Clark static inline uint32_t HDMI_DDC_SPEED_THRESHOLD(uint32_t val) 3700cf6c71dSRob Clark { 3710cf6c71dSRob Clark return ((val) << HDMI_DDC_SPEED_THRESHOLD__SHIFT) & HDMI_DDC_SPEED_THRESHOLD__MASK; 3720cf6c71dSRob Clark } 3730cf6c71dSRob Clark #define HDMI_DDC_SPEED_PRESCALE__MASK 0xffff0000 3740cf6c71dSRob Clark #define HDMI_DDC_SPEED_PRESCALE__SHIFT 16 3750cf6c71dSRob Clark static inline uint32_t HDMI_DDC_SPEED_PRESCALE(uint32_t val) 3760cf6c71dSRob Clark { 3770cf6c71dSRob Clark return ((val) << HDMI_DDC_SPEED_PRESCALE__SHIFT) & HDMI_DDC_SPEED_PRESCALE__MASK; 3780cf6c71dSRob Clark } 3790cf6c71dSRob Clark 3800cf6c71dSRob Clark #define REG_HDMI_DDC_SETUP 0x00000224 3810cf6c71dSRob Clark #define HDMI_DDC_SETUP_TIMEOUT__MASK 0xff000000 3820cf6c71dSRob Clark #define HDMI_DDC_SETUP_TIMEOUT__SHIFT 24 3830cf6c71dSRob Clark static inline uint32_t HDMI_DDC_SETUP_TIMEOUT(uint32_t val) 3840cf6c71dSRob Clark { 3850cf6c71dSRob Clark return ((val) << HDMI_DDC_SETUP_TIMEOUT__SHIFT) & HDMI_DDC_SETUP_TIMEOUT__MASK; 3860cf6c71dSRob Clark } 3870cf6c71dSRob Clark 3880cf6c71dSRob Clark static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; } 3890cf6c71dSRob Clark 3900cf6c71dSRob Clark static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; } 3910cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_RW__MASK 0x00000001 3920cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_RW__SHIFT 0 3930cf6c71dSRob Clark static inline uint32_t HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val) 3940cf6c71dSRob Clark { 3950cf6c71dSRob Clark return ((val) << HDMI_I2C_TRANSACTION_REG_RW__SHIFT) & HDMI_I2C_TRANSACTION_REG_RW__MASK; 3960cf6c71dSRob Clark } 3970cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_STOP_ON_NACK 0x00000100 3980cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_START 0x00001000 3990cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_STOP 0x00002000 4000cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_CNT__MASK 0x00ff0000 4010cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_CNT__SHIFT 16 4020cf6c71dSRob Clark static inline uint32_t HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val) 4030cf6c71dSRob Clark { 4040cf6c71dSRob Clark return ((val) << HDMI_I2C_TRANSACTION_REG_CNT__SHIFT) & HDMI_I2C_TRANSACTION_REG_CNT__MASK; 4050cf6c71dSRob Clark } 4060cf6c71dSRob Clark 4070cf6c71dSRob Clark #define REG_HDMI_DDC_DATA 0x00000238 4080cf6c71dSRob Clark #define HDMI_DDC_DATA_DATA_RW__MASK 0x00000001 4090cf6c71dSRob Clark #define HDMI_DDC_DATA_DATA_RW__SHIFT 0 4100cf6c71dSRob Clark static inline uint32_t HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val) 4110cf6c71dSRob Clark { 4120cf6c71dSRob Clark return ((val) << HDMI_DDC_DATA_DATA_RW__SHIFT) & HDMI_DDC_DATA_DATA_RW__MASK; 4130cf6c71dSRob Clark } 4140cf6c71dSRob Clark #define HDMI_DDC_DATA_DATA__MASK 0x0000ff00 4150cf6c71dSRob Clark #define HDMI_DDC_DATA_DATA__SHIFT 8 4160cf6c71dSRob Clark static inline uint32_t HDMI_DDC_DATA_DATA(uint32_t val) 4170cf6c71dSRob Clark { 4180cf6c71dSRob Clark return ((val) << HDMI_DDC_DATA_DATA__SHIFT) & HDMI_DDC_DATA_DATA__MASK; 4190cf6c71dSRob Clark } 4200cf6c71dSRob Clark #define HDMI_DDC_DATA_INDEX__MASK 0x00ff0000 4210cf6c71dSRob Clark #define HDMI_DDC_DATA_INDEX__SHIFT 16 4220cf6c71dSRob Clark static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val) 4230cf6c71dSRob Clark { 4240cf6c71dSRob Clark return ((val) << HDMI_DDC_DATA_INDEX__SHIFT) & HDMI_DDC_DATA_INDEX__MASK; 4250cf6c71dSRob Clark } 4260cf6c71dSRob Clark #define HDMI_DDC_DATA_INDEX_WRITE 0x80000000 4270cf6c71dSRob Clark 4288a264743SRob Clark #define REG_HDMI_HDCP_SHA_CTRL 0x0000023c 4298a264743SRob Clark 4308a264743SRob Clark #define REG_HDMI_HDCP_SHA_STATUS 0x00000240 4318a264743SRob Clark #define HDMI_HDCP_SHA_STATUS_BLOCK_DONE 0x00000001 4328a264743SRob Clark #define HDMI_HDCP_SHA_STATUS_COMP_DONE 0x00000010 4338a264743SRob Clark 4348a264743SRob Clark #define REG_HDMI_HDCP_SHA_DATA 0x00000244 4358a264743SRob Clark #define HDMI_HDCP_SHA_DATA_DONE 0x00000001 4368a264743SRob Clark 4370cf6c71dSRob Clark #define REG_HDMI_HPD_INT_STATUS 0x00000250 4380cf6c71dSRob Clark #define HDMI_HPD_INT_STATUS_INT 0x00000001 4390cf6c71dSRob Clark #define HDMI_HPD_INT_STATUS_CABLE_DETECTED 0x00000002 4400cf6c71dSRob Clark 4410cf6c71dSRob Clark #define REG_HDMI_HPD_INT_CTRL 0x00000254 4420cf6c71dSRob Clark #define HDMI_HPD_INT_CTRL_INT_ACK 0x00000001 4430cf6c71dSRob Clark #define HDMI_HPD_INT_CTRL_INT_CONNECT 0x00000002 4440cf6c71dSRob Clark #define HDMI_HPD_INT_CTRL_INT_EN 0x00000004 4450cf6c71dSRob Clark #define HDMI_HPD_INT_CTRL_RX_INT_ACK 0x00000010 4460cf6c71dSRob Clark #define HDMI_HPD_INT_CTRL_RX_INT_EN 0x00000020 4470cf6c71dSRob Clark #define HDMI_HPD_INT_CTRL_RCV_PLUGIN_DET_MASK 0x00000200 4480cf6c71dSRob Clark 4490cf6c71dSRob Clark #define REG_HDMI_HPD_CTRL 0x00000258 4500cf6c71dSRob Clark #define HDMI_HPD_CTRL_TIMEOUT__MASK 0x00001fff 4510cf6c71dSRob Clark #define HDMI_HPD_CTRL_TIMEOUT__SHIFT 0 4520cf6c71dSRob Clark static inline uint32_t HDMI_HPD_CTRL_TIMEOUT(uint32_t val) 4530cf6c71dSRob Clark { 4540cf6c71dSRob Clark return ((val) << HDMI_HPD_CTRL_TIMEOUT__SHIFT) & HDMI_HPD_CTRL_TIMEOUT__MASK; 4550cf6c71dSRob Clark } 4560cf6c71dSRob Clark #define HDMI_HPD_CTRL_ENABLE 0x10000000 4570cf6c71dSRob Clark 4580cf6c71dSRob Clark #define REG_HDMI_DDC_REF 0x0000027c 4590cf6c71dSRob Clark #define HDMI_DDC_REF_REFTIMER_ENABLE 0x00010000 4600cf6c71dSRob Clark #define HDMI_DDC_REF_REFTIMER__MASK 0x0000ffff 4610cf6c71dSRob Clark #define HDMI_DDC_REF_REFTIMER__SHIFT 0 4620cf6c71dSRob Clark static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val) 4630cf6c71dSRob Clark { 4640cf6c71dSRob Clark return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK; 4650cf6c71dSRob Clark } 4660cf6c71dSRob Clark 4678a264743SRob Clark #define REG_HDMI_HDCP_SW_UPPER_AKSV 0x00000284 4688a264743SRob Clark 4698a264743SRob Clark #define REG_HDMI_HDCP_SW_LOWER_AKSV 0x00000288 4708a264743SRob Clark 4712d3584ebSRob Clark #define REG_HDMI_CEC_CTRL 0x0000028c 4722d3584ebSRob Clark 4732d3584ebSRob Clark #define REG_HDMI_CEC_WR_DATA 0x00000290 4742d3584ebSRob Clark 4752d3584ebSRob Clark #define REG_HDMI_CEC_CEC_RETRANSMIT 0x00000294 4762d3584ebSRob Clark 477facb4f4eSRob Clark #define REG_HDMI_CEC_STATUS 0x00000298 478facb4f4eSRob Clark 479facb4f4eSRob Clark #define REG_HDMI_CEC_INT 0x0000029c 480facb4f4eSRob Clark 481facb4f4eSRob Clark #define REG_HDMI_CEC_ADDR 0x000002a0 482facb4f4eSRob Clark 483facb4f4eSRob Clark #define REG_HDMI_CEC_TIME 0x000002a4 484facb4f4eSRob Clark 485facb4f4eSRob Clark #define REG_HDMI_CEC_REFTIMER 0x000002a8 486facb4f4eSRob Clark 487facb4f4eSRob Clark #define REG_HDMI_CEC_RD_DATA 0x000002ac 488facb4f4eSRob Clark 489facb4f4eSRob Clark #define REG_HDMI_CEC_RD_FILTER 0x000002b0 490facb4f4eSRob Clark 4910cf6c71dSRob Clark #define REG_HDMI_ACTIVE_HSYNC 0x000002b4 49252260ae4SRob Clark #define HDMI_ACTIVE_HSYNC_START__MASK 0x00001fff 4930cf6c71dSRob Clark #define HDMI_ACTIVE_HSYNC_START__SHIFT 0 4940cf6c71dSRob Clark static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val) 4950cf6c71dSRob Clark { 4960cf6c71dSRob Clark return ((val) << HDMI_ACTIVE_HSYNC_START__SHIFT) & HDMI_ACTIVE_HSYNC_START__MASK; 4970cf6c71dSRob Clark } 4980cf6c71dSRob Clark #define HDMI_ACTIVE_HSYNC_END__MASK 0x0fff0000 4990cf6c71dSRob Clark #define HDMI_ACTIVE_HSYNC_END__SHIFT 16 5000cf6c71dSRob Clark static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val) 5010cf6c71dSRob Clark { 5020cf6c71dSRob Clark return ((val) << HDMI_ACTIVE_HSYNC_END__SHIFT) & HDMI_ACTIVE_HSYNC_END__MASK; 5030cf6c71dSRob Clark } 5040cf6c71dSRob Clark 5050cf6c71dSRob Clark #define REG_HDMI_ACTIVE_VSYNC 0x000002b8 50652260ae4SRob Clark #define HDMI_ACTIVE_VSYNC_START__MASK 0x00001fff 5070cf6c71dSRob Clark #define HDMI_ACTIVE_VSYNC_START__SHIFT 0 5080cf6c71dSRob Clark static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val) 5090cf6c71dSRob Clark { 5100cf6c71dSRob Clark return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK; 5110cf6c71dSRob Clark } 51252260ae4SRob Clark #define HDMI_ACTIVE_VSYNC_END__MASK 0x1fff0000 5130cf6c71dSRob Clark #define HDMI_ACTIVE_VSYNC_END__SHIFT 16 5140cf6c71dSRob Clark static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val) 5150cf6c71dSRob Clark { 5160cf6c71dSRob Clark return ((val) << HDMI_ACTIVE_VSYNC_END__SHIFT) & HDMI_ACTIVE_VSYNC_END__MASK; 5170cf6c71dSRob Clark } 5180cf6c71dSRob Clark 5190cf6c71dSRob Clark #define REG_HDMI_VSYNC_ACTIVE_F2 0x000002bc 52052260ae4SRob Clark #define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00001fff 5210cf6c71dSRob Clark #define HDMI_VSYNC_ACTIVE_F2_START__SHIFT 0 5220cf6c71dSRob Clark static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val) 5230cf6c71dSRob Clark { 5240cf6c71dSRob Clark return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK; 5250cf6c71dSRob Clark } 52652260ae4SRob Clark #define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x1fff0000 5270cf6c71dSRob Clark #define HDMI_VSYNC_ACTIVE_F2_END__SHIFT 16 5280cf6c71dSRob Clark static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val) 5290cf6c71dSRob Clark { 5300cf6c71dSRob Clark return ((val) << HDMI_VSYNC_ACTIVE_F2_END__SHIFT) & HDMI_VSYNC_ACTIVE_F2_END__MASK; 5310cf6c71dSRob Clark } 5320cf6c71dSRob Clark 5330cf6c71dSRob Clark #define REG_HDMI_TOTAL 0x000002c0 53452260ae4SRob Clark #define HDMI_TOTAL_H_TOTAL__MASK 0x00001fff 5350cf6c71dSRob Clark #define HDMI_TOTAL_H_TOTAL__SHIFT 0 5360cf6c71dSRob Clark static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val) 5370cf6c71dSRob Clark { 5380cf6c71dSRob Clark return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK; 5390cf6c71dSRob Clark } 54052260ae4SRob Clark #define HDMI_TOTAL_V_TOTAL__MASK 0x1fff0000 5410cf6c71dSRob Clark #define HDMI_TOTAL_V_TOTAL__SHIFT 16 5420cf6c71dSRob Clark static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val) 5430cf6c71dSRob Clark { 5440cf6c71dSRob Clark return ((val) << HDMI_TOTAL_V_TOTAL__SHIFT) & HDMI_TOTAL_V_TOTAL__MASK; 5450cf6c71dSRob Clark } 5460cf6c71dSRob Clark 5470cf6c71dSRob Clark #define REG_HDMI_VSYNC_TOTAL_F2 0x000002c4 54852260ae4SRob Clark #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00001fff 5490cf6c71dSRob Clark #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT 0 5500cf6c71dSRob Clark static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val) 5510cf6c71dSRob Clark { 5520cf6c71dSRob Clark return ((val) << HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT) & HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK; 5530cf6c71dSRob Clark } 5540cf6c71dSRob Clark 5550cf6c71dSRob Clark #define REG_HDMI_FRAME_CTRL 0x000002c8 5560cf6c71dSRob Clark #define HDMI_FRAME_CTRL_RGB_MUX_SEL_BGR 0x00001000 5570cf6c71dSRob Clark #define HDMI_FRAME_CTRL_VSYNC_LOW 0x10000000 5580cf6c71dSRob Clark #define HDMI_FRAME_CTRL_HSYNC_LOW 0x20000000 5590cf6c71dSRob Clark #define HDMI_FRAME_CTRL_INTERLACED_EN 0x80000000 5600cf6c71dSRob Clark 561facb4f4eSRob Clark #define REG_HDMI_AUD_INT 0x000002cc 562facb4f4eSRob Clark #define HDMI_AUD_INT_AUD_FIFO_URUN_INT 0x00000001 563facb4f4eSRob Clark #define HDMI_AUD_INT_AUD_FIFO_URAN_MASK 0x00000002 564facb4f4eSRob Clark #define HDMI_AUD_INT_AUD_SAM_DROP_INT 0x00000004 565facb4f4eSRob Clark #define HDMI_AUD_INT_AUD_SAM_DROP_MASK 0x00000008 566facb4f4eSRob Clark 5670cf6c71dSRob Clark #define REG_HDMI_PHY_CTRL 0x000002d4 5680cf6c71dSRob Clark #define HDMI_PHY_CTRL_SW_RESET_PLL 0x00000001 5690cf6c71dSRob Clark #define HDMI_PHY_CTRL_SW_RESET_PLL_LOW 0x00000002 5700cf6c71dSRob Clark #define HDMI_PHY_CTRL_SW_RESET 0x00000004 5710cf6c71dSRob Clark #define HDMI_PHY_CTRL_SW_RESET_LOW 0x00000008 5720cf6c71dSRob Clark 573facb4f4eSRob Clark #define REG_HDMI_CEC_WR_RANGE 0x000002dc 574facb4f4eSRob Clark 575facb4f4eSRob Clark #define REG_HDMI_CEC_RD_RANGE 0x000002e0 576facb4f4eSRob Clark 577facb4f4eSRob Clark #define REG_HDMI_VERSION 0x000002e4 578facb4f4eSRob Clark 579facb4f4eSRob Clark #define REG_HDMI_CEC_COMPL_CTL 0x00000360 580facb4f4eSRob Clark 581facb4f4eSRob Clark #define REG_HDMI_CEC_RD_START_RANGE 0x00000364 582facb4f4eSRob Clark 583facb4f4eSRob Clark #define REG_HDMI_CEC_RD_TOTAL_RANGE 0x00000368 584facb4f4eSRob Clark 585facb4f4eSRob Clark #define REG_HDMI_CEC_RD_ERR_RESP_LO 0x0000036c 586facb4f4eSRob Clark 587facb4f4eSRob Clark #define REG_HDMI_CEC_WR_CHECK_CONFIG 0x00000370 5880cf6c71dSRob Clark 589568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG0 0x00000000 5900cf6c71dSRob Clark #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c 5910cf6c71dSRob Clark #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT 2 5920cf6c71dSRob Clark static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val) 5930cf6c71dSRob Clark { 5940cf6c71dSRob Clark return ((val) << HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT) & HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK; 5950cf6c71dSRob Clark } 5960cf6c71dSRob Clark 597568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG1 0x00000004 5980cf6c71dSRob Clark #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK 0x000000f0 5990cf6c71dSRob Clark #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT 4 6000cf6c71dSRob Clark static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val) 6010cf6c71dSRob Clark { 6020cf6c71dSRob Clark return ((val) << HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT) & HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK; 6030cf6c71dSRob Clark } 6040cf6c71dSRob Clark #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK 0x0000000f 6050cf6c71dSRob Clark #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT 0 6060cf6c71dSRob Clark static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val) 6070cf6c71dSRob Clark { 6080cf6c71dSRob Clark return ((val) << HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT) & HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK; 6090cf6c71dSRob Clark } 6100cf6c71dSRob Clark 611568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG2 0x00000008 6120cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_DESER 0x00000001 6130cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_DRIVE_1 0x00000002 6140cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_DRIVE_2 0x00000004 6150cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_DRIVE_3 0x00000008 6160cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_DRIVE_4 0x00000010 6170cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_PLL 0x00000020 6180cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_PWRGEN 0x00000040 6190cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_RCV_SENSE_EN 0x00000080 6200cf6c71dSRob Clark 621568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG3 0x0000000c 6220cf6c71dSRob Clark #define HDMI_8x60_PHY_REG3_PLL_ENABLE 0x00000001 6230cf6c71dSRob Clark 624568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG4 0x00000010 6250cf6c71dSRob Clark 626568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG5 0x00000014 6270cf6c71dSRob Clark 628568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG6 0x00000018 6290cf6c71dSRob Clark 630568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG7 0x0000001c 6310cf6c71dSRob Clark 632568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG8 0x00000020 6330cf6c71dSRob Clark 634568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG9 0x00000024 6350cf6c71dSRob Clark 636568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG10 0x00000028 6370cf6c71dSRob Clark 638568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG11 0x0000002c 6390cf6c71dSRob Clark 640568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG12 0x00000030 6410cf6c71dSRob Clark #define HDMI_8x60_PHY_REG12_RETIMING_EN 0x00000001 6420cf6c71dSRob Clark #define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN 0x00000002 6430cf6c71dSRob Clark #define HDMI_8x60_PHY_REG12_FORCE_LOCK 0x00000010 6440cf6c71dSRob Clark 645568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG0 0x00000000 6460cf6c71dSRob Clark 647568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG1 0x00000004 6480cf6c71dSRob Clark 649568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG2 0x00000008 6500cf6c71dSRob Clark 651568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG3 0x0000000c 6520cf6c71dSRob Clark 653568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG4 0x00000010 6540cf6c71dSRob Clark 655568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG5 0x00000014 6560cf6c71dSRob Clark 657568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG6 0x00000018 6580cf6c71dSRob Clark 659568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG7 0x0000001c 6600cf6c71dSRob Clark 661568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG8 0x00000020 6620cf6c71dSRob Clark 663568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG9 0x00000024 6640cf6c71dSRob Clark 665568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG10 0x00000028 6660cf6c71dSRob Clark 667568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG11 0x0000002c 6680cf6c71dSRob Clark 669568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG12 0x00000030 67089301471SRob Clark #define HDMI_8960_PHY_REG12_SW_RESET 0x00000020 67189301471SRob Clark #define HDMI_8960_PHY_REG12_PWRDN_B 0x00000080 67289301471SRob Clark 673568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG_BIST_CFG 0x00000034 67489301471SRob Clark 675568be320SArchit Taneja #define REG_HDMI_8960_PHY_DEBUG_BUS_SEL 0x00000038 67689301471SRob Clark 677568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG_MISC0 0x0000003c 67889301471SRob Clark 679568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG13 0x00000040 68089301471SRob Clark 681568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG14 0x00000044 68289301471SRob Clark 683568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG15 0x00000048 68489301471SRob Clark 685568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_REFCLK_CFG 0x00000000 68689301471SRob Clark 687568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG 0x00000004 68889301471SRob Clark 689568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 0x00000008 69089301471SRob Clark 691568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 0x0000000c 69289301471SRob Clark 693568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG 0x00000010 69489301471SRob Clark 695568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG 0x00000014 69689301471SRob Clark 697568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_PWRDN_B 0x00000018 69889301471SRob Clark #define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL 0x00000002 69989301471SRob Clark #define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B 0x00000008 70089301471SRob Clark 701568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_SDM_CFG0 0x0000001c 70289301471SRob Clark 703568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_SDM_CFG1 0x00000020 70489301471SRob Clark 705568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_SDM_CFG2 0x00000024 70689301471SRob Clark 707568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_SDM_CFG3 0x00000028 70889301471SRob Clark 709568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_SDM_CFG4 0x0000002c 71089301471SRob Clark 711568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_SSC_CFG0 0x00000030 71289301471SRob Clark 713568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_SSC_CFG1 0x00000034 71489301471SRob Clark 715568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_SSC_CFG2 0x00000038 71689301471SRob Clark 717568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_SSC_CFG3 0x0000003c 71889301471SRob Clark 719568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 0x00000040 72089301471SRob Clark 721568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 0x00000044 72289301471SRob Clark 723568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 0x00000048 72489301471SRob Clark 725568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 0x0000004c 72689301471SRob Clark 727568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 0x00000050 72889301471SRob Clark 729568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 0x00000054 73089301471SRob Clark 731568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 0x00000058 73289301471SRob Clark 733568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 0x0000005c 73489301471SRob Clark 735568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 0x00000060 73689301471SRob Clark 737568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 0x00000064 73889301471SRob Clark 739568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 0x00000068 74089301471SRob Clark 741568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_DEBUG_SEL 0x0000006c 74289301471SRob Clark 743568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_MISC0 0x00000070 74489301471SRob Clark 745568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_MISC1 0x00000074 74689301471SRob Clark 747568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_MISC2 0x00000078 74889301471SRob Clark 749568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_MISC3 0x0000007c 75089301471SRob Clark 751568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_MISC4 0x00000080 75289301471SRob Clark 753568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_MISC5 0x00000084 75489301471SRob Clark 755568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_MISC6 0x00000088 75689301471SRob Clark 757568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0 0x0000008c 75889301471SRob Clark 759568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1 0x00000090 76089301471SRob Clark 761568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2 0x00000094 76289301471SRob Clark 763568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_STATUS0 0x00000098 76489301471SRob Clark #define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK 0x00000001 76589301471SRob Clark 766568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_STATUS1 0x0000009c 7670cf6c71dSRob Clark 768facb4f4eSRob Clark #define REG_HDMI_8x74_ANA_CFG0 0x00000000 769facb4f4eSRob Clark 770facb4f4eSRob Clark #define REG_HDMI_8x74_ANA_CFG1 0x00000004 771facb4f4eSRob Clark 772facb4f4eSRob Clark #define REG_HDMI_8x74_PD_CTRL0 0x00000010 773facb4f4eSRob Clark 774facb4f4eSRob Clark #define REG_HDMI_8x74_PD_CTRL1 0x00000014 775facb4f4eSRob Clark 776facb4f4eSRob Clark #define REG_HDMI_8x74_BIST_CFG0 0x00000034 777facb4f4eSRob Clark 778facb4f4eSRob Clark #define REG_HDMI_8x74_BIST_PATN0 0x0000003c 779facb4f4eSRob Clark 780facb4f4eSRob Clark #define REG_HDMI_8x74_BIST_PATN1 0x00000040 781facb4f4eSRob Clark 782facb4f4eSRob Clark #define REG_HDMI_8x74_BIST_PATN2 0x00000044 783facb4f4eSRob Clark 784facb4f4eSRob Clark #define REG_HDMI_8x74_BIST_PATN3 0x00000048 785facb4f4eSRob Clark 786af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_REFCLK_CFG 0x00000000 787af6cb4c1SRob Clark 788af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004 789af6cb4c1SRob Clark 790af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008 791af6cb4c1SRob Clark 792af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c 793af6cb4c1SRob Clark 794af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_VREG_CFG 0x00000010 795af6cb4c1SRob Clark 796af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014 797af6cb4c1SRob Clark 798af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_DMUX_CFG 0x00000018 799af6cb4c1SRob Clark 800af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_AMUX_CFG 0x0000001c 801af6cb4c1SRob Clark 802af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_GLB_CFG 0x00000020 803af6cb4c1SRob Clark #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001 804af6cb4c1SRob Clark #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002 805af6cb4c1SRob Clark #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004 806af6cb4c1SRob Clark #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008 807af6cb4c1SRob Clark 808af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024 809af6cb4c1SRob Clark 810af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028 811af6cb4c1SRob Clark 812af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_LPFR_CFG 0x0000002c 813af6cb4c1SRob Clark 814af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_LPFC1_CFG 0x00000030 815af6cb4c1SRob Clark 816af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_LPFC2_CFG 0x00000034 817af6cb4c1SRob Clark 818af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SDM_CFG0 0x00000038 819af6cb4c1SRob Clark 820af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SDM_CFG1 0x0000003c 821af6cb4c1SRob Clark 822af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SDM_CFG2 0x00000040 823af6cb4c1SRob Clark 824af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SDM_CFG3 0x00000044 825af6cb4c1SRob Clark 826af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SDM_CFG4 0x00000048 827af6cb4c1SRob Clark 828af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SSC_CFG0 0x0000004c 829af6cb4c1SRob Clark 830af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SSC_CFG1 0x00000050 831af6cb4c1SRob Clark 832af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SSC_CFG2 0x00000054 833af6cb4c1SRob Clark 834af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SSC_CFG3 0x00000058 835af6cb4c1SRob Clark 836af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c 837af6cb4c1SRob Clark 838af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG1 0x00000060 839af6cb4c1SRob Clark 840af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG2 0x00000064 841af6cb4c1SRob Clark 842af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_TEST_CFG 0x00000068 843af6cb4c1SRob Clark #define HDMI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001 844af6cb4c1SRob Clark 845af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG0 0x0000006c 846af6cb4c1SRob Clark 847af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG1 0x00000070 848af6cb4c1SRob Clark 849af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG2 0x00000074 850af6cb4c1SRob Clark 851af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG3 0x00000078 852af6cb4c1SRob Clark 853af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG4 0x0000007c 854af6cb4c1SRob Clark 855af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG5 0x00000080 856af6cb4c1SRob Clark 857af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG6 0x00000084 858af6cb4c1SRob Clark 859af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG7 0x00000088 860af6cb4c1SRob Clark 861af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG8 0x0000008c 862af6cb4c1SRob Clark 863af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG9 0x00000090 864af6cb4c1SRob Clark 865af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG10 0x00000094 866af6cb4c1SRob Clark 867af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG11 0x00000098 868af6cb4c1SRob Clark 869af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c 870af6cb4c1SRob Clark 871af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0 872af6cb4c1SRob Clark 873e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_CFG 0x00000000 874e9a2ce13SArchit Taneja 875e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_PD_CTL 0x00000004 876e9a2ce13SArchit Taneja 877e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_MODE 0x00000008 878e9a2ce13SArchit Taneja 879e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_MISR_CLEAR 0x0000000c 880e9a2ce13SArchit Taneja 881e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG0 0x00000010 882e9a2ce13SArchit Taneja 883e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG1 0x00000014 884e9a2ce13SArchit Taneja 885e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE0 0x00000018 886e9a2ce13SArchit Taneja 887e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE1 0x0000001c 888e9a2ce13SArchit Taneja 889e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN0 0x00000020 890e9a2ce13SArchit Taneja 891e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN1 0x00000024 892e9a2ce13SArchit Taneja 893e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG0 0x00000028 894e9a2ce13SArchit Taneja 895e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG1 0x0000002c 896e9a2ce13SArchit Taneja 897e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE0 0x00000030 898e9a2ce13SArchit Taneja 899e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE1 0x00000034 900e9a2ce13SArchit Taneja 901e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN0 0x00000038 902e9a2ce13SArchit Taneja 903e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN1 0x0000003c 904e9a2ce13SArchit Taneja 905e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_DEBUG_BUS_SEL 0x00000040 906e9a2ce13SArchit Taneja 907e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TXCAL_CFG0 0x00000044 908e9a2ce13SArchit Taneja 909e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TXCAL_CFG1 0x00000048 910e9a2ce13SArchit Taneja 911e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL 0x0000004c 912e9a2ce13SArchit Taneja 913e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL 0x00000050 914e9a2ce13SArchit Taneja 915e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_LANE_BIST_CONFIG 0x00000054 916e9a2ce13SArchit Taneja 917e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_CLOCK 0x00000058 918e9a2ce13SArchit Taneja 919e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_MISC1 0x0000005c 920e9a2ce13SArchit Taneja 921e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_MISC2 0x00000060 922e9a2ce13SArchit Taneja 923e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS0 0x00000064 924e9a2ce13SArchit Taneja 925e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS1 0x00000068 926e9a2ce13SArchit Taneja 927e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS2 0x0000006c 928e9a2ce13SArchit Taneja 929e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS0 0x00000070 930e9a2ce13SArchit Taneja 931e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS1 0x00000074 932e9a2ce13SArchit Taneja 933e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS2 0x00000078 934e9a2ce13SArchit Taneja 935e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_PRE_MISR_STATUS0 0x0000007c 936e9a2ce13SArchit Taneja 937e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_PRE_MISR_STATUS1 0x00000080 938e9a2ce13SArchit Taneja 939e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_PRE_MISR_STATUS2 0x00000084 940e9a2ce13SArchit Taneja 941e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_PRE_MISR_STATUS3 0x00000088 942e9a2ce13SArchit Taneja 943e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_POST_MISR_STATUS0 0x0000008c 944e9a2ce13SArchit Taneja 945e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_POST_MISR_STATUS1 0x00000090 946e9a2ce13SArchit Taneja 947e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_POST_MISR_STATUS2 0x00000094 948e9a2ce13SArchit Taneja 949e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_POST_MISR_STATUS3 0x00000098 950e9a2ce13SArchit Taneja 951e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_STATUS 0x0000009c 952e9a2ce13SArchit Taneja 953e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_MISC3_STATUS 0x000000a0 954e9a2ce13SArchit Taneja 955e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_MISC4_STATUS 0x000000a4 956e9a2ce13SArchit Taneja 957e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_DEBUG_BUS0 0x000000a8 958e9a2ce13SArchit Taneja 959e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_DEBUG_BUS1 0x000000ac 960e9a2ce13SArchit Taneja 961e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_DEBUG_BUS2 0x000000b0 962e9a2ce13SArchit Taneja 963e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_DEBUG_BUS3 0x000000b4 964e9a2ce13SArchit Taneja 965e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_PHY_REVISION_ID0 0x000000b8 966e9a2ce13SArchit Taneja 967e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_PHY_REVISION_ID1 0x000000bc 968e9a2ce13SArchit Taneja 969e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_PHY_REVISION_ID2 0x000000c0 970e9a2ce13SArchit Taneja 971e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_PHY_REVISION_ID3 0x000000c4 972e9a2ce13SArchit Taneja 973e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_ATB_SEL1 0x00000000 974e9a2ce13SArchit Taneja 975e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_ATB_SEL2 0x00000004 976e9a2ce13SArchit Taneja 977e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_FREQ_UPDATE 0x00000008 978e9a2ce13SArchit Taneja 979e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_BG_TIMER 0x0000000c 980e9a2ce13SArchit Taneja 981e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER 0x00000010 982e9a2ce13SArchit Taneja 983e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER1 0x00000014 984e9a2ce13SArchit Taneja 985e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER2 0x00000018 986e9a2ce13SArchit Taneja 987e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SSC_PER1 0x0000001c 988e9a2ce13SArchit Taneja 989e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SSC_PER2 0x00000020 990e9a2ce13SArchit Taneja 991e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1 0x00000024 992e9a2ce13SArchit Taneja 993e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2 0x00000028 994e9a2ce13SArchit Taneja 995e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_POST_DIV 0x0000002c 996e9a2ce13SArchit Taneja 997e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_POST_DIV_MUX 0x00000030 998e9a2ce13SArchit Taneja 999e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x00000034 1000e9a2ce13SArchit Taneja 1001e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1 0x00000038 1002e9a2ce13SArchit Taneja 1003e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL 0x0000003c 1004e9a2ce13SArchit Taneja 1005e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE 0x00000040 1006e9a2ce13SArchit Taneja 1007e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_EN 0x00000044 1008e9a2ce13SArchit Taneja 1009e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_IVCO 0x00000048 1010e9a2ce13SArchit Taneja 1011e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x0000004c 1012e9a2ce13SArchit Taneja 1013e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x00000050 1014e9a2ce13SArchit Taneja 1015e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x00000054 1016e9a2ce13SArchit Taneja 1017e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE1 0x00000058 1018e9a2ce13SArchit Taneja 1019e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE1 0x0000005c 1020e9a2ce13SArchit Taneja 1021e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE1 0x00000060 1022e9a2ce13SArchit Taneja 1023e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE2 0x00000064 1024e9a2ce13SArchit Taneja 1025e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD0 0x00000064 1026e9a2ce13SArchit Taneja 1027e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE2 0x00000068 1028e9a2ce13SArchit Taneja 1029e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x00000068 1030e9a2ce13SArchit Taneja 1031e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE2 0x0000006c 1032e9a2ce13SArchit Taneja 1033e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x0000006c 1034e9a2ce13SArchit Taneja 1035e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_BG_TRIM 0x00000070 1036e9a2ce13SArchit Taneja 1037e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CLK_EP_DIV 0x00000074 1038e9a2ce13SArchit Taneja 1039e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0 0x00000078 1040e9a2ce13SArchit Taneja 1041e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE1 0x0000007c 1042e9a2ce13SArchit Taneja 1043e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE2 0x00000080 1044e9a2ce13SArchit Taneja 1045e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD1 0x00000080 1046e9a2ce13SArchit Taneja 1047e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x00000084 1048e9a2ce13SArchit Taneja 1049e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE1 0x00000088 1050e9a2ce13SArchit Taneja 1051e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE2 0x0000008c 1052e9a2ce13SArchit Taneja 1053e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD2 0x0000008c 1054e9a2ce13SArchit Taneja 1055e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x00000090 1056e9a2ce13SArchit Taneja 1057e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE1 0x00000094 1058e9a2ce13SArchit Taneja 1059e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE2 0x00000098 1060e9a2ce13SArchit Taneja 1061e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD3 0x00000098 1062e9a2ce13SArchit Taneja 1063e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_CNTRL 0x0000009c 1064e9a2ce13SArchit Taneja 1065e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_CTRL 0x000000a0 1066e9a2ce13SArchit Taneja 1067e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_DC 0x000000a4 1068e9a2ce13SArchit Taneja 1069e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_IN_SYNC_SEL 0x000000a8 1070e9a2ce13SArchit Taneja 1071e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x000000a8 1072e9a2ce13SArchit Taneja 1073e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL 0x000000ac 1074e9a2ce13SArchit Taneja 1075e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CML_SYSCLK_SEL 0x000000b0 1076e9a2ce13SArchit Taneja 1077e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL 0x000000b4 1078e9a2ce13SArchit Taneja 1079e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL2 0x000000b8 1080e9a2ce13SArchit Taneja 1081e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL 0x000000bc 1082e9a2ce13SArchit Taneja 1083e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL2 0x000000c0 1084e9a2ce13SArchit Taneja 1085e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM 0x000000c4 1086e9a2ce13SArchit Taneja 1087e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN 0x000000c8 1088e9a2ce13SArchit Taneja 1089e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_CFG 0x000000cc 1090e9a2ce13SArchit Taneja 1091e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0 0x000000d0 1092e9a2ce13SArchit Taneja 1093e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE1 0x000000d4 1094e9a2ce13SArchit Taneja 1095e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE2 0x000000d8 1096e9a2ce13SArchit Taneja 1097e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x000000d8 1098e9a2ce13SArchit Taneja 1099e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0x000000dc 1100e9a2ce13SArchit Taneja 1101e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0x000000e0 1102e9a2ce13SArchit Taneja 1103e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x000000e4 1104e9a2ce13SArchit Taneja 1105e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE1 0x000000e8 1106e9a2ce13SArchit Taneja 1107e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE1 0x000000ec 1108e9a2ce13SArchit Taneja 1109e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE1 0x000000f0 1110e9a2ce13SArchit Taneja 1111e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE2 0x000000f4 1112e9a2ce13SArchit Taneja 1113e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL1 0x000000f4 1114e9a2ce13SArchit Taneja 1115e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE2 0x000000f8 1116e9a2ce13SArchit Taneja 1117e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL2 0x000000f8 1118e9a2ce13SArchit Taneja 1119e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE2 0x000000fc 1120e9a2ce13SArchit Taneja 1121e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD4 0x000000fc 1122e9a2ce13SArchit Taneja 1123e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_INITVAL 0x00000100 1124e9a2ce13SArchit Taneja 1125e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_EN 0x00000104 1126e9a2ce13SArchit Taneja 1127e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x00000108 1128e9a2ce13SArchit Taneja 1129e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x0000010c 1130e9a2ce13SArchit Taneja 1131e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x00000110 1132e9a2ce13SArchit Taneja 1133e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x00000114 1134e9a2ce13SArchit Taneja 1135e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE2 0x00000118 1136e9a2ce13SArchit Taneja 1137e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL1 0x00000118 1138e9a2ce13SArchit Taneja 1139e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE2 0x0000011c 1140e9a2ce13SArchit Taneja 1141e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL2 0x0000011c 1142e9a2ce13SArchit Taneja 1143e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_RES_TRIM_CONTROL2 0x00000120 1144e9a2ce13SArchit Taneja 1145e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL 0x00000124 1146e9a2ce13SArchit Taneja 1147e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP 0x00000128 1148e9a2ce13SArchit Taneja 1149e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE0 0x0000012c 1150e9a2ce13SArchit Taneja 1151e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE0 0x00000130 1152e9a2ce13SArchit Taneja 1153e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE1 0x00000134 1154e9a2ce13SArchit Taneja 1155e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE1 0x00000138 1156e9a2ce13SArchit Taneja 1157e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE2 0x0000013c 1158e9a2ce13SArchit Taneja 1159e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL1 0x0000013c 1160e9a2ce13SArchit Taneja 1161e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE2 0x00000140 1162e9a2ce13SArchit Taneja 1163e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL2 0x00000140 1164e9a2ce13SArchit Taneja 1165e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER1 0x00000144 1166e9a2ce13SArchit Taneja 1167e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER2 0x00000148 1168e9a2ce13SArchit Taneja 1169e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SAR 0x0000014c 1170e9a2ce13SArchit Taneja 1171e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SAR_CLK 0x00000150 1172e9a2ce13SArchit Taneja 1173e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_OUT_STATUS 0x00000154 1174e9a2ce13SArchit Taneja 1175e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_READY_STATUS 0x00000158 1176e9a2ce13SArchit Taneja 1177e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_STATUS 0x0000015c 1178e9a2ce13SArchit Taneja 1179e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_RESET_SM_STATUS 0x00000160 1180e9a2ce13SArchit Taneja 1181e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CODE_STATUS 0x00000164 1182e9a2ce13SArchit Taneja 1183e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE1_STATUS 0x00000168 1184e9a2ce13SArchit Taneja 1185e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE2_STATUS 0x0000016c 1186e9a2ce13SArchit Taneja 1187e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_BG_CTRL 0x00000170 1188e9a2ce13SArchit Taneja 1189e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CLK_SELECT 0x00000174 1190e9a2ce13SArchit Taneja 1191e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL 0x00000178 1192e9a2ce13SArchit Taneja 1193e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x0000017c 1194e9a2ce13SArchit Taneja 1195e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_ANALOG 0x00000180 1196e9a2ce13SArchit Taneja 1197e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV 0x00000184 1198e9a2ce13SArchit Taneja 1199e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SW_RESET 0x00000188 1200e9a2ce13SArchit Taneja 1201e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN 0x0000018c 1202e9a2ce13SArchit Taneja 1203e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS 0x00000190 1204e9a2ce13SArchit Taneja 1205e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG 0x00000194 1206e9a2ce13SArchit Taneja 1207e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_RATE_OVERRIDE 0x00000198 1208e9a2ce13SArchit Taneja 1209e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x0000019c 1210e9a2ce13SArchit Taneja 1211e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS0 0x000001a0 1212e9a2ce13SArchit Taneja 1213e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS1 0x000001a4 1214e9a2ce13SArchit Taneja 1215e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS2 0x000001a8 1216e9a2ce13SArchit Taneja 1217e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS3 0x000001ac 1218e9a2ce13SArchit Taneja 1219e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS_SEL 0x000001b0 1220e9a2ce13SArchit Taneja 1221e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_MISC1 0x000001b4 1222e9a2ce13SArchit Taneja 1223e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_MISC2 0x000001b8 1224e9a2ce13SArchit Taneja 1225e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE1 0x000001bc 1226e9a2ce13SArchit Taneja 1227e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE2 0x000001c0 1228e9a2ce13SArchit Taneja 1229e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD5 0x000001c4 1230e9a2ce13SArchit Taneja 1231e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_MODE_LANENO 0x00000000 1232e9a2ce13SArchit Taneja 1233e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_INVERT 0x00000004 1234e9a2ce13SArchit Taneja 1235e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE 0x00000008 1236e9a2ce13SArchit Taneja 1237e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_ONE 0x0000000c 1238e9a2ce13SArchit Taneja 1239e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_TWO 0x00000010 1240e9a2ce13SArchit Taneja 1241e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_THREE 0x00000014 1242e9a2ce13SArchit Taneja 1243e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL 0x00000018 1244e9a2ce13SArchit Taneja 1245e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_POST2_EMPH 0x0000001c 1246e9a2ce13SArchit Taneja 1247e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_BOOST_LVL_UP_DN 0x00000020 1248e9a2ce13SArchit Taneja 1249e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES 0x00000024 1250e9a2ce13SArchit Taneja 1251e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_IDLE_LVL_LARGE_AMP 0x00000028 1252e9a2ce13SArchit Taneja 1253e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL 0x0000002c 1254e9a2ce13SArchit Taneja 1255e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET 0x00000030 1256e9a2ce13SArchit Taneja 1257e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN 0x00000034 1258e9a2ce13SArchit Taneja 1259e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PRE_STALL_LDO_BOOST_EN 0x00000038 1260e9a2ce13SArchit Taneja 1261e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND 0x0000003c 1262e9a2ce13SArchit Taneja 1263e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_SLEW_CNTL 0x00000040 1264e9a2ce13SArchit Taneja 1265e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_INTERFACE_SELECT 0x00000044 1266e9a2ce13SArchit Taneja 1267e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_LPB_EN 0x00000048 1268e9a2ce13SArchit Taneja 1269e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_TX 0x0000004c 1270e9a2ce13SArchit Taneja 1271e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_RX 0x00000050 1272e9a2ce13SArchit Taneja 1273e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET 0x00000054 1274e9a2ce13SArchit Taneja 1275e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH1 0x00000058 1276e9a2ce13SArchit Taneja 1277e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH2 0x0000005c 1278e9a2ce13SArchit Taneja 1279e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_SERDES_BYP_EN_OUT 0x00000060 1280e9a2ce13SArchit Taneja 1281e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_DEBUG_BUS_SEL 0x00000064 1282e9a2ce13SArchit Taneja 1283e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x00000068 1284e9a2ce13SArchit Taneja 1285e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_POL_INV 0x0000006c 1286e9a2ce13SArchit Taneja 1287e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN 0x00000070 1288e9a2ce13SArchit Taneja 1289e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN1 0x00000074 1290e9a2ce13SArchit Taneja 1291e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN2 0x00000078 1292e9a2ce13SArchit Taneja 1293e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN3 0x0000007c 1294e9a2ce13SArchit Taneja 1295e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN4 0x00000080 1296e9a2ce13SArchit Taneja 1297e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN5 0x00000084 1298e9a2ce13SArchit Taneja 1299e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN6 0x00000088 1300e9a2ce13SArchit Taneja 1301e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN7 0x0000008c 1302e9a2ce13SArchit Taneja 1303e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN8 0x00000090 1304e9a2ce13SArchit Taneja 1305e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE 0x00000094 1306e9a2ce13SArchit Taneja 1307e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE 0x00000098 1308e9a2ce13SArchit Taneja 1309e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE_CONFIGURATION 0x0000009c 1310e9a2ce13SArchit Taneja 1311e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL1 0x000000a0 1312e9a2ce13SArchit Taneja 1313e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL2 0x000000a4 1314e9a2ce13SArchit Taneja 1315e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL 0x000000a8 1316e9a2ce13SArchit Taneja 1317e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL_2 0x000000ac 1318e9a2ce13SArchit Taneja 1319e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED1 0x000000b0 1320e9a2ce13SArchit Taneja 1321e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED2 0x000000b4 1322e9a2ce13SArchit Taneja 1323e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED3 0x000000b8 1324e9a2ce13SArchit Taneja 1325e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED4 0x000000bc 1326e9a2ce13SArchit Taneja 1327e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN 0x000000c0 1328e9a2ce13SArchit Taneja 1329e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN_MUXES 0x000000c4 1330e9a2ce13SArchit Taneja 1331e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN 0x000000c8 1332e9a2ce13SArchit Taneja 1333e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_INTERFACE_MODE 0x000000cc 1334e9a2ce13SArchit Taneja 1335e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_CTRL 0x000000d0 1336e9a2ce13SArchit Taneja 1337e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_ENCODED_OR_DATA 0x000000d4 1338e9a2ce13SArchit Taneja 1339e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND2 0x000000d8 1340e9a2ce13SArchit Taneja 1341e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND2 0x000000dc 1342e9a2ce13SArchit Taneja 1343e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND2 0x000000e0 1344e9a2ce13SArchit Taneja 1345e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND2 0x000000e4 1346e9a2ce13SArchit Taneja 1347e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND0_1 0x000000e8 1348e9a2ce13SArchit Taneja 1349e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND0_1 0x000000ec 1350e9a2ce13SArchit Taneja 1351e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND0_1 0x000000f0 1352e9a2ce13SArchit Taneja 1353e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND0_1 0x000000f4 1354e9a2ce13SArchit Taneja 1355e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1 0x000000f8 1356e9a2ce13SArchit Taneja 1357e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2 0x000000fc 1358e9a2ce13SArchit Taneja 1359e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV_CNTL 0x00000100 1360e9a2ce13SArchit Taneja 1361e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_STATUS 0x00000104 1362e9a2ce13SArchit Taneja 1363e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT1 0x00000108 1364e9a2ce13SArchit Taneja 1365e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT2 0x0000010c 1366e9a2ce13SArchit Taneja 1367e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV 0x00000110 1368e9a2ce13SArchit Taneja 13690cf6c71dSRob Clark 13700cf6c71dSRob Clark #endif /* HDMI_XML */ 1371