1 /*
2  * SPDX-License-Identifier: GPL-2.0
3  * Copyright (c) 2018, The Linux Foundation
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/iopoll.h>
9 
10 #include "dsi_phy.h"
11 #include "dsi.xml.h"
12 #include "dsi_phy_7nm.xml.h"
13 
14 /*
15  * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
16  *
17  *           dsi0_pll_out_div_clk  dsi0_pll_bit_clk
18  *                              |                |
19  *                              |                |
20  *                 +---------+  |  +----------+  |  +----+
21  *  dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
22  *                 +---------+  |  +----------+  |  +----+
23  *                              |                |
24  *                              |                |         dsi0_pll_by_2_bit_clk
25  *                              |                |          |
26  *                              |                |  +----+  |  |\  dsi0_pclk_mux
27  *                              |                |--| /2 |--o--| \   |
28  *                              |                |  +----+     |  \  |  +---------+
29  *                              |                --------------|  |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk
30  *                              |------------------------------|  /     +---------+
31  *                              |          +-----+             | /
32  *                              -----------| /4? |--o----------|/
33  *                                         +-----+  |           |
34  *                                                  |           |dsiclk_sel
35  *                                                  |
36  *                                                  dsi0_pll_post_out_div_clk
37  */
38 
39 #define VCO_REF_CLK_RATE		19200000
40 #define FRAC_BITS 18
41 
42 /* Hardware is V4.1 */
43 #define DSI_PHY_7NM_QUIRK_V4_1		BIT(0)
44 
45 struct dsi_pll_config {
46 	bool enable_ssc;
47 	bool ssc_center;
48 	u32 ssc_freq;
49 	u32 ssc_offset;
50 	u32 ssc_adj_per;
51 
52 	/* out */
53 	u32 decimal_div_start;
54 	u32 frac_div_start;
55 	u32 pll_clock_inverters;
56 	u32 ssc_stepsize;
57 	u32 ssc_div_per;
58 };
59 
60 struct pll_7nm_cached_state {
61 	unsigned long vco_rate;
62 	u8 bit_clk_div;
63 	u8 pix_clk_div;
64 	u8 pll_out_div;
65 	u8 pll_mux;
66 };
67 
68 struct dsi_pll_7nm {
69 	struct clk_hw clk_hw;
70 
71 	struct msm_dsi_phy *phy;
72 
73 	u64 vco_current_rate;
74 
75 	/* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */
76 	spinlock_t postdiv_lock;
77 
78 	struct pll_7nm_cached_state cached_state;
79 
80 	struct dsi_pll_7nm *slave;
81 };
82 
83 #define to_pll_7nm(x)	container_of(x, struct dsi_pll_7nm, clk_hw)
84 
85 /*
86  * Global list of private DSI PLL struct pointers. We need this for bonded DSI
87  * mode, where the master PLL's clk_ops needs access the slave's private data
88  */
89 static struct dsi_pll_7nm *pll_7nm_list[DSI_MAX];
90 
91 static void dsi_pll_setup_config(struct dsi_pll_config *config)
92 {
93 	config->ssc_freq = 31500;
94 	config->ssc_offset = 4800;
95 	config->ssc_adj_per = 2;
96 
97 	/* TODO: ssc enable */
98 	config->enable_ssc = false;
99 	config->ssc_center = 0;
100 }
101 
102 static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
103 {
104 	u64 fref = VCO_REF_CLK_RATE;
105 	u64 pll_freq;
106 	u64 divider;
107 	u64 dec, dec_multiple;
108 	u32 frac;
109 	u64 multiplier;
110 
111 	pll_freq = pll->vco_current_rate;
112 
113 	divider = fref * 2;
114 
115 	multiplier = 1 << FRAC_BITS;
116 	dec_multiple = div_u64(pll_freq * multiplier, divider);
117 	dec = div_u64_rem(dec_multiple, multiplier, &frac);
118 
119 	if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
120 		config->pll_clock_inverters = 0x28;
121 	else if (pll_freq <= 1000000000ULL)
122 		config->pll_clock_inverters = 0xa0;
123 	else if (pll_freq <= 2500000000ULL)
124 		config->pll_clock_inverters = 0x20;
125 	else if (pll_freq <= 3020000000ULL)
126 		config->pll_clock_inverters = 0x00;
127 	else
128 		config->pll_clock_inverters = 0x40;
129 
130 	config->decimal_div_start = dec;
131 	config->frac_div_start = frac;
132 }
133 
134 #define SSC_CENTER		BIT(0)
135 #define SSC_EN			BIT(1)
136 
137 static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
138 {
139 	u32 ssc_per;
140 	u32 ssc_mod;
141 	u64 ssc_step_size;
142 	u64 frac;
143 
144 	if (!config->enable_ssc) {
145 		DBG("SSC not enabled\n");
146 		return;
147 	}
148 
149 	ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1;
150 	ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1);
151 	ssc_per -= ssc_mod;
152 
153 	frac = config->frac_div_start;
154 	ssc_step_size = config->decimal_div_start;
155 	ssc_step_size *= (1 << FRAC_BITS);
156 	ssc_step_size += frac;
157 	ssc_step_size *= config->ssc_offset;
158 	ssc_step_size *= (config->ssc_adj_per + 1);
159 	ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1));
160 	ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000);
161 
162 	config->ssc_div_per = ssc_per;
163 	config->ssc_stepsize = ssc_step_size;
164 
165 	pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n",
166 		 config->decimal_div_start, frac, FRAC_BITS);
167 	pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n",
168 		 ssc_per, (u32)ssc_step_size, config->ssc_adj_per);
169 }
170 
171 static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
172 {
173 	void __iomem *base = pll->phy->pll_base;
174 
175 	if (config->enable_ssc) {
176 		pr_debug("SSC is enabled\n");
177 
178 		dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
179 			  config->ssc_stepsize & 0xff);
180 		dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
181 			  config->ssc_stepsize >> 8);
182 		dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1,
183 			  config->ssc_div_per & 0xff);
184 		dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
185 			  config->ssc_div_per >> 8);
186 		dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1,
187 			  config->ssc_adj_per & 0xff);
188 		dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1,
189 			  config->ssc_adj_per >> 8);
190 		dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL,
191 			  SSC_EN | (config->ssc_center ? SSC_CENTER : 0));
192 	}
193 }
194 
195 static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
196 {
197 	void __iomem *base = pll->phy->pll_base;
198 	u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
199 
200 	if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
201 		if (pll->vco_current_rate >= 3100000000ULL)
202 			analog_controls_five_1 = 0x03;
203 
204 		if (pll->vco_current_rate < 1520000000ULL)
205 			vco_config_1 = 0x08;
206 		else if (pll->vco_current_rate < 2990000000ULL)
207 			vco_config_1 = 0x01;
208 	}
209 
210 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
211 		  analog_controls_five_1);
212 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
213 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE, 0x01);
214 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
215 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00);
216 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER, 0x00);
217 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
218 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
219 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba);
220 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c);
221 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_OUTDIV, 0x00);
222 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE, 0x00);
223 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);
224 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x0a);
225 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1, 0xc0);
226 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x84);
227 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82);
228 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c);
229 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
230 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x29);
231 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
232 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
233 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
234 		  pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22);
235 
236 	if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
237 		dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
238 		if (pll->slave)
239 			dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
240 	}
241 }
242 
243 static void dsi_pll_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
244 {
245 	void __iomem *base = pll->phy->pll_base;
246 
247 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
248 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1, config->decimal_div_start);
249 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1,
250 		  config->frac_div_start & 0xff);
251 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1,
252 		  (config->frac_div_start & 0xff00) >> 8);
253 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
254 		  (config->frac_div_start & 0x30000) >> 16);
255 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40);
256 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
257 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, pll->phy->cphy_mode ? 0x00 : 0x10);
258 	dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, config->pll_clock_inverters);
259 }
260 
261 static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
262 				     unsigned long parent_rate)
263 {
264 	struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
265 	struct dsi_pll_config config;
266 
267 	DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->phy->id, rate,
268 	    parent_rate);
269 
270 	pll_7nm->vco_current_rate = rate;
271 
272 	dsi_pll_setup_config(&config);
273 
274 	dsi_pll_calc_dec_frac(pll_7nm, &config);
275 
276 	dsi_pll_calc_ssc(pll_7nm, &config);
277 
278 	dsi_pll_commit(pll_7nm, &config);
279 
280 	dsi_pll_config_hzindep_reg(pll_7nm);
281 
282 	dsi_pll_ssc_commit(pll_7nm, &config);
283 
284 	/* flush, ensure all register writes are done*/
285 	wmb();
286 
287 	return 0;
288 }
289 
290 static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
291 {
292 	int rc;
293 	u32 status = 0;
294 	u32 const delay_us = 100;
295 	u32 const timeout_us = 5000;
296 
297 	rc = readl_poll_timeout_atomic(pll->phy->pll_base +
298 				       REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE,
299 				       status,
300 				       ((status & BIT(0)) > 0),
301 				       delay_us,
302 				       timeout_us);
303 	if (rc)
304 		pr_err("DSI PLL(%d) lock failed, status=0x%08x\n",
305 		       pll->phy->id, status);
306 
307 	return rc;
308 }
309 
310 static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
311 {
312 	u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
313 
314 	dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0);
315 	dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5));
316 	ndelay(250);
317 }
318 
319 static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll)
320 {
321 	u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
322 
323 	dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5));
324 	dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
325 	ndelay(250);
326 }
327 
328 static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
329 {
330 	u32 data;
331 
332 	data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
333 	dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5));
334 }
335 
336 static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll)
337 {
338 	u32 data;
339 
340 	dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04);
341 
342 	data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
343 	dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1,
344 		  data | BIT(5) | BIT(4));
345 }
346 
347 static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll)
348 {
349 	/*
350 	 * Reset the PHY digital domain. This would be needed when
351 	 * coming out of a CX or analog rail power collapse while
352 	 * ensuring that the pads maintain LP00 or LP11 state
353 	 */
354 	dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0));
355 	wmb(); /* Ensure that the reset is deasserted */
356 	dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0);
357 	wmb(); /* Ensure that the reset is deasserted */
358 }
359 
360 static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
361 {
362 	struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
363 	int rc;
364 
365 	dsi_pll_enable_pll_bias(pll_7nm);
366 	if (pll_7nm->slave)
367 		dsi_pll_enable_pll_bias(pll_7nm->slave);
368 
369 	/* Start PLL */
370 	dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01);
371 
372 	/*
373 	 * ensure all PLL configurations are written prior to checking
374 	 * for PLL lock.
375 	 */
376 	wmb();
377 
378 	/* Check for PLL lock */
379 	rc = dsi_pll_7nm_lock_status(pll_7nm);
380 	if (rc) {
381 		pr_err("PLL(%d) lock failed\n", pll_7nm->phy->id);
382 		goto error;
383 	}
384 
385 	pll_7nm->phy->pll_on = true;
386 
387 	/*
388 	 * assert power on reset for PHY digital in case the PLL is
389 	 * enabled after CX of analog domain power collapse. This needs
390 	 * to be done before enabling the global clk.
391 	 */
392 	dsi_pll_phy_dig_reset(pll_7nm);
393 	if (pll_7nm->slave)
394 		dsi_pll_phy_dig_reset(pll_7nm->slave);
395 
396 	dsi_pll_enable_global_clk(pll_7nm);
397 	if (pll_7nm->slave)
398 		dsi_pll_enable_global_clk(pll_7nm->slave);
399 
400 error:
401 	return rc;
402 }
403 
404 static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll)
405 {
406 	dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0);
407 	dsi_pll_disable_pll_bias(pll);
408 }
409 
410 static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw)
411 {
412 	struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
413 
414 	/*
415 	 * To avoid any stray glitches while abruptly powering down the PLL
416 	 * make sure to gate the clock using the clock enable bit before
417 	 * powering down the PLL
418 	 */
419 	dsi_pll_disable_global_clk(pll_7nm);
420 	dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0);
421 	dsi_pll_disable_sub(pll_7nm);
422 	if (pll_7nm->slave) {
423 		dsi_pll_disable_global_clk(pll_7nm->slave);
424 		dsi_pll_disable_sub(pll_7nm->slave);
425 	}
426 	/* flush, ensure all register writes are done */
427 	wmb();
428 	pll_7nm->phy->pll_on = false;
429 }
430 
431 static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
432 						  unsigned long parent_rate)
433 {
434 	struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
435 	void __iomem *base = pll_7nm->phy->pll_base;
436 	u64 ref_clk = VCO_REF_CLK_RATE;
437 	u64 vco_rate = 0x0;
438 	u64 multiplier;
439 	u32 frac;
440 	u32 dec;
441 	u64 pll_freq, tmp64;
442 
443 	dec = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1);
444 	dec &= 0xff;
445 
446 	frac = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1);
447 	frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) &
448 		  0xff) << 8);
449 	frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
450 		  0x3) << 16);
451 
452 	/*
453 	 * TODO:
454 	 *	1. Assumes prescaler is disabled
455 	 */
456 	multiplier = 1 << FRAC_BITS;
457 	pll_freq = dec * (ref_clk * 2);
458 	tmp64 = (ref_clk * 2 * frac);
459 	pll_freq += div_u64(tmp64, multiplier);
460 
461 	vco_rate = pll_freq;
462 	pll_7nm->vco_current_rate = vco_rate;
463 
464 	DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x",
465 	    pll_7nm->phy->id, (unsigned long)vco_rate, dec, frac);
466 
467 	return (unsigned long)vco_rate;
468 }
469 
470 static long dsi_pll_7nm_clk_round_rate(struct clk_hw *hw,
471 		unsigned long rate, unsigned long *parent_rate)
472 {
473 	struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
474 
475 	if      (rate < pll_7nm->phy->cfg->min_pll_rate)
476 		return  pll_7nm->phy->cfg->min_pll_rate;
477 	else if (rate > pll_7nm->phy->cfg->max_pll_rate)
478 		return  pll_7nm->phy->cfg->max_pll_rate;
479 	else
480 		return rate;
481 }
482 
483 static const struct clk_ops clk_ops_dsi_pll_7nm_vco = {
484 	.round_rate = dsi_pll_7nm_clk_round_rate,
485 	.set_rate = dsi_pll_7nm_vco_set_rate,
486 	.recalc_rate = dsi_pll_7nm_vco_recalc_rate,
487 	.prepare = dsi_pll_7nm_vco_prepare,
488 	.unprepare = dsi_pll_7nm_vco_unprepare,
489 };
490 
491 /*
492  * PLL Callbacks
493  */
494 
495 static void dsi_7nm_pll_save_state(struct msm_dsi_phy *phy)
496 {
497 	struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
498 	struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
499 	void __iomem *phy_base = pll_7nm->phy->base;
500 	u32 cmn_clk_cfg0, cmn_clk_cfg1;
501 
502 	cached->pll_out_div = dsi_phy_read(pll_7nm->phy->pll_base +
503 				       REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
504 	cached->pll_out_div &= 0x3;
505 
506 	cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
507 	cached->bit_clk_div = cmn_clk_cfg0 & 0xf;
508 	cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4;
509 
510 	cmn_clk_cfg1 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
511 	cached->pll_mux = cmn_clk_cfg1 & 0x3;
512 
513 	DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
514 	    pll_7nm->phy->id, cached->pll_out_div, cached->bit_clk_div,
515 	    cached->pix_clk_div, cached->pll_mux);
516 }
517 
518 static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy)
519 {
520 	struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
521 	struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
522 	void __iomem *phy_base = pll_7nm->phy->base;
523 	u32 val;
524 	int ret;
525 
526 	val = dsi_phy_read(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
527 	val &= ~0x3;
528 	val |= cached->pll_out_div;
529 	dsi_phy_write(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val);
530 
531 	dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
532 		  cached->bit_clk_div | (cached->pix_clk_div << 4));
533 
534 	val = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
535 	val &= ~0x3;
536 	val |= cached->pll_mux;
537 	dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
538 
539 	ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw,
540 			pll_7nm->vco_current_rate,
541 			VCO_REF_CLK_RATE);
542 	if (ret) {
543 		DRM_DEV_ERROR(&pll_7nm->phy->pdev->dev,
544 			"restore vco rate failed. ret=%d\n", ret);
545 		return ret;
546 	}
547 
548 	DBG("DSI PLL%d", pll_7nm->phy->id);
549 
550 	return 0;
551 }
552 
553 static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
554 {
555 	struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
556 	void __iomem *base = phy->base;
557 	u32 data = 0x0;	/* internal PLL */
558 
559 	DBG("DSI PLL%d", pll_7nm->phy->id);
560 
561 	switch (phy->usecase) {
562 	case MSM_DSI_PHY_STANDALONE:
563 		break;
564 	case MSM_DSI_PHY_MASTER:
565 		pll_7nm->slave = pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX];
566 		break;
567 	case MSM_DSI_PHY_SLAVE:
568 		data = 0x1; /* external PLL */
569 		break;
570 	default:
571 		return -EINVAL;
572 	}
573 
574 	/* set PLL src */
575 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2));
576 
577 	return 0;
578 }
579 
580 /*
581  * The post dividers and mux clocks are created using the standard divider and
582  * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux
583  * state to follow the master PLL's divider/mux state. Therefore, we don't
584  * require special clock ops that also configure the slave PLL registers
585  */
586 static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provided_clocks)
587 {
588 	char clk_name[32], parent[32], vco_name[32];
589 	char parent2[32], parent3[32], parent4[32];
590 	struct clk_init_data vco_init = {
591 		.parent_names = (const char *[]){ "bi_tcxo" },
592 		.num_parents = 1,
593 		.name = vco_name,
594 		.flags = CLK_IGNORE_UNUSED,
595 		.ops = &clk_ops_dsi_pll_7nm_vco,
596 	};
597 	struct device *dev = &pll_7nm->phy->pdev->dev;
598 	struct clk_hw *hw;
599 	int ret;
600 
601 	DBG("DSI%d", pll_7nm->phy->id);
602 
603 	snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->phy->id);
604 	pll_7nm->clk_hw.init = &vco_init;
605 
606 	ret = devm_clk_hw_register(dev, &pll_7nm->clk_hw);
607 	if (ret)
608 		return ret;
609 
610 	snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
611 	snprintf(parent, 32, "dsi%dvco_clk", pll_7nm->phy->id);
612 
613 	hw = devm_clk_hw_register_divider(dev, clk_name,
614 				     parent, CLK_SET_RATE_PARENT,
615 				     pll_7nm->phy->pll_base +
616 				     REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE,
617 				     0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
618 	if (IS_ERR(hw)) {
619 		ret = PTR_ERR(hw);
620 		goto fail;
621 	}
622 
623 	snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
624 	snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
625 
626 	/* BIT CLK: DIV_CTRL_3_0 */
627 	hw = devm_clk_hw_register_divider(dev, clk_name, parent,
628 				     CLK_SET_RATE_PARENT,
629 				     pll_7nm->phy->base +
630 				     REG_DSI_7nm_PHY_CMN_CLK_CFG0,
631 				     0, 4, CLK_DIVIDER_ONE_BASED,
632 				     &pll_7nm->postdiv_lock);
633 	if (IS_ERR(hw)) {
634 		ret = PTR_ERR(hw);
635 		goto fail;
636 	}
637 
638 	snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_7nm->phy->id);
639 	snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
640 
641 	/* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
642 	hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
643 					  CLK_SET_RATE_PARENT, 1,
644 					  pll_7nm->phy->cphy_mode ? 7 : 8);
645 	if (IS_ERR(hw)) {
646 		ret = PTR_ERR(hw);
647 		goto fail;
648 	}
649 
650 	provided_clocks[DSI_BYTE_PLL_CLK] = hw;
651 
652 	snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id);
653 	snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
654 
655 	hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
656 					  0, 1, 2);
657 	if (IS_ERR(hw)) {
658 		ret = PTR_ERR(hw);
659 		goto fail;
660 	}
661 
662 	snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id);
663 	snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
664 
665 	if (pll_7nm->phy->cphy_mode)
666 		hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 2, 7);
667 	else
668 		hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 4);
669 	if (IS_ERR(hw)) {
670 		ret = PTR_ERR(hw);
671 		goto fail;
672 	}
673 
674 	/* in CPHY mode, pclk_mux will always have post_out_div as parent
675 	 * don't register a pclk_mux clock and just use post_out_div instead
676 	 */
677 	if (pll_7nm->phy->cphy_mode) {
678 		u32 data;
679 
680 		data = dsi_phy_read(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
681 		dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data | 3);
682 
683 		snprintf(parent, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id);
684 	} else {
685 		snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->phy->id);
686 		snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
687 		snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id);
688 		snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
689 		snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id);
690 
691 		hw = devm_clk_hw_register_mux(dev, clk_name,
692 					((const char *[]){
693 					parent, parent2, parent3, parent4
694 					}), 4, 0, pll_7nm->phy->base +
695 					REG_DSI_7nm_PHY_CMN_CLK_CFG1,
696 					0, 2, 0, NULL);
697 		if (IS_ERR(hw)) {
698 			ret = PTR_ERR(hw);
699 			goto fail;
700 		}
701 
702 		snprintf(parent, 32, "dsi%d_pclk_mux", pll_7nm->phy->id);
703 	}
704 
705 	snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->phy->id);
706 
707 	/* PIX CLK DIV : DIV_CTRL_7_4*/
708 	hw = devm_clk_hw_register_divider(dev, clk_name, parent,
709 				     0, pll_7nm->phy->base +
710 					REG_DSI_7nm_PHY_CMN_CLK_CFG0,
711 				     4, 4, CLK_DIVIDER_ONE_BASED,
712 				     &pll_7nm->postdiv_lock);
713 	if (IS_ERR(hw)) {
714 		ret = PTR_ERR(hw);
715 		goto fail;
716 	}
717 
718 	provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
719 
720 	return 0;
721 
722 fail:
723 
724 	return ret;
725 }
726 
727 static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
728 {
729 	struct platform_device *pdev = phy->pdev;
730 	struct dsi_pll_7nm *pll_7nm;
731 	int ret;
732 
733 	pll_7nm = devm_kzalloc(&pdev->dev, sizeof(*pll_7nm), GFP_KERNEL);
734 	if (!pll_7nm)
735 		return -ENOMEM;
736 
737 	DBG("DSI PLL%d", phy->id);
738 
739 	pll_7nm_list[phy->id] = pll_7nm;
740 
741 	spin_lock_init(&pll_7nm->postdiv_lock);
742 
743 	pll_7nm->phy = phy;
744 
745 	ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws);
746 	if (ret) {
747 		DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
748 		return ret;
749 	}
750 
751 	phy->vco_hw = &pll_7nm->clk_hw;
752 
753 	/* TODO: Remove this when we have proper display handover support */
754 	msm_dsi_phy_pll_save_state(phy);
755 
756 	return 0;
757 }
758 
759 static int dsi_phy_hw_v4_0_is_pll_on(struct msm_dsi_phy *phy)
760 {
761 	void __iomem *base = phy->base;
762 	u32 data = 0;
763 
764 	data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL);
765 	mb(); /* make sure read happened */
766 
767 	return (data & BIT(0));
768 }
769 
770 static void dsi_phy_hw_v4_0_config_lpcdrx(struct msm_dsi_phy *phy, bool enable)
771 {
772 	void __iomem *lane_base = phy->lane_base;
773 	int phy_lane_0 = 0;	/* TODO: Support all lane swap configs */
774 
775 	/*
776 	 * LPRX and CDRX need to enabled only for physical data lane
777 	 * corresponding to the logical data lane 0
778 	 */
779 	if (enable)
780 		dsi_phy_write(lane_base +
781 			      REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0x3);
782 	else
783 		dsi_phy_write(lane_base +
784 			      REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0);
785 }
786 
787 static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy)
788 {
789 	int i;
790 	const u8 tx_dctrl_0[] = { 0x00, 0x00, 0x00, 0x04, 0x01 };
791 	const u8 tx_dctrl_1[] = { 0x40, 0x40, 0x40, 0x46, 0x41 };
792 	const u8 *tx_dctrl = tx_dctrl_0;
793 	void __iomem *lane_base = phy->lane_base;
794 
795 	if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)
796 		tx_dctrl = tx_dctrl_1;
797 
798 	/* Strength ctrl settings */
799 	for (i = 0; i < 5; i++) {
800 		/*
801 		 * Disable LPRX and CDRX for all lanes. And later on, it will
802 		 * be only enabled for the physical data lane corresponding
803 		 * to the logical data lane 0
804 		 */
805 		dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(i), 0);
806 		dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_PIN_SWAP(i), 0x0);
807 	}
808 
809 	dsi_phy_hw_v4_0_config_lpcdrx(phy, true);
810 
811 	/* other settings */
812 	for (i = 0; i < 5; i++) {
813 		dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG0(i), 0x0);
814 		dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG1(i), 0x0);
815 		dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG2(i), i == 4 ? 0x8a : 0xa);
816 		dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_TX_DCTRL(i), tx_dctrl[i]);
817 	}
818 }
819 
820 static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
821 			      struct msm_dsi_phy_clk_request *clk_req)
822 {
823 	int ret;
824 	u32 status;
825 	u32 const delay_us = 5;
826 	u32 const timeout_us = 1000;
827 	struct msm_dsi_dphy_timing *timing = &phy->timing;
828 	void __iomem *base = phy->base;
829 	bool less_than_1500_mhz;
830 	u32 vreg_ctrl_0, vreg_ctrl_1, lane_ctrl0;
831 	u32 glbl_pemph_ctrl_0;
832 	u32 glbl_str_swi_cal_sel_ctrl, glbl_hstx_str_ctrl_0;
833 	u32 glbl_rescode_top_ctrl, glbl_rescode_bot_ctrl;
834 	u32 data;
835 
836 	DBG("");
837 
838 	if (phy->cphy_mode)
839 		ret = msm_dsi_cphy_timing_calc_v4(timing, clk_req);
840 	else
841 		ret = msm_dsi_dphy_timing_calc_v4(timing, clk_req);
842 	if (ret) {
843 		DRM_DEV_ERROR(&phy->pdev->dev,
844 			"%s: PHY timing calculation failed\n", __func__);
845 		return -EINVAL;
846 	}
847 
848 	if (dsi_phy_hw_v4_0_is_pll_on(phy))
849 		pr_warn("PLL turned on before configuring PHY\n");
850 
851 	/* wait for REFGEN READY */
852 	ret = readl_poll_timeout_atomic(base + REG_DSI_7nm_PHY_CMN_PHY_STATUS,
853 					status, (status & BIT(0)),
854 					delay_us, timeout_us);
855 	if (ret) {
856 		pr_err("Ref gen not ready. Aborting\n");
857 		return -EINVAL;
858 	}
859 
860 	/* TODO: CPHY enable path (this is for DPHY only) */
861 
862 	/* Alter PHY configurations if data rate less than 1.5GHZ*/
863 	less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000);
864 
865 	/* For C-PHY, no low power settings for lower clk rate */
866 	if (phy->cphy_mode)
867 		less_than_1500_mhz = false;
868 
869 	if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
870 		vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
871 		glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d :  0x00;
872 		glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 :  0x3c;
873 		glbl_str_swi_cal_sel_ctrl = 0x00;
874 		glbl_hstx_str_ctrl_0 = 0x88;
875 	} else {
876 		vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
877 		glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00;
878 		glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;
879 		glbl_rescode_top_ctrl = 0x03;
880 		glbl_rescode_bot_ctrl = 0x3c;
881 	}
882 
883 	if (phy->cphy_mode) {
884 		vreg_ctrl_0 = 0x51;
885 		vreg_ctrl_1 = 0x55;
886 		glbl_pemph_ctrl_0 = 0x11;
887 		lane_ctrl0 = 0x17;
888 	} else {
889 		vreg_ctrl_1 = 0x5c;
890 		glbl_pemph_ctrl_0 = 0x00;
891 		lane_ctrl0 = 0x1f;
892 	}
893 
894 	/* de-assert digital and pll power down */
895 	data = BIT(6) | BIT(5);
896 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data);
897 
898 	/* Assert PLL core reset */
899 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x00);
900 
901 	/* turn off resync FIFO */
902 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0x00);
903 
904 	/* program CMN_CTRL_4 for minor_ver 2 chipsets*/
905 	data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0);
906 	data = data & (0xf0);
907 	if (data == 0x20)
908 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_4, 0x04);
909 
910 	/* Configure PHY lane swap (TODO: we need to calculate this) */
911 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG0, 0x21);
912 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG1, 0x84);
913 
914 	if (phy->cphy_mode)
915 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_CTRL, BIT(6));
916 
917 	/* Enable LDO */
918 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_0, vreg_ctrl_0);
919 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_1, vreg_ctrl_1);
920 
921 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x00);
922 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL,
923 		      glbl_str_swi_cal_sel_ctrl);
924 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0,
925 		      glbl_hstx_str_ctrl_0);
926 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0,
927 		      glbl_pemph_ctrl_0);
928 	if (phy->cphy_mode)
929 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1, 0x01);
930 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL,
931 		      glbl_rescode_top_ctrl);
932 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL,
933 		      glbl_rescode_bot_ctrl);
934 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL, 0x55);
935 
936 	/* Remove power down from all blocks */
937 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x7f);
938 
939 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, lane_ctrl0);
940 
941 	/* Select full-rate mode */
942 	if (!phy->cphy_mode)
943 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_2, 0x40);
944 
945 	ret = dsi_7nm_set_usecase(phy);
946 	if (ret) {
947 		DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
948 			__func__, ret);
949 		return ret;
950 	}
951 
952 	/* DSI PHY timings */
953 	if (phy->cphy_mode) {
954 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0, 0x00);
955 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4, timing->hs_exit);
956 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5,
957 			timing->shared_timings.clk_pre);
958 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6, timing->clk_prepare);
959 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7,
960 			timing->shared_timings.clk_post);
961 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8, timing->hs_rqst);
962 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9, 0x02);
963 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10, 0x04);
964 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11, 0x00);
965 	} else {
966 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0, 0x00);
967 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1, timing->clk_zero);
968 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2, timing->clk_prepare);
969 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3, timing->clk_trail);
970 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4, timing->hs_exit);
971 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5, timing->hs_zero);
972 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6, timing->hs_prepare);
973 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7, timing->hs_trail);
974 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8, timing->hs_rqst);
975 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9, 0x02);
976 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10, 0x04);
977 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11, 0x00);
978 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12,
979 			timing->shared_timings.clk_pre);
980 		dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13,
981 			timing->shared_timings.clk_post);
982 	}
983 
984 	/* DSI lane settings */
985 	dsi_phy_hw_v4_0_lane_settings(phy);
986 
987 	DBG("DSI%d PHY enabled", phy->id);
988 
989 	return 0;
990 }
991 
992 static bool dsi_7nm_set_continuous_clock(struct msm_dsi_phy *phy, bool enable)
993 {
994 	void __iomem *base = phy->base;
995 	u32 data;
996 
997 	data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL1);
998 	if (enable)
999 		data |= BIT(5) | BIT(6);
1000 	else
1001 		data &= ~(BIT(5) | BIT(6));
1002 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL1, data);
1003 
1004 	return enable;
1005 }
1006 
1007 static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
1008 {
1009 	void __iomem *base = phy->base;
1010 	u32 data;
1011 
1012 	DBG("");
1013 
1014 	if (dsi_phy_hw_v4_0_is_pll_on(phy))
1015 		pr_warn("Turning OFF PHY while PLL is on\n");
1016 
1017 	dsi_phy_hw_v4_0_config_lpcdrx(phy, false);
1018 	data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0);
1019 
1020 	/* disable all lanes */
1021 	data &= ~0x1F;
1022 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data);
1023 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, 0);
1024 
1025 	/* Turn off all PHY blocks */
1026 	dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x00);
1027 	/* make sure phy is turned off */
1028 	wmb();
1029 
1030 	DBG("DSI%d PHY disabled", phy->id);
1031 }
1032 
1033 const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
1034 	.has_phy_lane = true,
1035 	.reg_cfg = {
1036 		.num = 1,
1037 		.regs = {
1038 			{"vdds", 36000, 32},
1039 		},
1040 	},
1041 	.ops = {
1042 		.enable = dsi_7nm_phy_enable,
1043 		.disable = dsi_7nm_phy_disable,
1044 		.pll_init = dsi_pll_7nm_init,
1045 		.save_pll_state = dsi_7nm_pll_save_state,
1046 		.restore_pll_state = dsi_7nm_pll_restore_state,
1047 		.set_continuous_clock = dsi_7nm_set_continuous_clock,
1048 	},
1049 	.min_pll_rate = 600000000UL,
1050 #ifdef CONFIG_64BIT
1051 	.max_pll_rate = 5000000000UL,
1052 #else
1053 	.max_pll_rate = ULONG_MAX,
1054 #endif
1055 	.io_start = { 0xae94400, 0xae96400 },
1056 	.num_dsi_phy = 2,
1057 	.quirks = DSI_PHY_7NM_QUIRK_V4_1,
1058 };
1059 
1060 const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
1061 	.has_phy_lane = true,
1062 	.reg_cfg = {
1063 		.num = 1,
1064 		.regs = {
1065 			{"vdds", 36000, 32},
1066 		},
1067 	},
1068 	.ops = {
1069 		.enable = dsi_7nm_phy_enable,
1070 		.disable = dsi_7nm_phy_disable,
1071 		.pll_init = dsi_pll_7nm_init,
1072 		.save_pll_state = dsi_7nm_pll_save_state,
1073 		.restore_pll_state = dsi_7nm_pll_restore_state,
1074 		.set_continuous_clock = dsi_7nm_set_continuous_clock,
1075 	},
1076 	.min_pll_rate = 1000000000UL,
1077 	.max_pll_rate = 3500000000UL,
1078 	.io_start = { 0xae94400, 0xae96400 },
1079 	.num_dsi_phy = 2,
1080 };
1081 
1082 const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = {
1083 	.has_phy_lane = true,
1084 	.reg_cfg = {
1085 		.num = 1,
1086 		.regs = {
1087 			{"vdds", 37550, 0},
1088 		},
1089 	},
1090 	.ops = {
1091 		.enable = dsi_7nm_phy_enable,
1092 		.disable = dsi_7nm_phy_disable,
1093 		.pll_init = dsi_pll_7nm_init,
1094 		.save_pll_state = dsi_7nm_pll_save_state,
1095 		.restore_pll_state = dsi_7nm_pll_restore_state,
1096 	},
1097 	.min_pll_rate = 600000000UL,
1098 #ifdef CONFIG_64BIT
1099 	.max_pll_rate = 5000000000ULL,
1100 #else
1101 	.max_pll_rate = ULONG_MAX,
1102 #endif
1103 	.io_start = { 0xae94400 },
1104 	.num_dsi_phy = 1,
1105 	.quirks = DSI_PHY_7NM_QUIRK_V4_1,
1106 };
1107