1 /* 2 * SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2018, The Linux Foundation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/iopoll.h> 9 10 #include "dsi_phy.h" 11 #include "dsi.xml.h" 12 13 /* 14 * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram 15 * 16 * dsi0_pll_out_div_clk dsi0_pll_bit_clk 17 * | | 18 * | | 19 * +---------+ | +----------+ | +----+ 20 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk 21 * +---------+ | +----------+ | +----+ 22 * | | 23 * | | dsi0_pll_by_2_bit_clk 24 * | | | 25 * | | +----+ | |\ dsi0_pclk_mux 26 * | |--| /2 |--o--| \ | 27 * | | +----+ | \ | +---------+ 28 * | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk 29 * |------------------------------| / +---------+ 30 * | +-----+ | / 31 * -----------| /4? |--o----------|/ 32 * +-----+ | | 33 * | |dsiclk_sel 34 * | 35 * dsi0_pll_post_out_div_clk 36 */ 37 38 #define VCO_REF_CLK_RATE 19200000 39 #define FRAC_BITS 18 40 41 /* Hardware is V4.1 */ 42 #define DSI_PHY_7NM_QUIRK_V4_1 BIT(0) 43 44 struct dsi_pll_config { 45 bool enable_ssc; 46 bool ssc_center; 47 u32 ssc_freq; 48 u32 ssc_offset; 49 u32 ssc_adj_per; 50 51 /* out */ 52 u32 decimal_div_start; 53 u32 frac_div_start; 54 u32 pll_clock_inverters; 55 u32 ssc_stepsize; 56 u32 ssc_div_per; 57 }; 58 59 struct pll_7nm_cached_state { 60 unsigned long vco_rate; 61 u8 bit_clk_div; 62 u8 pix_clk_div; 63 u8 pll_out_div; 64 u8 pll_mux; 65 }; 66 67 struct dsi_pll_7nm { 68 struct clk_hw clk_hw; 69 70 struct msm_dsi_phy *phy; 71 72 u64 vco_current_rate; 73 74 /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */ 75 spinlock_t postdiv_lock; 76 77 struct pll_7nm_cached_state cached_state; 78 79 struct dsi_pll_7nm *slave; 80 }; 81 82 #define to_pll_7nm(x) container_of(x, struct dsi_pll_7nm, clk_hw) 83 84 /* 85 * Global list of private DSI PLL struct pointers. We need this for Dual DSI 86 * mode, where the master PLL's clk_ops needs access the slave's private data 87 */ 88 static struct dsi_pll_7nm *pll_7nm_list[DSI_MAX]; 89 90 static void dsi_pll_setup_config(struct dsi_pll_config *config) 91 { 92 config->ssc_freq = 31500; 93 config->ssc_offset = 4800; 94 config->ssc_adj_per = 2; 95 96 /* TODO: ssc enable */ 97 config->enable_ssc = false; 98 config->ssc_center = 0; 99 } 100 101 static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) 102 { 103 u64 fref = VCO_REF_CLK_RATE; 104 u64 pll_freq; 105 u64 divider; 106 u64 dec, dec_multiple; 107 u32 frac; 108 u64 multiplier; 109 110 pll_freq = pll->vco_current_rate; 111 112 divider = fref * 2; 113 114 multiplier = 1 << FRAC_BITS; 115 dec_multiple = div_u64(pll_freq * multiplier, divider); 116 div_u64_rem(dec_multiple, multiplier, &frac); 117 118 dec = div_u64(dec_multiple, multiplier); 119 120 if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)) 121 config->pll_clock_inverters = 0x28; 122 else if (pll_freq <= 1000000000ULL) 123 config->pll_clock_inverters = 0xa0; 124 else if (pll_freq <= 2500000000ULL) 125 config->pll_clock_inverters = 0x20; 126 else if (pll_freq <= 3020000000ULL) 127 config->pll_clock_inverters = 0x00; 128 else 129 config->pll_clock_inverters = 0x40; 130 131 config->decimal_div_start = dec; 132 config->frac_div_start = frac; 133 } 134 135 #define SSC_CENTER BIT(0) 136 #define SSC_EN BIT(1) 137 138 static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) 139 { 140 u32 ssc_per; 141 u32 ssc_mod; 142 u64 ssc_step_size; 143 u64 frac; 144 145 if (!config->enable_ssc) { 146 DBG("SSC not enabled\n"); 147 return; 148 } 149 150 ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1; 151 ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1); 152 ssc_per -= ssc_mod; 153 154 frac = config->frac_div_start; 155 ssc_step_size = config->decimal_div_start; 156 ssc_step_size *= (1 << FRAC_BITS); 157 ssc_step_size += frac; 158 ssc_step_size *= config->ssc_offset; 159 ssc_step_size *= (config->ssc_adj_per + 1); 160 ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1)); 161 ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000); 162 163 config->ssc_div_per = ssc_per; 164 config->ssc_stepsize = ssc_step_size; 165 166 pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n", 167 config->decimal_div_start, frac, FRAC_BITS); 168 pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n", 169 ssc_per, (u32)ssc_step_size, config->ssc_adj_per); 170 } 171 172 static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) 173 { 174 void __iomem *base = pll->phy->pll_base; 175 176 if (config->enable_ssc) { 177 pr_debug("SSC is enabled\n"); 178 179 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1, 180 config->ssc_stepsize & 0xff); 181 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, 182 config->ssc_stepsize >> 8); 183 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1, 184 config->ssc_div_per & 0xff); 185 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1, 186 config->ssc_div_per >> 8); 187 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1, 188 config->ssc_adj_per & 0xff); 189 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1, 190 config->ssc_adj_per >> 8); 191 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL, 192 SSC_EN | (config->ssc_center ? SSC_CENTER : 0)); 193 } 194 } 195 196 static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) 197 { 198 void __iomem *base = pll->phy->pll_base; 199 u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; 200 201 if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { 202 if (pll->vco_current_rate >= 3100000000ULL) 203 analog_controls_five_1 = 0x03; 204 205 if (pll->vco_current_rate < 1520000000ULL) 206 vco_config_1 = 0x08; 207 else if (pll->vco_current_rate < 2990000000ULL) 208 vco_config_1 = 0x01; 209 } 210 211 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1, 212 analog_controls_five_1); 213 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1); 214 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE, 0x01); 215 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03); 216 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00); 217 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER, 0x00); 218 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e); 219 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40); 220 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba); 221 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c); 222 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_OUTDIV, 0x00); 223 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE, 0x00); 224 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08); 225 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x0a); 226 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1, 0xc0); 227 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x84); 228 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82); 229 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c); 230 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80); 231 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x29); 232 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); 233 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); 234 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 235 pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22); 236 237 if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { 238 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); 239 if (pll->slave) 240 dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); 241 } 242 } 243 244 static void dsi_pll_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) 245 { 246 void __iomem *base = pll->phy->pll_base; 247 248 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12); 249 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1, config->decimal_div_start); 250 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1, 251 config->frac_div_start & 0xff); 252 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1, 253 (config->frac_div_start & 0xff00) >> 8); 254 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1, 255 (config->frac_div_start & 0x30000) >> 16); 256 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40); 257 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); 258 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO: 0x00 for CPHY */ 259 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, config->pll_clock_inverters); 260 } 261 262 static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, 263 unsigned long parent_rate) 264 { 265 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); 266 struct dsi_pll_config config; 267 268 DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->phy->id, rate, 269 parent_rate); 270 271 pll_7nm->vco_current_rate = rate; 272 273 dsi_pll_setup_config(&config); 274 275 dsi_pll_calc_dec_frac(pll_7nm, &config); 276 277 dsi_pll_calc_ssc(pll_7nm, &config); 278 279 dsi_pll_commit(pll_7nm, &config); 280 281 dsi_pll_config_hzindep_reg(pll_7nm); 282 283 dsi_pll_ssc_commit(pll_7nm, &config); 284 285 /* flush, ensure all register writes are done*/ 286 wmb(); 287 288 return 0; 289 } 290 291 static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll) 292 { 293 int rc; 294 u32 status = 0; 295 u32 const delay_us = 100; 296 u32 const timeout_us = 5000; 297 298 rc = readl_poll_timeout_atomic(pll->phy->pll_base + 299 REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE, 300 status, 301 ((status & BIT(0)) > 0), 302 delay_us, 303 timeout_us); 304 if (rc) 305 pr_err("DSI PLL(%d) lock failed, status=0x%08x\n", 306 pll->phy->id, status); 307 308 return rc; 309 } 310 311 static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll) 312 { 313 u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); 314 315 dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0); 316 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5)); 317 ndelay(250); 318 } 319 320 static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll) 321 { 322 u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); 323 324 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5)); 325 dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0); 326 ndelay(250); 327 } 328 329 static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll) 330 { 331 u32 data; 332 333 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); 334 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5)); 335 } 336 337 static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll) 338 { 339 u32 data; 340 341 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04); 342 343 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); 344 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, 345 data | BIT(5) | BIT(4)); 346 } 347 348 static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll) 349 { 350 /* 351 * Reset the PHY digital domain. This would be needed when 352 * coming out of a CX or analog rail power collapse while 353 * ensuring that the pads maintain LP00 or LP11 state 354 */ 355 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0)); 356 wmb(); /* Ensure that the reset is deasserted */ 357 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0); 358 wmb(); /* Ensure that the reset is deasserted */ 359 } 360 361 static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw) 362 { 363 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); 364 int rc; 365 366 dsi_pll_enable_pll_bias(pll_7nm); 367 if (pll_7nm->slave) 368 dsi_pll_enable_pll_bias(pll_7nm->slave); 369 370 /* Start PLL */ 371 dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01); 372 373 /* 374 * ensure all PLL configurations are written prior to checking 375 * for PLL lock. 376 */ 377 wmb(); 378 379 /* Check for PLL lock */ 380 rc = dsi_pll_7nm_lock_status(pll_7nm); 381 if (rc) { 382 pr_err("PLL(%d) lock failed\n", pll_7nm->phy->id); 383 goto error; 384 } 385 386 pll_7nm->phy->pll_on = true; 387 388 /* 389 * assert power on reset for PHY digital in case the PLL is 390 * enabled after CX of analog domain power collapse. This needs 391 * to be done before enabling the global clk. 392 */ 393 dsi_pll_phy_dig_reset(pll_7nm); 394 if (pll_7nm->slave) 395 dsi_pll_phy_dig_reset(pll_7nm->slave); 396 397 dsi_pll_enable_global_clk(pll_7nm); 398 if (pll_7nm->slave) 399 dsi_pll_enable_global_clk(pll_7nm->slave); 400 401 error: 402 return rc; 403 } 404 405 static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll) 406 { 407 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0); 408 dsi_pll_disable_pll_bias(pll); 409 } 410 411 static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw) 412 { 413 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); 414 415 /* 416 * To avoid any stray glitches while abruptly powering down the PLL 417 * make sure to gate the clock using the clock enable bit before 418 * powering down the PLL 419 */ 420 dsi_pll_disable_global_clk(pll_7nm); 421 dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0); 422 dsi_pll_disable_sub(pll_7nm); 423 if (pll_7nm->slave) { 424 dsi_pll_disable_global_clk(pll_7nm->slave); 425 dsi_pll_disable_sub(pll_7nm->slave); 426 } 427 /* flush, ensure all register writes are done */ 428 wmb(); 429 pll_7nm->phy->pll_on = false; 430 } 431 432 static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, 433 unsigned long parent_rate) 434 { 435 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); 436 void __iomem *base = pll_7nm->phy->pll_base; 437 u64 ref_clk = VCO_REF_CLK_RATE; 438 u64 vco_rate = 0x0; 439 u64 multiplier; 440 u32 frac; 441 u32 dec; 442 u64 pll_freq, tmp64; 443 444 dec = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1); 445 dec &= 0xff; 446 447 frac = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1); 448 frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) & 449 0xff) << 8); 450 frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) & 451 0x3) << 16); 452 453 /* 454 * TODO: 455 * 1. Assumes prescaler is disabled 456 */ 457 multiplier = 1 << FRAC_BITS; 458 pll_freq = dec * (ref_clk * 2); 459 tmp64 = (ref_clk * 2 * frac); 460 pll_freq += div_u64(tmp64, multiplier); 461 462 vco_rate = pll_freq; 463 pll_7nm->vco_current_rate = vco_rate; 464 465 DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x", 466 pll_7nm->phy->id, (unsigned long)vco_rate, dec, frac); 467 468 return (unsigned long)vco_rate; 469 } 470 471 static long dsi_pll_7nm_clk_round_rate(struct clk_hw *hw, 472 unsigned long rate, unsigned long *parent_rate) 473 { 474 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); 475 476 if (rate < pll_7nm->phy->cfg->min_pll_rate) 477 return pll_7nm->phy->cfg->min_pll_rate; 478 else if (rate > pll_7nm->phy->cfg->max_pll_rate) 479 return pll_7nm->phy->cfg->max_pll_rate; 480 else 481 return rate; 482 } 483 484 static const struct clk_ops clk_ops_dsi_pll_7nm_vco = { 485 .round_rate = dsi_pll_7nm_clk_round_rate, 486 .set_rate = dsi_pll_7nm_vco_set_rate, 487 .recalc_rate = dsi_pll_7nm_vco_recalc_rate, 488 .prepare = dsi_pll_7nm_vco_prepare, 489 .unprepare = dsi_pll_7nm_vco_unprepare, 490 }; 491 492 /* 493 * PLL Callbacks 494 */ 495 496 static void dsi_7nm_pll_save_state(struct msm_dsi_phy *phy) 497 { 498 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); 499 struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; 500 void __iomem *phy_base = pll_7nm->phy->base; 501 u32 cmn_clk_cfg0, cmn_clk_cfg1; 502 503 cached->pll_out_div = dsi_phy_read(pll_7nm->phy->pll_base + 504 REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); 505 cached->pll_out_div &= 0x3; 506 507 cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0); 508 cached->bit_clk_div = cmn_clk_cfg0 & 0xf; 509 cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4; 510 511 cmn_clk_cfg1 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); 512 cached->pll_mux = cmn_clk_cfg1 & 0x3; 513 514 DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", 515 pll_7nm->phy->id, cached->pll_out_div, cached->bit_clk_div, 516 cached->pix_clk_div, cached->pll_mux); 517 } 518 519 static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy) 520 { 521 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); 522 struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; 523 void __iomem *phy_base = pll_7nm->phy->base; 524 u32 val; 525 int ret; 526 527 val = dsi_phy_read(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); 528 val &= ~0x3; 529 val |= cached->pll_out_div; 530 dsi_phy_write(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val); 531 532 dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0, 533 cached->bit_clk_div | (cached->pix_clk_div << 4)); 534 535 val = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); 536 val &= ~0x3; 537 val |= cached->pll_mux; 538 dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val); 539 540 ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw, 541 pll_7nm->vco_current_rate, 542 VCO_REF_CLK_RATE); 543 if (ret) { 544 DRM_DEV_ERROR(&pll_7nm->phy->pdev->dev, 545 "restore vco rate failed. ret=%d\n", ret); 546 return ret; 547 } 548 549 DBG("DSI PLL%d", pll_7nm->phy->id); 550 551 return 0; 552 } 553 554 static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) 555 { 556 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); 557 void __iomem *base = phy->base; 558 u32 data = 0x0; /* internal PLL */ 559 560 DBG("DSI PLL%d", pll_7nm->phy->id); 561 562 switch (phy->usecase) { 563 case MSM_DSI_PHY_STANDALONE: 564 break; 565 case MSM_DSI_PHY_MASTER: 566 pll_7nm->slave = pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX]; 567 break; 568 case MSM_DSI_PHY_SLAVE: 569 data = 0x1; /* external PLL */ 570 break; 571 default: 572 return -EINVAL; 573 } 574 575 /* set PLL src */ 576 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2)); 577 578 return 0; 579 } 580 581 /* 582 * The post dividers and mux clocks are created using the standard divider and 583 * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux 584 * state to follow the master PLL's divider/mux state. Therefore, we don't 585 * require special clock ops that also configure the slave PLL registers 586 */ 587 static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provided_clocks) 588 { 589 char clk_name[32], parent[32], vco_name[32]; 590 char parent2[32], parent3[32], parent4[32]; 591 struct clk_init_data vco_init = { 592 .parent_names = (const char *[]){ "bi_tcxo" }, 593 .num_parents = 1, 594 .name = vco_name, 595 .flags = CLK_IGNORE_UNUSED, 596 .ops = &clk_ops_dsi_pll_7nm_vco, 597 }; 598 struct device *dev = &pll_7nm->phy->pdev->dev; 599 struct clk_hw *hw; 600 int ret; 601 602 DBG("DSI%d", pll_7nm->phy->id); 603 604 snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->phy->id); 605 pll_7nm->clk_hw.init = &vco_init; 606 607 ret = devm_clk_hw_register(dev, &pll_7nm->clk_hw); 608 if (ret) 609 return ret; 610 611 snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id); 612 snprintf(parent, 32, "dsi%dvco_clk", pll_7nm->phy->id); 613 614 hw = devm_clk_hw_register_divider(dev, clk_name, 615 parent, CLK_SET_RATE_PARENT, 616 pll_7nm->phy->pll_base + 617 REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, 618 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL); 619 if (IS_ERR(hw)) { 620 ret = PTR_ERR(hw); 621 goto fail; 622 } 623 624 snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id); 625 snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id); 626 627 /* BIT CLK: DIV_CTRL_3_0 */ 628 hw = devm_clk_hw_register_divider(dev, clk_name, parent, 629 CLK_SET_RATE_PARENT, 630 pll_7nm->phy->base + 631 REG_DSI_7nm_PHY_CMN_CLK_CFG0, 632 0, 4, CLK_DIVIDER_ONE_BASED, 633 &pll_7nm->postdiv_lock); 634 if (IS_ERR(hw)) { 635 ret = PTR_ERR(hw); 636 goto fail; 637 } 638 639 snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_7nm->phy->id); 640 snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id); 641 642 /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */ 643 hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 644 CLK_SET_RATE_PARENT, 1, 8); 645 if (IS_ERR(hw)) { 646 ret = PTR_ERR(hw); 647 goto fail; 648 } 649 650 provided_clocks[DSI_BYTE_PLL_CLK] = hw; 651 652 snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id); 653 snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id); 654 655 hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 656 0, 1, 2); 657 if (IS_ERR(hw)) { 658 ret = PTR_ERR(hw); 659 goto fail; 660 } 661 662 snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id); 663 snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id); 664 665 hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 666 0, 1, 4); 667 if (IS_ERR(hw)) { 668 ret = PTR_ERR(hw); 669 goto fail; 670 } 671 672 snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->phy->id); 673 snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id); 674 snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id); 675 snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id); 676 snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id); 677 678 hw = devm_clk_hw_register_mux(dev, clk_name, 679 ((const char *[]){ 680 parent, parent2, parent3, parent4 681 }), 4, 0, pll_7nm->phy->base + 682 REG_DSI_7nm_PHY_CMN_CLK_CFG1, 683 0, 2, 0, NULL); 684 if (IS_ERR(hw)) { 685 ret = PTR_ERR(hw); 686 goto fail; 687 } 688 689 snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->phy->id); 690 snprintf(parent, 32, "dsi%d_pclk_mux", pll_7nm->phy->id); 691 692 /* PIX CLK DIV : DIV_CTRL_7_4*/ 693 hw = devm_clk_hw_register_divider(dev, clk_name, parent, 694 0, pll_7nm->phy->base + 695 REG_DSI_7nm_PHY_CMN_CLK_CFG0, 696 4, 4, CLK_DIVIDER_ONE_BASED, 697 &pll_7nm->postdiv_lock); 698 if (IS_ERR(hw)) { 699 ret = PTR_ERR(hw); 700 goto fail; 701 } 702 703 provided_clocks[DSI_PIXEL_PLL_CLK] = hw; 704 705 return 0; 706 707 fail: 708 709 return ret; 710 } 711 712 static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) 713 { 714 struct platform_device *pdev = phy->pdev; 715 struct dsi_pll_7nm *pll_7nm; 716 int ret; 717 718 pll_7nm = devm_kzalloc(&pdev->dev, sizeof(*pll_7nm), GFP_KERNEL); 719 if (!pll_7nm) 720 return -ENOMEM; 721 722 DBG("DSI PLL%d", phy->id); 723 724 pll_7nm_list[phy->id] = pll_7nm; 725 726 spin_lock_init(&pll_7nm->postdiv_lock); 727 728 pll_7nm->phy = phy; 729 730 ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws); 731 if (ret) { 732 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); 733 return ret; 734 } 735 736 phy->vco_hw = &pll_7nm->clk_hw; 737 738 /* TODO: Remove this when we have proper display handover support */ 739 msm_dsi_phy_pll_save_state(phy); 740 741 return 0; 742 } 743 744 static int dsi_phy_hw_v4_0_is_pll_on(struct msm_dsi_phy *phy) 745 { 746 void __iomem *base = phy->base; 747 u32 data = 0; 748 749 data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL); 750 mb(); /* make sure read happened */ 751 752 return (data & BIT(0)); 753 } 754 755 static void dsi_phy_hw_v4_0_config_lpcdrx(struct msm_dsi_phy *phy, bool enable) 756 { 757 void __iomem *lane_base = phy->lane_base; 758 int phy_lane_0 = 0; /* TODO: Support all lane swap configs */ 759 760 /* 761 * LPRX and CDRX need to enabled only for physical data lane 762 * corresponding to the logical data lane 0 763 */ 764 if (enable) 765 dsi_phy_write(lane_base + 766 REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0x3); 767 else 768 dsi_phy_write(lane_base + 769 REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0); 770 } 771 772 static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy) 773 { 774 int i; 775 const u8 tx_dctrl_0[] = { 0x00, 0x00, 0x00, 0x04, 0x01 }; 776 const u8 tx_dctrl_1[] = { 0x40, 0x40, 0x40, 0x46, 0x41 }; 777 const u8 *tx_dctrl = tx_dctrl_0; 778 void __iomem *lane_base = phy->lane_base; 779 780 if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) 781 tx_dctrl = tx_dctrl_1; 782 783 /* Strength ctrl settings */ 784 for (i = 0; i < 5; i++) { 785 /* 786 * Disable LPRX and CDRX for all lanes. And later on, it will 787 * be only enabled for the physical data lane corresponding 788 * to the logical data lane 0 789 */ 790 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(i), 0); 791 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_PIN_SWAP(i), 0x0); 792 } 793 794 dsi_phy_hw_v4_0_config_lpcdrx(phy, true); 795 796 /* other settings */ 797 for (i = 0; i < 5; i++) { 798 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG0(i), 0x0); 799 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG1(i), 0x0); 800 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG2(i), i == 4 ? 0x8a : 0xa); 801 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_TX_DCTRL(i), tx_dctrl[i]); 802 } 803 } 804 805 static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, 806 struct msm_dsi_phy_clk_request *clk_req) 807 { 808 int ret; 809 u32 status; 810 u32 const delay_us = 5; 811 u32 const timeout_us = 1000; 812 struct msm_dsi_dphy_timing *timing = &phy->timing; 813 void __iomem *base = phy->base; 814 bool less_than_1500_mhz; 815 u32 vreg_ctrl_0, glbl_str_swi_cal_sel_ctrl, glbl_hstx_str_ctrl_0; 816 u32 glbl_rescode_top_ctrl, glbl_rescode_bot_ctrl; 817 u32 data; 818 819 DBG(""); 820 821 if (msm_dsi_dphy_timing_calc_v4(timing, clk_req)) { 822 DRM_DEV_ERROR(&phy->pdev->dev, 823 "%s: D-PHY timing calculation failed\n", __func__); 824 return -EINVAL; 825 } 826 827 if (dsi_phy_hw_v4_0_is_pll_on(phy)) 828 pr_warn("PLL turned on before configuring PHY\n"); 829 830 /* wait for REFGEN READY */ 831 ret = readl_poll_timeout_atomic(base + REG_DSI_7nm_PHY_CMN_PHY_STATUS, 832 status, (status & BIT(0)), 833 delay_us, timeout_us); 834 if (ret) { 835 pr_err("Ref gen not ready. Aborting\n"); 836 return -EINVAL; 837 } 838 839 /* TODO: CPHY enable path (this is for DPHY only) */ 840 841 /* Alter PHY configurations if data rate less than 1.5GHZ*/ 842 less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000); 843 844 if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { 845 vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; 846 glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; 847 glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; 848 glbl_str_swi_cal_sel_ctrl = 0x00; 849 glbl_hstx_str_ctrl_0 = 0x88; 850 } else { 851 vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; 852 glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00; 853 glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; 854 glbl_rescode_top_ctrl = 0x03; 855 glbl_rescode_bot_ctrl = 0x3c; 856 } 857 858 /* de-assert digital and pll power down */ 859 data = BIT(6) | BIT(5); 860 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data); 861 862 /* Assert PLL core reset */ 863 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x00); 864 865 /* turn off resync FIFO */ 866 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0x00); 867 868 /* program CMN_CTRL_4 for minor_ver 2 chipsets*/ 869 data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0); 870 data = data & (0xf0); 871 if (data == 0x20) 872 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_4, 0x04); 873 874 /* Configure PHY lane swap (TODO: we need to calculate this) */ 875 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG0, 0x21); 876 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG1, 0x84); 877 878 /* Enable LDO */ 879 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_0, vreg_ctrl_0); 880 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_1, 0x5c); 881 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x00); 882 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL, 883 glbl_str_swi_cal_sel_ctrl); 884 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0, 885 glbl_hstx_str_ctrl_0); 886 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0, 0x00); 887 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL, 888 glbl_rescode_top_ctrl); 889 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL, 890 glbl_rescode_bot_ctrl); 891 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL, 0x55); 892 893 /* Remove power down from all blocks */ 894 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x7f); 895 896 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, 0x1f); 897 898 /* Select full-rate mode */ 899 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_2, 0x40); 900 901 ret = dsi_7nm_set_usecase(phy); 902 if (ret) { 903 DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n", 904 __func__, ret); 905 return ret; 906 } 907 908 /* DSI PHY timings */ 909 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0, 0x00); 910 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1, timing->clk_zero); 911 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2, timing->clk_prepare); 912 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3, timing->clk_trail); 913 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4, timing->hs_exit); 914 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5, timing->hs_zero); 915 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6, timing->hs_prepare); 916 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7, timing->hs_trail); 917 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8, timing->hs_rqst); 918 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9, 0x02); 919 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10, 0x04); 920 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11, 0x00); 921 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12, 922 timing->shared_timings.clk_pre); 923 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13, 924 timing->shared_timings.clk_post); 925 926 /* DSI lane settings */ 927 dsi_phy_hw_v4_0_lane_settings(phy); 928 929 DBG("DSI%d PHY enabled", phy->id); 930 931 return 0; 932 } 933 934 static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy) 935 { 936 void __iomem *base = phy->base; 937 u32 data; 938 939 DBG(""); 940 941 if (dsi_phy_hw_v4_0_is_pll_on(phy)) 942 pr_warn("Turning OFF PHY while PLL is on\n"); 943 944 dsi_phy_hw_v4_0_config_lpcdrx(phy, false); 945 data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0); 946 947 /* disable all lanes */ 948 data &= ~0x1F; 949 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data); 950 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, 0); 951 952 /* Turn off all PHY blocks */ 953 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x00); 954 /* make sure phy is turned off */ 955 wmb(); 956 957 DBG("DSI%d PHY disabled", phy->id); 958 } 959 960 const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { 961 .has_phy_lane = true, 962 .reg_cfg = { 963 .num = 1, 964 .regs = { 965 {"vdds", 36000, 32}, 966 }, 967 }, 968 .ops = { 969 .enable = dsi_7nm_phy_enable, 970 .disable = dsi_7nm_phy_disable, 971 .pll_init = dsi_pll_7nm_init, 972 .save_pll_state = dsi_7nm_pll_save_state, 973 .restore_pll_state = dsi_7nm_pll_restore_state, 974 }, 975 .min_pll_rate = 600000000UL, 976 .max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : ULONG_MAX, 977 .io_start = { 0xae94400, 0xae96400 }, 978 .num_dsi_phy = 2, 979 .quirks = DSI_PHY_7NM_QUIRK_V4_1, 980 }; 981 982 const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { 983 .has_phy_lane = true, 984 .reg_cfg = { 985 .num = 1, 986 .regs = { 987 {"vdds", 36000, 32}, 988 }, 989 }, 990 .ops = { 991 .enable = dsi_7nm_phy_enable, 992 .disable = dsi_7nm_phy_disable, 993 .pll_init = dsi_pll_7nm_init, 994 .save_pll_state = dsi_7nm_pll_save_state, 995 .restore_pll_state = dsi_7nm_pll_restore_state, 996 }, 997 .min_pll_rate = 1000000000UL, 998 .max_pll_rate = 3500000000UL, 999 .io_start = { 0xae94400, 0xae96400 }, 1000 .num_dsi_phy = 2, 1001 }; 1002