1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include "dsi_phy.h" 7 #include "dsi.xml.h" 8 9 static void dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy, 10 struct msm_dsi_dphy_timing *timing) 11 { 12 void __iomem *base = phy->base; 13 14 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_0, 15 DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); 16 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_1, 17 DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); 18 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_2, 19 DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); 20 if (timing->clk_zero & BIT(8)) 21 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_3, 22 DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8); 23 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_4, 24 DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); 25 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_5, 26 DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); 27 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_6, 28 DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); 29 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_7, 30 DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail)); 31 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_8, 32 DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); 33 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_9, 34 DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) | 35 DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure)); 36 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_10, 37 DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get)); 38 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_11, 39 DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0)); 40 } 41 42 static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) 43 { 44 void __iomem *base = phy->reg_base; 45 46 if (!enable) { 47 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0); 48 return; 49 } 50 51 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0); 52 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 1); 53 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0); 54 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0); 55 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x3); 56 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x9); 57 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x7); 58 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20); 59 } 60 61 static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, 62 struct msm_dsi_phy_clk_request *clk_req) 63 { 64 struct msm_dsi_dphy_timing *timing = &phy->timing; 65 int i; 66 void __iomem *base = phy->base; 67 68 DBG(""); 69 70 if (msm_dsi_dphy_timing_calc(timing, clk_req)) { 71 DRM_DEV_ERROR(&phy->pdev->dev, 72 "%s: D-PHY timing calculation failed\n", __func__); 73 return -EINVAL; 74 } 75 76 dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_0, 0xff); 77 78 dsi_28nm_phy_regulator_ctrl(phy, true); 79 80 dsi_phy_write(base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x00); 81 82 dsi_28nm_dphy_set_timing(phy, timing); 83 84 dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_1, 0x00); 85 dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f); 86 87 dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_1, 0x6); 88 89 for (i = 0; i < 4; i++) { 90 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_0(i), 0); 91 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_1(i), 0); 92 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_2(i), 0); 93 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_3(i), 0); 94 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(i), 0); 95 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i), 0); 96 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i), 0); 97 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i), 0x1); 98 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i), 0x97); 99 } 100 101 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_4, 0); 102 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_1, 0xc0); 103 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR0, 0x1); 104 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR1, 0xbb); 105 106 dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f); 107 108 msm_dsi_phy_set_src_pll(phy, src_pll_id, 109 REG_DSI_28nm_PHY_GLBL_TEST_CTRL, 110 DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL); 111 112 return 0; 113 } 114 115 static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy) 116 { 117 dsi_phy_write(phy->base + REG_DSI_28nm_PHY_CTRL_0, 0); 118 dsi_28nm_phy_regulator_ctrl(phy, false); 119 120 /* 121 * Wait for the registers writes to complete in order to 122 * ensure that the phy is completely disabled 123 */ 124 wmb(); 125 } 126 127 const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { 128 .type = MSM_DSI_PHY_28NM_HPM, 129 .src_pll_truthtable = { {true, true}, {false, true} }, 130 .reg_cfg = { 131 .num = 1, 132 .regs = { 133 {"vddio", 100000, 100}, 134 }, 135 }, 136 .ops = { 137 .enable = dsi_28nm_phy_enable, 138 .disable = dsi_28nm_phy_disable, 139 .init = msm_dsi_phy_init_common, 140 }, 141 .io_start = { 0xfd922b00, 0xfd923100 }, 142 .num_dsi_phy = 2, 143 }; 144 145 const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { 146 .type = MSM_DSI_PHY_28NM_LP, 147 .src_pll_truthtable = { {true, true}, {true, true} }, 148 .reg_cfg = { 149 .num = 1, 150 .regs = { 151 {"vddio", 100000, 100}, /* 1.8 V */ 152 }, 153 }, 154 .ops = { 155 .enable = dsi_28nm_phy_enable, 156 .disable = dsi_28nm_phy_disable, 157 .init = msm_dsi_phy_init_common, 158 }, 159 .io_start = { 0x1a98500 }, 160 .num_dsi_phy = 1, 161 }; 162 163