1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4  */
5 
6 #include "dsi_phy.h"
7 #include "dsi.xml.h"
8 
9 static void dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy,
10 		struct msm_dsi_dphy_timing *timing)
11 {
12 	void __iomem *base = phy->base;
13 
14 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_0,
15 		DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero));
16 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_1,
17 		DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail));
18 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_2,
19 		DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare));
20 	if (timing->clk_zero & BIT(8))
21 		dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_3,
22 			DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8);
23 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_4,
24 		DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit));
25 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_5,
26 		DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero));
27 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_6,
28 		DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare));
29 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_7,
30 		DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail));
31 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_8,
32 		DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst));
33 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_9,
34 		DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
35 		DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure));
36 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_10,
37 		DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get));
38 	dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_11,
39 		DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0));
40 }
41 
42 static void dsi_28nm_phy_regulator_enable_dcdc(struct msm_dsi_phy *phy)
43 {
44 	void __iomem *base = phy->reg_base;
45 
46 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0);
47 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 1);
48 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0);
49 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0);
50 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x3);
51 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x9);
52 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x7);
53 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20);
54 	dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x00);
55 }
56 
57 static void dsi_28nm_phy_regulator_enable_ldo(struct msm_dsi_phy *phy)
58 {
59 	void __iomem *base = phy->reg_base;
60 
61 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0);
62 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0);
63 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0x7);
64 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0);
65 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x1);
66 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x1);
67 	dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20);
68 
69 	if (phy->cfg->type == MSM_DSI_PHY_28NM_LP)
70 		dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x05);
71 	else
72 		dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x0d);
73 }
74 
75 static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
76 {
77 	if (!enable) {
78 		dsi_phy_write(phy->reg_base +
79 			      REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0);
80 		return;
81 	}
82 
83 	if (phy->regulator_ldo_mode)
84 		dsi_28nm_phy_regulator_enable_ldo(phy);
85 	else
86 		dsi_28nm_phy_regulator_enable_dcdc(phy);
87 }
88 
89 static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
90 				struct msm_dsi_phy_clk_request *clk_req)
91 {
92 	struct msm_dsi_dphy_timing *timing = &phy->timing;
93 	int i;
94 	void __iomem *base = phy->base;
95 
96 	DBG("");
97 
98 	if (msm_dsi_dphy_timing_calc(timing, clk_req)) {
99 		DRM_DEV_ERROR(&phy->pdev->dev,
100 			"%s: D-PHY timing calculation failed\n", __func__);
101 		return -EINVAL;
102 	}
103 
104 	dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_0, 0xff);
105 
106 	dsi_28nm_phy_regulator_ctrl(phy, true);
107 
108 	dsi_28nm_dphy_set_timing(phy, timing);
109 
110 	dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_1, 0x00);
111 	dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f);
112 
113 	dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_1, 0x6);
114 
115 	for (i = 0; i < 4; i++) {
116 		dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_0(i), 0);
117 		dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_1(i), 0);
118 		dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_2(i), 0);
119 		dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_3(i), 0);
120 		dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(i), 0);
121 		dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i), 0);
122 		dsi_phy_write(base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i), 0);
123 		dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i), 0x1);
124 		dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i), 0x97);
125 	}
126 
127 	dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_4, 0);
128 	dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_1, 0xc0);
129 	dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR0, 0x1);
130 	dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR1, 0xbb);
131 
132 	dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f);
133 
134 	msm_dsi_phy_set_src_pll(phy, src_pll_id,
135 				REG_DSI_28nm_PHY_GLBL_TEST_CTRL,
136 				DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL);
137 
138 	return 0;
139 }
140 
141 static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
142 {
143 	dsi_phy_write(phy->base + REG_DSI_28nm_PHY_CTRL_0, 0);
144 	dsi_28nm_phy_regulator_ctrl(phy, false);
145 
146 	/*
147 	 * Wait for the registers writes to complete in order to
148 	 * ensure that the phy is completely disabled
149 	 */
150 	wmb();
151 }
152 
153 const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
154 	.type = MSM_DSI_PHY_28NM_HPM,
155 	.src_pll_truthtable = { {true, true}, {false, true} },
156 	.reg_cfg = {
157 		.num = 1,
158 		.regs = {
159 			{"vddio", 100000, 100},
160 		},
161 	},
162 	.ops = {
163 		.enable = dsi_28nm_phy_enable,
164 		.disable = dsi_28nm_phy_disable,
165 		.init = msm_dsi_phy_init_common,
166 	},
167 	.io_start = { 0xfd922b00, 0xfd923100 },
168 	.num_dsi_phy = 2,
169 };
170 
171 const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
172 	.type = MSM_DSI_PHY_28NM_HPM,
173 	.src_pll_truthtable = { {true, true}, {false, true} },
174 	.reg_cfg = {
175 		.num = 1,
176 		.regs = {
177 			{"vddio", 100000, 100},
178 		},
179 	},
180 	.ops = {
181 		.enable = dsi_28nm_phy_enable,
182 		.disable = dsi_28nm_phy_disable,
183 		.init = msm_dsi_phy_init_common,
184 	},
185 	.io_start = { 0x1a94400, 0x1a96400 },
186 	.num_dsi_phy = 2,
187 };
188 
189 const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
190 	.type = MSM_DSI_PHY_28NM_LP,
191 	.src_pll_truthtable = { {true, true}, {true, true} },
192 	.reg_cfg = {
193 		.num = 1,
194 		.regs = {
195 			{"vddio", 100000, 100},	/* 1.8 V */
196 		},
197 	},
198 	.ops = {
199 		.enable = dsi_28nm_phy_enable,
200 		.disable = dsi_28nm_phy_disable,
201 		.init = msm_dsi_phy_init_common,
202 	},
203 	.io_start = { 0x1a98500 },
204 	.num_dsi_phy = 1,
205 };
206 
207