1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include "dsi_phy.h" 7 #include "dsi.xml.h" 8 9 static void dsi_20nm_dphy_set_timing(struct msm_dsi_phy *phy, 10 struct msm_dsi_dphy_timing *timing) 11 { 12 void __iomem *base = phy->base; 13 14 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0, 15 DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); 16 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1, 17 DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); 18 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2, 19 DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); 20 if (timing->clk_zero & BIT(8)) 21 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3, 22 DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8); 23 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4, 24 DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); 25 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5, 26 DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); 27 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6, 28 DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); 29 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7, 30 DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail)); 31 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_8, 32 DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); 33 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_9, 34 DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) | 35 DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure)); 36 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_10, 37 DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get)); 38 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_11, 39 DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0)); 40 } 41 42 static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) 43 { 44 void __iomem *base = phy->reg_base; 45 46 if (!enable) { 47 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0); 48 return; 49 } 50 51 if (phy->regulator_ldo_mode) { 52 dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x1d); 53 return; 54 } 55 56 /* non LDO mode */ 57 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_1, 0x03); 58 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_2, 0x03); 59 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_3, 0x00); 60 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_4, 0x20); 61 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0x01); 62 dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x00); 63 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0, 0x03); 64 } 65 66 static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, 67 struct msm_dsi_phy_clk_request *clk_req) 68 { 69 struct msm_dsi_dphy_timing *timing = &phy->timing; 70 int i; 71 void __iomem *base = phy->base; 72 u32 cfg_4[4] = {0x20, 0x40, 0x20, 0x00}; 73 u32 val; 74 75 DBG(""); 76 77 if (msm_dsi_dphy_timing_calc(timing, clk_req)) { 78 DRM_DEV_ERROR(&phy->pdev->dev, 79 "%s: D-PHY timing calculation failed\n", __func__); 80 return -EINVAL; 81 } 82 83 dsi_20nm_phy_regulator_ctrl(phy, true); 84 85 dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff); 86 87 val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL); 88 if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_STANDALONE) 89 val |= DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL; 90 else 91 val &= ~DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL; 92 dsi_phy_write(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL, val); 93 94 for (i = 0; i < 4; i++) { 95 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i), 96 (i >> 1) * 0x40); 97 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_0(i), 0x01); 98 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_1(i), 0x46); 99 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_0(i), 0x02); 100 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_1(i), 0xa0); 101 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_4(i), cfg_4[i]); 102 } 103 104 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_3, 0x80); 105 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR0, 0x01); 106 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR1, 0x46); 107 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_0, 0x00); 108 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_1, 0xa0); 109 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_2, 0x00); 110 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_4, 0x00); 111 112 dsi_20nm_dphy_set_timing(phy, timing); 113 114 dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_1, 0x00); 115 116 dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_1, 0x06); 117 118 /* make sure everything is written before enable */ 119 wmb(); 120 dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_0, 0x7f); 121 122 return 0; 123 } 124 125 static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy) 126 { 127 dsi_phy_write(phy->base + REG_DSI_20nm_PHY_CTRL_0, 0); 128 dsi_20nm_phy_regulator_ctrl(phy, false); 129 } 130 131 const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = { 132 .has_phy_regulator = true, 133 .reg_cfg = { 134 .num = 2, 135 .regs = { 136 {"vddio", 100000, 100}, /* 1.8 V */ 137 {"vcca", 10000, 100}, /* 1.0 V */ 138 }, 139 }, 140 .ops = { 141 .enable = dsi_20nm_phy_enable, 142 .disable = dsi_20nm_phy_disable, 143 }, 144 .io_start = { 0xfd998500, 0xfd9a0500 }, 145 .num_dsi_phy = 2, 146 }; 147 148