1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016, The Linux Foundation. All rights reserved. 4 */ 5 6 #include "dsi_phy.h" 7 #include "dsi.xml.h" 8 9 #define PHY_14NM_CKLN_IDX 4 10 11 static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy, 12 struct msm_dsi_dphy_timing *timing, 13 int lane_idx) 14 { 15 void __iomem *base = phy->lane_base; 16 bool clk_ln = (lane_idx == PHY_14NM_CKLN_IDX); 17 u32 zero = clk_ln ? timing->clk_zero : timing->hs_zero; 18 u32 prepare = clk_ln ? timing->clk_prepare : timing->hs_prepare; 19 u32 trail = clk_ln ? timing->clk_trail : timing->hs_trail; 20 u32 rqst = clk_ln ? timing->hs_rqst_ckln : timing->hs_rqst; 21 u32 prep_dly = clk_ln ? timing->hs_prep_dly_ckln : timing->hs_prep_dly; 22 u32 halfbyte_en = clk_ln ? timing->hs_halfbyte_en_ckln : 23 timing->hs_halfbyte_en; 24 25 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(lane_idx), 26 DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); 27 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(lane_idx), 28 DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(zero)); 29 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(lane_idx), 30 DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(prepare)); 31 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(lane_idx), 32 DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(trail)); 33 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(lane_idx), 34 DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(rqst)); 35 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG0(lane_idx), 36 DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(prep_dly)); 37 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG1(lane_idx), 38 halfbyte_en ? DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN : 0); 39 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(lane_idx), 40 DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(timing->ta_go) | 41 DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(timing->ta_sure)); 42 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(lane_idx), 43 DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(timing->ta_get)); 44 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(lane_idx), 45 DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(0xa0)); 46 } 47 48 static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, 49 struct msm_dsi_phy_clk_request *clk_req) 50 { 51 struct msm_dsi_dphy_timing *timing = &phy->timing; 52 u32 data; 53 int i; 54 int ret; 55 void __iomem *base = phy->base; 56 void __iomem *lane_base = phy->lane_base; 57 58 if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) { 59 DRM_DEV_ERROR(&phy->pdev->dev, 60 "%s: D-PHY timing calculation failed\n", __func__); 61 return -EINVAL; 62 } 63 64 data = 0x1c; 65 if (phy->usecase != MSM_DSI_PHY_STANDALONE) 66 data |= DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(32); 67 dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data); 68 69 dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0x1); 70 71 /* 4 data lanes + 1 clk lane configuration */ 72 for (i = 0; i < 5; i++) { 73 dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_VREG_CNTRL(i), 74 0x1d); 75 76 dsi_phy_write(lane_base + 77 REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(i), 0xff); 78 dsi_phy_write(lane_base + 79 REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(i), 80 (i == PHY_14NM_CKLN_IDX) ? 0x00 : 0x06); 81 82 dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG3(i), 83 (i == PHY_14NM_CKLN_IDX) ? 0x8f : 0x0f); 84 dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG2(i), 0x10); 85 dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_DATAPATH(i), 86 0); 87 dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_STR(i), 88 0x88); 89 90 dsi_14nm_dphy_set_timing(phy, timing, i); 91 } 92 93 /* Make sure PLL is not start */ 94 dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0x00); 95 96 wmb(); /* make sure everything is written before reset and enable */ 97 98 /* reset digital block */ 99 dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x80); 100 wmb(); /* ensure reset is asserted */ 101 udelay(100); 102 dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00); 103 104 msm_dsi_phy_set_src_pll(phy, src_pll_id, 105 REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 106 DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL); 107 108 ret = msm_dsi_pll_set_usecase(phy->pll, phy->usecase); 109 if (ret) { 110 DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n", 111 __func__, ret); 112 return ret; 113 } 114 115 /* Remove power down from PLL and all lanes */ 116 dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0xff); 117 118 return 0; 119 } 120 121 static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy) 122 { 123 dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0); 124 dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0); 125 126 /* ensure that the phy is completely disabled */ 127 wmb(); 128 } 129 130 static int dsi_14nm_phy_init(struct msm_dsi_phy *phy) 131 { 132 struct platform_device *pdev = phy->pdev; 133 134 phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", 135 "DSI_PHY_LANE"); 136 if (IS_ERR(phy->lane_base)) { 137 DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n", 138 __func__); 139 return -ENOMEM; 140 } 141 142 return 0; 143 } 144 145 const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { 146 .type = MSM_DSI_PHY_14NM, 147 .src_pll_truthtable = { {false, false}, {true, false} }, 148 .reg_cfg = { 149 .num = 1, 150 .regs = { 151 {"vcca", 17000, 32}, 152 }, 153 }, 154 .ops = { 155 .enable = dsi_14nm_phy_enable, 156 .disable = dsi_14nm_phy_disable, 157 .init = dsi_14nm_phy_init, 158 }, 159 .io_start = { 0x994400, 0x996400 }, 160 .num_dsi_phy = 2, 161 }; 162