1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 10 #include "dsi_phy.h" 11 #include "dsi.xml.h" 12 13 #define PHY_14NM_CKLN_IDX 4 14 15 /* 16 * DSI PLL 14nm - clock diagram (eg: DSI0): 17 * 18 * dsi0n1_postdiv_clk 19 * | 20 * | 21 * +----+ | +----+ 22 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte 23 * +----+ | +----+ 24 * | dsi0n1_postdivby2_clk 25 * | +----+ | 26 * o---| /2 |--o--|\ 27 * | +----+ | \ +----+ 28 * | | |--| n2 |-- dsi0pll 29 * o--------------| / +----+ 30 * |/ 31 */ 32 33 #define POLL_MAX_READS 15 34 #define POLL_TIMEOUT_US 1000 35 36 #define VCO_REF_CLK_RATE 19200000 37 #define VCO_MIN_RATE 1300000000UL 38 #define VCO_MAX_RATE 2600000000UL 39 40 struct dsi_pll_config { 41 u64 vco_current_rate; 42 43 u32 ssc_en; /* SSC enable/disable */ 44 45 /* fixed params */ 46 u32 plllock_cnt; 47 u32 ssc_center; 48 u32 ssc_adj_period; 49 u32 ssc_spread; 50 u32 ssc_freq; 51 52 /* calculated */ 53 u32 dec_start; 54 u32 div_frac_start; 55 u32 ssc_period; 56 u32 ssc_step_size; 57 u32 plllock_cmp; 58 u32 pll_vco_div_ref; 59 u32 pll_vco_count; 60 u32 pll_kvco_div_ref; 61 u32 pll_kvco_count; 62 }; 63 64 struct pll_14nm_cached_state { 65 unsigned long vco_rate; 66 u8 n2postdiv; 67 u8 n1postdiv; 68 }; 69 70 struct dsi_pll_14nm { 71 struct clk_hw clk_hw; 72 73 struct msm_dsi_phy *phy; 74 75 /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */ 76 spinlock_t postdiv_lock; 77 78 struct pll_14nm_cached_state cached_state; 79 80 struct dsi_pll_14nm *slave; 81 }; 82 83 #define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, clk_hw) 84 85 /* 86 * Private struct for N1/N2 post-divider clocks. These clocks are similar to 87 * the generic clk_divider class of clocks. The only difference is that it 88 * also sets the slave DSI PLL's post-dividers if in Dual DSI mode 89 */ 90 struct dsi_pll_14nm_postdiv { 91 struct clk_hw hw; 92 93 /* divider params */ 94 u8 shift; 95 u8 width; 96 u8 flags; /* same flags as used by clk_divider struct */ 97 98 struct dsi_pll_14nm *pll; 99 }; 100 101 #define to_pll_14nm_postdiv(_hw) container_of(_hw, struct dsi_pll_14nm_postdiv, hw) 102 103 /* 104 * Global list of private DSI PLL struct pointers. We need this for Dual DSI 105 * mode, where the master PLL's clk_ops needs access the slave's private data 106 */ 107 static struct dsi_pll_14nm *pll_14nm_list[DSI_MAX]; 108 109 static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm, 110 u32 nb_tries, u32 timeout_us) 111 { 112 bool pll_locked = false; 113 void __iomem *base = pll_14nm->phy->pll_base; 114 u32 tries, val; 115 116 tries = nb_tries; 117 while (tries--) { 118 val = dsi_phy_read(base + 119 REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); 120 pll_locked = !!(val & BIT(5)); 121 122 if (pll_locked) 123 break; 124 125 udelay(timeout_us); 126 } 127 128 if (!pll_locked) { 129 tries = nb_tries; 130 while (tries--) { 131 val = dsi_phy_read(base + 132 REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); 133 pll_locked = !!(val & BIT(0)); 134 135 if (pll_locked) 136 break; 137 138 udelay(timeout_us); 139 } 140 } 141 142 DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* "); 143 144 return pll_locked; 145 } 146 147 static void dsi_pll_14nm_config_init(struct dsi_pll_config *pconf) 148 { 149 /* fixed input */ 150 pconf->plllock_cnt = 1; 151 152 /* 153 * SSC is enabled by default. We might need DT props for configuring 154 * some SSC params like PPM and center/down spread etc. 155 */ 156 pconf->ssc_en = 1; 157 pconf->ssc_center = 0; /* down spread by default */ 158 pconf->ssc_spread = 5; /* PPM / 1000 */ 159 pconf->ssc_freq = 31500; /* default recommended */ 160 pconf->ssc_adj_period = 37; 161 } 162 163 #define CEIL(x, y) (((x) + ((y) - 1)) / (y)) 164 165 static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf) 166 { 167 u32 period, ssc_period; 168 u32 ref, rem; 169 u64 step_size; 170 171 DBG("vco=%lld ref=%d", pconf->vco_current_rate, VCO_REF_CLK_RATE); 172 173 ssc_period = pconf->ssc_freq / 500; 174 period = (u32)VCO_REF_CLK_RATE / 1000; 175 ssc_period = CEIL(period, ssc_period); 176 ssc_period -= 1; 177 pconf->ssc_period = ssc_period; 178 179 DBG("ssc freq=%d spread=%d period=%d", pconf->ssc_freq, 180 pconf->ssc_spread, pconf->ssc_period); 181 182 step_size = (u32)pconf->vco_current_rate; 183 ref = VCO_REF_CLK_RATE; 184 ref /= 1000; 185 step_size = div_u64(step_size, ref); 186 step_size <<= 20; 187 step_size = div_u64(step_size, 1000); 188 step_size *= pconf->ssc_spread; 189 step_size = div_u64(step_size, 1000); 190 step_size *= (pconf->ssc_adj_period + 1); 191 192 rem = 0; 193 step_size = div_u64_rem(step_size, ssc_period + 1, &rem); 194 if (rem) 195 step_size++; 196 197 DBG("step_size=%lld", step_size); 198 199 step_size &= 0x0ffff; /* take lower 16 bits */ 200 201 pconf->ssc_step_size = step_size; 202 } 203 204 static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf) 205 { 206 u64 multiplier = BIT(20); 207 u64 dec_start_multiple, dec_start, pll_comp_val; 208 u32 duration, div_frac_start; 209 u64 vco_clk_rate = pconf->vco_current_rate; 210 u64 fref = VCO_REF_CLK_RATE; 211 212 DBG("vco_clk_rate=%lld ref_clk_rate=%lld", vco_clk_rate, fref); 213 214 dec_start_multiple = div_u64(vco_clk_rate * multiplier, fref); 215 div_u64_rem(dec_start_multiple, multiplier, &div_frac_start); 216 217 dec_start = div_u64(dec_start_multiple, multiplier); 218 219 pconf->dec_start = (u32)dec_start; 220 pconf->div_frac_start = div_frac_start; 221 222 if (pconf->plllock_cnt == 0) 223 duration = 1024; 224 else if (pconf->plllock_cnt == 1) 225 duration = 256; 226 else if (pconf->plllock_cnt == 2) 227 duration = 128; 228 else 229 duration = 32; 230 231 pll_comp_val = duration * dec_start_multiple; 232 pll_comp_val = div_u64(pll_comp_val, multiplier); 233 do_div(pll_comp_val, 10); 234 235 pconf->plllock_cmp = (u32)pll_comp_val; 236 } 237 238 static u32 pll_14nm_kvco_slop(u32 vrate) 239 { 240 u32 slop = 0; 241 242 if (vrate > VCO_MIN_RATE && vrate <= 1800000000UL) 243 slop = 600; 244 else if (vrate > 1800000000UL && vrate < 2300000000UL) 245 slop = 400; 246 else if (vrate > 2300000000UL && vrate < VCO_MAX_RATE) 247 slop = 280; 248 249 return slop; 250 } 251 252 static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf) 253 { 254 u64 vco_clk_rate = pconf->vco_current_rate; 255 u64 fref = VCO_REF_CLK_RATE; 256 u32 vco_measure_time = 5; 257 u32 kvco_measure_time = 5; 258 u64 data; 259 u32 cnt; 260 261 data = fref * vco_measure_time; 262 do_div(data, 1000000); 263 data &= 0x03ff; /* 10 bits */ 264 data -= 2; 265 pconf->pll_vco_div_ref = data; 266 267 data = div_u64(vco_clk_rate, 1000000); /* unit is Mhz */ 268 data *= vco_measure_time; 269 do_div(data, 10); 270 pconf->pll_vco_count = data; 271 272 data = fref * kvco_measure_time; 273 do_div(data, 1000000); 274 data &= 0x03ff; /* 10 bits */ 275 data -= 1; 276 pconf->pll_kvco_div_ref = data; 277 278 cnt = pll_14nm_kvco_slop(vco_clk_rate); 279 cnt *= 2; 280 cnt /= 100; 281 cnt *= kvco_measure_time; 282 pconf->pll_kvco_count = cnt; 283 } 284 285 static void pll_db_commit_ssc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf) 286 { 287 void __iomem *base = pll->phy->pll_base; 288 u8 data; 289 290 data = pconf->ssc_adj_period; 291 data &= 0x0ff; 292 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data); 293 data = (pconf->ssc_adj_period >> 8); 294 data &= 0x03; 295 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data); 296 297 data = pconf->ssc_period; 298 data &= 0x0ff; 299 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data); 300 data = (pconf->ssc_period >> 8); 301 data &= 0x0ff; 302 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data); 303 304 data = pconf->ssc_step_size; 305 data &= 0x0ff; 306 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data); 307 data = (pconf->ssc_step_size >> 8); 308 data &= 0x0ff; 309 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data); 310 311 data = (pconf->ssc_center & 0x01); 312 data <<= 1; 313 data |= 0x01; /* enable */ 314 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data); 315 316 wmb(); /* make sure register committed */ 317 } 318 319 static void pll_db_commit_common(struct dsi_pll_14nm *pll, 320 struct dsi_pll_config *pconf) 321 { 322 void __iomem *base = pll->phy->pll_base; 323 u8 data; 324 325 /* confgiure the non frequency dependent pll registers */ 326 data = 0; 327 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data); 328 329 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, 1); 330 331 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, 48); 332 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, 4 << 3); /* bandgap_timer */ 333 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, 5); /* pll_wakeup_timer */ 334 335 data = pconf->pll_vco_div_ref & 0xff; 336 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data); 337 data = (pconf->pll_vco_div_ref >> 8) & 0x3; 338 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data); 339 340 data = pconf->pll_kvco_div_ref & 0xff; 341 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data); 342 data = (pconf->pll_kvco_div_ref >> 8) & 0x3; 343 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data); 344 345 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, 16); 346 347 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, 4); 348 349 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, 4); 350 351 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, 1 << 3 | 1); 352 353 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, 0 << 3 | 0); 354 355 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, 0 << 3 | 0); 356 357 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, 4 << 3 | 4); 358 359 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, 1 << 4 | 11); 360 361 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, 7); 362 363 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, 1 << 4 | 2); 364 } 365 366 static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm) 367 { 368 void __iomem *cmn_base = pll_14nm->phy->base; 369 370 /* de assert pll start and apply pll sw reset */ 371 372 /* stop pll */ 373 dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0); 374 375 /* pll sw reset */ 376 dsi_phy_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10); 377 wmb(); /* make sure register committed */ 378 379 dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0); 380 wmb(); /* make sure register committed */ 381 } 382 383 static void pll_db_commit_14nm(struct dsi_pll_14nm *pll, 384 struct dsi_pll_config *pconf) 385 { 386 void __iomem *base = pll->phy->pll_base; 387 void __iomem *cmn_base = pll->phy->base; 388 u8 data; 389 390 DBG("DSI%d PLL", pll->phy->id); 391 392 dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, 0x3c); 393 394 pll_db_commit_common(pll, pconf); 395 396 pll_14nm_software_reset(pll); 397 398 /* Use the /2 path in Mux */ 399 dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, 1); 400 401 data = 0xff; /* data, clk, pll normal operation */ 402 dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data); 403 404 /* configure the frequency dependent pll registers */ 405 data = pconf->dec_start; 406 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data); 407 408 data = pconf->div_frac_start & 0xff; 409 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data); 410 data = (pconf->div_frac_start >> 8) & 0xff; 411 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data); 412 data = (pconf->div_frac_start >> 16) & 0xf; 413 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data); 414 415 data = pconf->plllock_cmp & 0xff; 416 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data); 417 418 data = (pconf->plllock_cmp >> 8) & 0xff; 419 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data); 420 421 data = (pconf->plllock_cmp >> 16) & 0x3; 422 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data); 423 424 data = pconf->plllock_cnt << 1 | 0 << 3; /* plllock_rng */ 425 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data); 426 427 data = pconf->pll_vco_count & 0xff; 428 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data); 429 data = (pconf->pll_vco_count >> 8) & 0xff; 430 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data); 431 432 data = pconf->pll_kvco_count & 0xff; 433 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data); 434 data = (pconf->pll_kvco_count >> 8) & 0x3; 435 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data); 436 437 /* 438 * High nibble configures the post divider internal to the VCO. It's 439 * fixed to divide by 1 for now. 440 * 441 * 0: divided by 1 442 * 1: divided by 2 443 * 2: divided by 4 444 * 3: divided by 8 445 */ 446 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, 0 << 4 | 3); 447 448 if (pconf->ssc_en) 449 pll_db_commit_ssc(pll, pconf); 450 451 wmb(); /* make sure register committed */ 452 } 453 454 /* 455 * VCO clock Callbacks 456 */ 457 static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, 458 unsigned long parent_rate) 459 { 460 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); 461 struct dsi_pll_config conf; 462 463 DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->phy->id, rate, 464 parent_rate); 465 466 dsi_pll_14nm_config_init(&conf); 467 conf.vco_current_rate = rate; 468 469 pll_14nm_dec_frac_calc(pll_14nm, &conf); 470 471 if (conf.ssc_en) 472 pll_14nm_ssc_calc(pll_14nm, &conf); 473 474 pll_14nm_calc_vco_count(pll_14nm, &conf); 475 476 /* commit the slave DSI PLL registers if we're master. Note that we 477 * don't lock the slave PLL. We just ensure that the PLL/PHY registers 478 * of the master and slave are identical 479 */ 480 if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) { 481 struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; 482 483 pll_db_commit_14nm(pll_14nm_slave, &conf); 484 } 485 486 pll_db_commit_14nm(pll_14nm, &conf); 487 488 return 0; 489 } 490 491 static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw, 492 unsigned long parent_rate) 493 { 494 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); 495 void __iomem *base = pll_14nm->phy->pll_base; 496 u64 vco_rate, multiplier = BIT(20); 497 u32 div_frac_start; 498 u32 dec_start; 499 u64 ref_clk = parent_rate; 500 501 dec_start = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DEC_START); 502 dec_start &= 0x0ff; 503 504 DBG("dec_start = %x", dec_start); 505 506 div_frac_start = (dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3) 507 & 0xf) << 16; 508 div_frac_start |= (dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2) 509 & 0xff) << 8; 510 div_frac_start |= dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1) 511 & 0xff; 512 513 DBG("div_frac_start = %x", div_frac_start); 514 515 vco_rate = ref_clk * dec_start; 516 517 vco_rate += ((ref_clk * div_frac_start) / multiplier); 518 519 /* 520 * Recalculating the rate from dec_start and frac_start doesn't end up 521 * the rate we originally set. Convert the freq to KHz, round it up and 522 * convert it back to MHz. 523 */ 524 vco_rate = DIV_ROUND_UP_ULL(vco_rate, 1000) * 1000; 525 526 DBG("returning vco rate = %lu", (unsigned long)vco_rate); 527 528 return (unsigned long)vco_rate; 529 } 530 531 static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw) 532 { 533 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); 534 void __iomem *base = pll_14nm->phy->pll_base; 535 void __iomem *cmn_base = pll_14nm->phy->base; 536 bool locked; 537 538 DBG(""); 539 540 if (unlikely(pll_14nm->phy->pll_on)) 541 return 0; 542 543 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10); 544 dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1); 545 546 locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS, 547 POLL_TIMEOUT_US); 548 549 if (unlikely(!locked)) { 550 DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev, "DSI PLL lock failed\n"); 551 return -EINVAL; 552 } 553 554 DBG("DSI PLL lock success"); 555 pll_14nm->phy->pll_on = true; 556 557 return 0; 558 } 559 560 static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw) 561 { 562 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); 563 void __iomem *cmn_base = pll_14nm->phy->base; 564 565 DBG(""); 566 567 if (unlikely(!pll_14nm->phy->pll_on)) 568 return; 569 570 dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0); 571 572 pll_14nm->phy->pll_on = false; 573 } 574 575 static long dsi_pll_14nm_clk_round_rate(struct clk_hw *hw, 576 unsigned long rate, unsigned long *parent_rate) 577 { 578 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); 579 580 if (rate < pll_14nm->phy->cfg->min_pll_rate) 581 return pll_14nm->phy->cfg->min_pll_rate; 582 else if (rate > pll_14nm->phy->cfg->max_pll_rate) 583 return pll_14nm->phy->cfg->max_pll_rate; 584 else 585 return rate; 586 } 587 588 static const struct clk_ops clk_ops_dsi_pll_14nm_vco = { 589 .round_rate = dsi_pll_14nm_clk_round_rate, 590 .set_rate = dsi_pll_14nm_vco_set_rate, 591 .recalc_rate = dsi_pll_14nm_vco_recalc_rate, 592 .prepare = dsi_pll_14nm_vco_prepare, 593 .unprepare = dsi_pll_14nm_vco_unprepare, 594 }; 595 596 /* 597 * N1 and N2 post-divider clock callbacks 598 */ 599 #define div_mask(width) ((1 << (width)) - 1) 600 static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw, 601 unsigned long parent_rate) 602 { 603 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); 604 struct dsi_pll_14nm *pll_14nm = postdiv->pll; 605 void __iomem *base = pll_14nm->phy->base; 606 u8 shift = postdiv->shift; 607 u8 width = postdiv->width; 608 u32 val; 609 610 DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, parent_rate); 611 612 val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift; 613 val &= div_mask(width); 614 615 return divider_recalc_rate(hw, parent_rate, val, NULL, 616 postdiv->flags, width); 617 } 618 619 static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw, 620 unsigned long rate, 621 unsigned long *prate) 622 { 623 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); 624 struct dsi_pll_14nm *pll_14nm = postdiv->pll; 625 626 DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, rate); 627 628 return divider_round_rate(hw, rate, prate, NULL, 629 postdiv->width, 630 postdiv->flags); 631 } 632 633 static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 634 unsigned long parent_rate) 635 { 636 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); 637 struct dsi_pll_14nm *pll_14nm = postdiv->pll; 638 void __iomem *base = pll_14nm->phy->base; 639 spinlock_t *lock = &pll_14nm->postdiv_lock; 640 u8 shift = postdiv->shift; 641 u8 width = postdiv->width; 642 unsigned int value; 643 unsigned long flags = 0; 644 u32 val; 645 646 DBG("DSI%d PLL parent rate=%lu parent rate %lu", pll_14nm->phy->id, rate, 647 parent_rate); 648 649 value = divider_get_val(rate, parent_rate, NULL, postdiv->width, 650 postdiv->flags); 651 652 spin_lock_irqsave(lock, flags); 653 654 val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); 655 val &= ~(div_mask(width) << shift); 656 657 val |= value << shift; 658 dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); 659 660 /* If we're master in dual DSI mode, then the slave PLL's post-dividers 661 * follow the master's post dividers 662 */ 663 if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) { 664 struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; 665 void __iomem *slave_base = pll_14nm_slave->phy->base; 666 667 dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); 668 } 669 670 spin_unlock_irqrestore(lock, flags); 671 672 return 0; 673 } 674 675 static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = { 676 .recalc_rate = dsi_pll_14nm_postdiv_recalc_rate, 677 .round_rate = dsi_pll_14nm_postdiv_round_rate, 678 .set_rate = dsi_pll_14nm_postdiv_set_rate, 679 }; 680 681 /* 682 * PLL Callbacks 683 */ 684 685 static void dsi_14nm_pll_save_state(struct msm_dsi_phy *phy) 686 { 687 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw); 688 struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; 689 void __iomem *cmn_base = pll_14nm->phy->base; 690 u32 data; 691 692 data = dsi_phy_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); 693 694 cached_state->n1postdiv = data & 0xf; 695 cached_state->n2postdiv = (data >> 4) & 0xf; 696 697 DBG("DSI%d PLL save state %x %x", pll_14nm->phy->id, 698 cached_state->n1postdiv, cached_state->n2postdiv); 699 700 cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw); 701 } 702 703 static int dsi_14nm_pll_restore_state(struct msm_dsi_phy *phy) 704 { 705 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw); 706 struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; 707 void __iomem *cmn_base = pll_14nm->phy->base; 708 u32 data; 709 int ret; 710 711 ret = dsi_pll_14nm_vco_set_rate(phy->vco_hw, 712 cached_state->vco_rate, 0); 713 if (ret) { 714 DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev, 715 "restore vco rate failed. ret=%d\n", ret); 716 return ret; 717 } 718 719 data = cached_state->n1postdiv | (cached_state->n2postdiv << 4); 720 721 DBG("DSI%d PLL restore state %x %x", pll_14nm->phy->id, 722 cached_state->n1postdiv, cached_state->n2postdiv); 723 724 dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); 725 726 /* also restore post-dividers for slave DSI PLL */ 727 if (phy->usecase == MSM_DSI_PHY_MASTER) { 728 struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; 729 void __iomem *slave_base = pll_14nm_slave->phy->base; 730 731 dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); 732 } 733 734 return 0; 735 } 736 737 static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy) 738 { 739 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw); 740 void __iomem *base = phy->pll_base; 741 u32 clkbuflr_en, bandgap = 0; 742 743 switch (phy->usecase) { 744 case MSM_DSI_PHY_STANDALONE: 745 clkbuflr_en = 0x1; 746 break; 747 case MSM_DSI_PHY_MASTER: 748 clkbuflr_en = 0x3; 749 pll_14nm->slave = pll_14nm_list[(pll_14nm->phy->id + 1) % DSI_MAX]; 750 break; 751 case MSM_DSI_PHY_SLAVE: 752 clkbuflr_en = 0x0; 753 bandgap = 0x3; 754 break; 755 default: 756 return -EINVAL; 757 } 758 759 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN, clkbuflr_en); 760 if (bandgap) 761 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap); 762 763 return 0; 764 } 765 766 static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm, 767 const char *name, 768 const char *parent_name, 769 unsigned long flags, 770 u8 shift) 771 { 772 struct dsi_pll_14nm_postdiv *pll_postdiv; 773 struct device *dev = &pll_14nm->phy->pdev->dev; 774 struct clk_init_data postdiv_init = { 775 .parent_names = (const char *[]) { parent_name }, 776 .num_parents = 1, 777 .name = name, 778 .flags = flags, 779 .ops = &clk_ops_dsi_pll_14nm_postdiv, 780 }; 781 int ret; 782 783 pll_postdiv = devm_kzalloc(dev, sizeof(*pll_postdiv), GFP_KERNEL); 784 if (!pll_postdiv) 785 return ERR_PTR(-ENOMEM); 786 787 pll_postdiv->pll = pll_14nm; 788 pll_postdiv->shift = shift; 789 /* both N1 and N2 postdividers are 4 bits wide */ 790 pll_postdiv->width = 4; 791 /* range of each divider is from 1 to 15 */ 792 pll_postdiv->flags = CLK_DIVIDER_ONE_BASED; 793 pll_postdiv->hw.init = &postdiv_init; 794 795 ret = devm_clk_hw_register(dev, &pll_postdiv->hw); 796 if (ret) 797 return ERR_PTR(ret); 798 799 return &pll_postdiv->hw; 800 } 801 802 static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **provided_clocks) 803 { 804 char clk_name[32], parent[32], vco_name[32]; 805 struct clk_init_data vco_init = { 806 .parent_names = (const char *[]){ "xo" }, 807 .num_parents = 1, 808 .name = vco_name, 809 .flags = CLK_IGNORE_UNUSED, 810 .ops = &clk_ops_dsi_pll_14nm_vco, 811 }; 812 struct device *dev = &pll_14nm->phy->pdev->dev; 813 struct clk_hw *hw; 814 int ret; 815 816 DBG("DSI%d", pll_14nm->phy->id); 817 818 snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->phy->id); 819 pll_14nm->clk_hw.init = &vco_init; 820 821 ret = devm_clk_hw_register(dev, &pll_14nm->clk_hw); 822 if (ret) 823 return ret; 824 825 snprintf(clk_name, 32, "dsi%dn1_postdiv_clk", pll_14nm->phy->id); 826 snprintf(parent, 32, "dsi%dvco_clk", pll_14nm->phy->id); 827 828 /* N1 postdiv, bits 0-3 in REG_DSI_14nm_PHY_CMN_CLK_CFG0 */ 829 hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent, 830 CLK_SET_RATE_PARENT, 0); 831 if (IS_ERR(hw)) 832 return PTR_ERR(hw); 833 834 snprintf(clk_name, 32, "dsi%dpllbyte", pll_14nm->phy->id); 835 snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->phy->id); 836 837 /* DSI Byte clock = VCO_CLK / N1 / 8 */ 838 hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 839 CLK_SET_RATE_PARENT, 1, 8); 840 if (IS_ERR(hw)) 841 return PTR_ERR(hw); 842 843 provided_clocks[DSI_BYTE_PLL_CLK] = hw; 844 845 snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->phy->id); 846 snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->phy->id); 847 848 /* 849 * Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider 850 * on the way. Don't let it set parent. 851 */ 852 hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2); 853 if (IS_ERR(hw)) 854 return PTR_ERR(hw); 855 856 snprintf(clk_name, 32, "dsi%dpll", pll_14nm->phy->id); 857 snprintf(parent, 32, "dsi%dn1_postdivby2_clk", pll_14nm->phy->id); 858 859 /* DSI pixel clock = VCO_CLK / N1 / 2 / N2 860 * This is the output of N2 post-divider, bits 4-7 in 861 * REG_DSI_14nm_PHY_CMN_CLK_CFG0. Don't let it set parent. 862 */ 863 hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent, 0, 4); 864 if (IS_ERR(hw)) 865 return PTR_ERR(hw); 866 867 provided_clocks[DSI_PIXEL_PLL_CLK] = hw; 868 869 return 0; 870 } 871 872 static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) 873 { 874 struct platform_device *pdev = phy->pdev; 875 struct dsi_pll_14nm *pll_14nm; 876 int ret; 877 878 if (!pdev) 879 return -ENODEV; 880 881 pll_14nm = devm_kzalloc(&pdev->dev, sizeof(*pll_14nm), GFP_KERNEL); 882 if (!pll_14nm) 883 return -ENOMEM; 884 885 DBG("PLL%d", phy->id); 886 887 pll_14nm_list[phy->id] = pll_14nm; 888 889 spin_lock_init(&pll_14nm->postdiv_lock); 890 891 pll_14nm->phy = phy; 892 893 ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws); 894 if (ret) { 895 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); 896 return ret; 897 } 898 899 phy->vco_hw = &pll_14nm->clk_hw; 900 901 return 0; 902 } 903 904 static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy, 905 struct msm_dsi_dphy_timing *timing, 906 int lane_idx) 907 { 908 void __iomem *base = phy->lane_base; 909 bool clk_ln = (lane_idx == PHY_14NM_CKLN_IDX); 910 u32 zero = clk_ln ? timing->clk_zero : timing->hs_zero; 911 u32 prepare = clk_ln ? timing->clk_prepare : timing->hs_prepare; 912 u32 trail = clk_ln ? timing->clk_trail : timing->hs_trail; 913 u32 rqst = clk_ln ? timing->hs_rqst_ckln : timing->hs_rqst; 914 u32 prep_dly = clk_ln ? timing->hs_prep_dly_ckln : timing->hs_prep_dly; 915 u32 halfbyte_en = clk_ln ? timing->hs_halfbyte_en_ckln : 916 timing->hs_halfbyte_en; 917 918 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(lane_idx), 919 DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); 920 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(lane_idx), 921 DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(zero)); 922 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(lane_idx), 923 DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(prepare)); 924 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(lane_idx), 925 DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(trail)); 926 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(lane_idx), 927 DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(rqst)); 928 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG0(lane_idx), 929 DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(prep_dly)); 930 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG1(lane_idx), 931 halfbyte_en ? DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN : 0); 932 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(lane_idx), 933 DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(timing->ta_go) | 934 DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(timing->ta_sure)); 935 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(lane_idx), 936 DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(timing->ta_get)); 937 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(lane_idx), 938 DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(0xa0)); 939 } 940 941 static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, 942 struct msm_dsi_phy_clk_request *clk_req) 943 { 944 struct msm_dsi_dphy_timing *timing = &phy->timing; 945 u32 data; 946 int i; 947 int ret; 948 void __iomem *base = phy->base; 949 void __iomem *lane_base = phy->lane_base; 950 u32 glbl_test_ctrl; 951 952 if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) { 953 DRM_DEV_ERROR(&phy->pdev->dev, 954 "%s: D-PHY timing calculation failed\n", __func__); 955 return -EINVAL; 956 } 957 958 data = 0x1c; 959 if (phy->usecase != MSM_DSI_PHY_STANDALONE) 960 data |= DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(32); 961 dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data); 962 963 dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0x1); 964 965 /* 4 data lanes + 1 clk lane configuration */ 966 for (i = 0; i < 5; i++) { 967 dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_VREG_CNTRL(i), 968 0x1d); 969 970 dsi_phy_write(lane_base + 971 REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(i), 0xff); 972 dsi_phy_write(lane_base + 973 REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(i), 974 (i == PHY_14NM_CKLN_IDX) ? 0x00 : 0x06); 975 976 dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG3(i), 977 (i == PHY_14NM_CKLN_IDX) ? 0x8f : 0x0f); 978 dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG2(i), 0x10); 979 dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_DATAPATH(i), 980 0); 981 dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_STR(i), 982 0x88); 983 984 dsi_14nm_dphy_set_timing(phy, timing, i); 985 } 986 987 /* Make sure PLL is not start */ 988 dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0x00); 989 990 wmb(); /* make sure everything is written before reset and enable */ 991 992 /* reset digital block */ 993 dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x80); 994 wmb(); /* ensure reset is asserted */ 995 udelay(100); 996 dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00); 997 998 glbl_test_ctrl = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL); 999 if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_SLAVE) 1000 glbl_test_ctrl |= DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL; 1001 else 1002 glbl_test_ctrl &= ~DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL; 1003 dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, glbl_test_ctrl); 1004 ret = dsi_14nm_set_usecase(phy); 1005 if (ret) { 1006 DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n", 1007 __func__, ret); 1008 return ret; 1009 } 1010 1011 /* Remove power down from PLL and all lanes */ 1012 dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0xff); 1013 1014 return 0; 1015 } 1016 1017 static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy) 1018 { 1019 dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0); 1020 dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0); 1021 1022 /* ensure that the phy is completely disabled */ 1023 wmb(); 1024 } 1025 1026 const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { 1027 .has_phy_lane = true, 1028 .reg_cfg = { 1029 .num = 1, 1030 .regs = { 1031 {"vcca", 17000, 32}, 1032 }, 1033 }, 1034 .ops = { 1035 .enable = dsi_14nm_phy_enable, 1036 .disable = dsi_14nm_phy_disable, 1037 .pll_init = dsi_pll_14nm_init, 1038 .save_pll_state = dsi_14nm_pll_save_state, 1039 .restore_pll_state = dsi_14nm_pll_restore_state, 1040 }, 1041 .min_pll_rate = VCO_MIN_RATE, 1042 .max_pll_rate = VCO_MAX_RATE, 1043 .io_start = { 0x994400, 0x996400 }, 1044 .num_dsi_phy = 2, 1045 }; 1046 1047 const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { 1048 .has_phy_lane = true, 1049 .reg_cfg = { 1050 .num = 1, 1051 .regs = { 1052 {"vcca", 17000, 32}, 1053 }, 1054 }, 1055 .ops = { 1056 .enable = dsi_14nm_phy_enable, 1057 .disable = dsi_14nm_phy_disable, 1058 .pll_init = dsi_pll_14nm_init, 1059 .save_pll_state = dsi_14nm_pll_save_state, 1060 .restore_pll_state = dsi_14nm_pll_restore_state, 1061 }, 1062 .min_pll_rate = VCO_MIN_RATE, 1063 .max_pll_rate = VCO_MAX_RATE, 1064 .io_start = { 0xc994400, 0xc996000 }, 1065 .num_dsi_phy = 2, 1066 }; 1067