1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2016, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/delay.h>
9 
10 #include "dsi_phy.h"
11 #include "dsi.xml.h"
12 #include "dsi_phy_14nm.xml.h"
13 
14 #define PHY_14NM_CKLN_IDX	4
15 
16 /*
17  * DSI PLL 14nm - clock diagram (eg: DSI0):
18  *
19  *         dsi0n1_postdiv_clk
20  *                         |
21  *                         |
22  *                 +----+  |  +----+
23  *  dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
24  *                 +----+  |  +----+
25  *                         |           dsi0n1_postdivby2_clk
26  *                         |   +----+  |
27  *                         o---| /2 |--o--|\
28  *                         |   +----+     | \   +----+
29  *                         |              |  |--| n2 |-- dsi0pll
30  *                         o--------------| /   +----+
31  *                                        |/
32  */
33 
34 #define POLL_MAX_READS			15
35 #define POLL_TIMEOUT_US			1000
36 
37 #define VCO_REF_CLK_RATE		19200000
38 #define VCO_MIN_RATE			1300000000UL
39 #define VCO_MAX_RATE			2600000000UL
40 
41 struct dsi_pll_config {
42 	u64 vco_current_rate;
43 
44 	u32 ssc_en;	/* SSC enable/disable */
45 
46 	/* fixed params */
47 	u32 plllock_cnt;
48 	u32 ssc_center;
49 	u32 ssc_adj_period;
50 	u32 ssc_spread;
51 	u32 ssc_freq;
52 
53 	/* calculated */
54 	u32 dec_start;
55 	u32 div_frac_start;
56 	u32 ssc_period;
57 	u32 ssc_step_size;
58 	u32 plllock_cmp;
59 	u32 pll_vco_div_ref;
60 	u32 pll_vco_count;
61 	u32 pll_kvco_div_ref;
62 	u32 pll_kvco_count;
63 };
64 
65 struct pll_14nm_cached_state {
66 	unsigned long vco_rate;
67 	u8 n2postdiv;
68 	u8 n1postdiv;
69 };
70 
71 struct dsi_pll_14nm {
72 	struct clk_hw clk_hw;
73 
74 	struct msm_dsi_phy *phy;
75 
76 	/* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
77 	spinlock_t postdiv_lock;
78 
79 	struct pll_14nm_cached_state cached_state;
80 
81 	struct dsi_pll_14nm *slave;
82 };
83 
84 #define to_pll_14nm(x)	container_of(x, struct dsi_pll_14nm, clk_hw)
85 
86 /*
87  * Private struct for N1/N2 post-divider clocks. These clocks are similar to
88  * the generic clk_divider class of clocks. The only difference is that it
89  * also sets the slave DSI PLL's post-dividers if in bonded DSI mode
90  */
91 struct dsi_pll_14nm_postdiv {
92 	struct clk_hw hw;
93 
94 	/* divider params */
95 	u8 shift;
96 	u8 width;
97 	u8 flags; /* same flags as used by clk_divider struct */
98 
99 	struct dsi_pll_14nm *pll;
100 };
101 
102 #define to_pll_14nm_postdiv(_hw) container_of(_hw, struct dsi_pll_14nm_postdiv, hw)
103 
104 /*
105  * Global list of private DSI PLL struct pointers. We need this for bonded DSI
106  * mode, where the master PLL's clk_ops needs access the slave's private data
107  */
108 static struct dsi_pll_14nm *pll_14nm_list[DSI_MAX];
109 
110 static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm,
111 				    u32 nb_tries, u32 timeout_us)
112 {
113 	bool pll_locked = false, pll_ready = false;
114 	void __iomem *base = pll_14nm->phy->pll_base;
115 	u32 tries, val;
116 
117 	tries = nb_tries;
118 	while (tries--) {
119 		val = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
120 		pll_locked = !!(val & BIT(5));
121 
122 		if (pll_locked)
123 			break;
124 
125 		udelay(timeout_us);
126 	}
127 
128 	if (!pll_locked)
129 		goto out;
130 
131 	tries = nb_tries;
132 	while (tries--) {
133 		val = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
134 		pll_ready = !!(val & BIT(0));
135 
136 		if (pll_ready)
137 			break;
138 
139 		udelay(timeout_us);
140 	}
141 
142 out:
143 	DBG("DSI PLL is %slocked, %sready", pll_locked ? "" : "*not* ", pll_ready ? "" : "*not* ");
144 
145 	return pll_locked && pll_ready;
146 }
147 
148 static void dsi_pll_14nm_config_init(struct dsi_pll_config *pconf)
149 {
150 	/* fixed input */
151 	pconf->plllock_cnt = 1;
152 
153 	/*
154 	 * SSC is enabled by default. We might need DT props for configuring
155 	 * some SSC params like PPM and center/down spread etc.
156 	 */
157 	pconf->ssc_en = 1;
158 	pconf->ssc_center = 0;		/* down spread by default */
159 	pconf->ssc_spread = 5;		/* PPM / 1000 */
160 	pconf->ssc_freq = 31500;	/* default recommended */
161 	pconf->ssc_adj_period = 37;
162 }
163 
164 #define CEIL(x, y)		(((x) + ((y) - 1)) / (y))
165 
166 static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
167 {
168 	u32 period, ssc_period;
169 	u32 ref, rem;
170 	u64 step_size;
171 
172 	DBG("vco=%lld ref=%d", pconf->vco_current_rate, VCO_REF_CLK_RATE);
173 
174 	ssc_period = pconf->ssc_freq / 500;
175 	period = (u32)VCO_REF_CLK_RATE / 1000;
176 	ssc_period  = CEIL(period, ssc_period);
177 	ssc_period -= 1;
178 	pconf->ssc_period = ssc_period;
179 
180 	DBG("ssc freq=%d spread=%d period=%d", pconf->ssc_freq,
181 	    pconf->ssc_spread, pconf->ssc_period);
182 
183 	step_size = (u32)pconf->vco_current_rate;
184 	ref = VCO_REF_CLK_RATE;
185 	ref /= 1000;
186 	step_size = div_u64(step_size, ref);
187 	step_size <<= 20;
188 	step_size = div_u64(step_size, 1000);
189 	step_size *= pconf->ssc_spread;
190 	step_size = div_u64(step_size, 1000);
191 	step_size *= (pconf->ssc_adj_period + 1);
192 
193 	rem = 0;
194 	step_size = div_u64_rem(step_size, ssc_period + 1, &rem);
195 	if (rem)
196 		step_size++;
197 
198 	DBG("step_size=%lld", step_size);
199 
200 	step_size &= 0x0ffff;	/* take lower 16 bits */
201 
202 	pconf->ssc_step_size = step_size;
203 }
204 
205 static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
206 {
207 	u64 multiplier = BIT(20);
208 	u64 dec_start_multiple, dec_start, pll_comp_val;
209 	u32 duration, div_frac_start;
210 	u64 vco_clk_rate = pconf->vco_current_rate;
211 	u64 fref = VCO_REF_CLK_RATE;
212 
213 	DBG("vco_clk_rate=%lld ref_clk_rate=%lld", vco_clk_rate, fref);
214 
215 	dec_start_multiple = div_u64(vco_clk_rate * multiplier, fref);
216 	dec_start = div_u64_rem(dec_start_multiple, multiplier, &div_frac_start);
217 
218 	pconf->dec_start = (u32)dec_start;
219 	pconf->div_frac_start = div_frac_start;
220 
221 	if (pconf->plllock_cnt == 0)
222 		duration = 1024;
223 	else if (pconf->plllock_cnt == 1)
224 		duration = 256;
225 	else if (pconf->plllock_cnt == 2)
226 		duration = 128;
227 	else
228 		duration = 32;
229 
230 	pll_comp_val = duration * dec_start_multiple;
231 	pll_comp_val = div_u64(pll_comp_val, multiplier);
232 	do_div(pll_comp_val, 10);
233 
234 	pconf->plllock_cmp = (u32)pll_comp_val;
235 }
236 
237 static u32 pll_14nm_kvco_slop(u32 vrate)
238 {
239 	u32 slop = 0;
240 
241 	if (vrate > VCO_MIN_RATE && vrate <= 1800000000UL)
242 		slop =  600;
243 	else if (vrate > 1800000000UL && vrate < 2300000000UL)
244 		slop = 400;
245 	else if (vrate > 2300000000UL && vrate < VCO_MAX_RATE)
246 		slop = 280;
247 
248 	return slop;
249 }
250 
251 static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
252 {
253 	u64 vco_clk_rate = pconf->vco_current_rate;
254 	u64 fref = VCO_REF_CLK_RATE;
255 	u32 vco_measure_time = 5;
256 	u32 kvco_measure_time = 5;
257 	u64 data;
258 	u32 cnt;
259 
260 	data = fref * vco_measure_time;
261 	do_div(data, 1000000);
262 	data &= 0x03ff;	/* 10 bits */
263 	data -= 2;
264 	pconf->pll_vco_div_ref = data;
265 
266 	data = div_u64(vco_clk_rate, 1000000);	/* unit is Mhz */
267 	data *= vco_measure_time;
268 	do_div(data, 10);
269 	pconf->pll_vco_count = data;
270 
271 	data = fref * kvco_measure_time;
272 	do_div(data, 1000000);
273 	data &= 0x03ff;	/* 10 bits */
274 	data -= 1;
275 	pconf->pll_kvco_div_ref = data;
276 
277 	cnt = pll_14nm_kvco_slop(vco_clk_rate);
278 	cnt *= 2;
279 	cnt /= 100;
280 	cnt *= kvco_measure_time;
281 	pconf->pll_kvco_count = cnt;
282 }
283 
284 static void pll_db_commit_ssc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
285 {
286 	void __iomem *base = pll->phy->pll_base;
287 	u8 data;
288 
289 	data = pconf->ssc_adj_period;
290 	data &= 0x0ff;
291 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data);
292 	data = (pconf->ssc_adj_period >> 8);
293 	data &= 0x03;
294 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data);
295 
296 	data = pconf->ssc_period;
297 	data &= 0x0ff;
298 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data);
299 	data = (pconf->ssc_period >> 8);
300 	data &= 0x0ff;
301 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data);
302 
303 	data = pconf->ssc_step_size;
304 	data &= 0x0ff;
305 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data);
306 	data = (pconf->ssc_step_size >> 8);
307 	data &= 0x0ff;
308 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data);
309 
310 	data = (pconf->ssc_center & 0x01);
311 	data <<= 1;
312 	data |= 0x01; /* enable */
313 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data);
314 
315 	wmb();	/* make sure register committed */
316 }
317 
318 static void pll_db_commit_common(struct dsi_pll_14nm *pll,
319 				 struct dsi_pll_config *pconf)
320 {
321 	void __iomem *base = pll->phy->pll_base;
322 	u8 data;
323 
324 	/* confgiure the non frequency dependent pll registers */
325 	data = 0;
326 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data);
327 
328 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, 1);
329 
330 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, 48);
331 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, 4 << 3); /* bandgap_timer */
332 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, 5); /* pll_wakeup_timer */
333 
334 	data = pconf->pll_vco_div_ref & 0xff;
335 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data);
336 	data = (pconf->pll_vco_div_ref >> 8) & 0x3;
337 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data);
338 
339 	data = pconf->pll_kvco_div_ref & 0xff;
340 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data);
341 	data = (pconf->pll_kvco_div_ref >> 8) & 0x3;
342 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data);
343 
344 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, 16);
345 
346 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, 4);
347 
348 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, 4);
349 
350 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, 1 << 3 | 1);
351 
352 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, 0 << 3 | 0);
353 
354 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, 0 << 3 | 0);
355 
356 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, 4 << 3 | 4);
357 
358 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, 1 << 4 | 11);
359 
360 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, 7);
361 
362 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, 1 << 4 | 2);
363 }
364 
365 static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
366 {
367 	void __iomem *cmn_base = pll_14nm->phy->base;
368 
369 	/* de assert pll start and apply pll sw reset */
370 
371 	/* stop pll */
372 	dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
373 
374 	/* pll sw reset */
375 	dsi_phy_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10);
376 	wmb();	/* make sure register committed */
377 
378 	dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0);
379 	wmb();	/* make sure register committed */
380 }
381 
382 static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
383 			       struct dsi_pll_config *pconf)
384 {
385 	void __iomem *base = pll->phy->pll_base;
386 	void __iomem *cmn_base = pll->phy->base;
387 	u8 data;
388 
389 	DBG("DSI%d PLL", pll->phy->id);
390 
391 	dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, 0x3c);
392 
393 	pll_db_commit_common(pll, pconf);
394 
395 	pll_14nm_software_reset(pll);
396 
397 	/* Use the /2 path in Mux */
398 	dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, 1);
399 
400 	data = 0xff; /* data, clk, pll normal operation */
401 	dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data);
402 
403 	/* configure the frequency dependent pll registers */
404 	data = pconf->dec_start;
405 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data);
406 
407 	data = pconf->div_frac_start & 0xff;
408 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data);
409 	data = (pconf->div_frac_start >> 8) & 0xff;
410 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data);
411 	data = (pconf->div_frac_start >> 16) & 0xf;
412 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data);
413 
414 	data = pconf->plllock_cmp & 0xff;
415 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data);
416 
417 	data = (pconf->plllock_cmp >> 8) & 0xff;
418 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data);
419 
420 	data = (pconf->plllock_cmp >> 16) & 0x3;
421 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data);
422 
423 	data = pconf->plllock_cnt << 1 | 0 << 3; /* plllock_rng */
424 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data);
425 
426 	data = pconf->pll_vco_count & 0xff;
427 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data);
428 	data = (pconf->pll_vco_count >> 8) & 0xff;
429 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data);
430 
431 	data = pconf->pll_kvco_count & 0xff;
432 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data);
433 	data = (pconf->pll_kvco_count >> 8) & 0x3;
434 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data);
435 
436 	/*
437 	 * High nibble configures the post divider internal to the VCO. It's
438 	 * fixed to divide by 1 for now.
439 	 *
440 	 * 0: divided by 1
441 	 * 1: divided by 2
442 	 * 2: divided by 4
443 	 * 3: divided by 8
444 	 */
445 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, 0 << 4 | 3);
446 
447 	if (pconf->ssc_en)
448 		pll_db_commit_ssc(pll, pconf);
449 
450 	wmb();	/* make sure register committed */
451 }
452 
453 /*
454  * VCO clock Callbacks
455  */
456 static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
457 				     unsigned long parent_rate)
458 {
459 	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
460 	struct dsi_pll_config conf;
461 
462 	DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->phy->id, rate,
463 	    parent_rate);
464 
465 	dsi_pll_14nm_config_init(&conf);
466 	conf.vco_current_rate = rate;
467 
468 	pll_14nm_dec_frac_calc(pll_14nm, &conf);
469 
470 	if (conf.ssc_en)
471 		pll_14nm_ssc_calc(pll_14nm, &conf);
472 
473 	pll_14nm_calc_vco_count(pll_14nm, &conf);
474 
475 	/* commit the slave DSI PLL registers if we're master. Note that we
476 	 * don't lock the slave PLL. We just ensure that the PLL/PHY registers
477 	 * of the master and slave are identical
478 	 */
479 	if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {
480 		struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
481 
482 		pll_db_commit_14nm(pll_14nm_slave, &conf);
483 	}
484 
485 	pll_db_commit_14nm(pll_14nm, &conf);
486 
487 	return 0;
488 }
489 
490 static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
491 						  unsigned long parent_rate)
492 {
493 	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
494 	void __iomem *base = pll_14nm->phy->pll_base;
495 	u64 vco_rate, multiplier = BIT(20);
496 	u32 div_frac_start;
497 	u32 dec_start;
498 	u64 ref_clk = parent_rate;
499 
500 	dec_start = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DEC_START);
501 	dec_start &= 0x0ff;
502 
503 	DBG("dec_start = %x", dec_start);
504 
505 	div_frac_start = (dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3)
506 				& 0xf) << 16;
507 	div_frac_start |= (dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2)
508 				& 0xff) << 8;
509 	div_frac_start |= dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1)
510 				& 0xff;
511 
512 	DBG("div_frac_start = %x", div_frac_start);
513 
514 	vco_rate = ref_clk * dec_start;
515 
516 	vco_rate += ((ref_clk * div_frac_start) / multiplier);
517 
518 	/*
519 	 * Recalculating the rate from dec_start and frac_start doesn't end up
520 	 * the rate we originally set. Convert the freq to KHz, round it up and
521 	 * convert it back to MHz.
522 	 */
523 	vco_rate = DIV_ROUND_UP_ULL(vco_rate, 1000) * 1000;
524 
525 	DBG("returning vco rate = %lu", (unsigned long)vco_rate);
526 
527 	return (unsigned long)vco_rate;
528 }
529 
530 static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
531 {
532 	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
533 	void __iomem *base = pll_14nm->phy->pll_base;
534 	void __iomem *cmn_base = pll_14nm->phy->base;
535 	bool locked;
536 
537 	DBG("");
538 
539 	if (unlikely(pll_14nm->phy->pll_on))
540 		return 0;
541 
542 	if (dsi_pll_14nm_vco_recalc_rate(hw, VCO_REF_CLK_RATE) == 0)
543 		dsi_pll_14nm_vco_set_rate(hw, pll_14nm->phy->cfg->min_pll_rate, VCO_REF_CLK_RATE);
544 
545 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
546 	dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
547 
548 	locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS,
549 					 POLL_TIMEOUT_US);
550 
551 	if (unlikely(!locked)) {
552 		DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev, "DSI PLL lock failed\n");
553 		return -EINVAL;
554 	}
555 
556 	DBG("DSI PLL lock success");
557 	pll_14nm->phy->pll_on = true;
558 
559 	return 0;
560 }
561 
562 static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw)
563 {
564 	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
565 	void __iomem *cmn_base = pll_14nm->phy->base;
566 
567 	DBG("");
568 
569 	if (unlikely(!pll_14nm->phy->pll_on))
570 		return;
571 
572 	dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
573 
574 	pll_14nm->phy->pll_on = false;
575 }
576 
577 static long dsi_pll_14nm_clk_round_rate(struct clk_hw *hw,
578 		unsigned long rate, unsigned long *parent_rate)
579 {
580 	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
581 
582 	if      (rate < pll_14nm->phy->cfg->min_pll_rate)
583 		return  pll_14nm->phy->cfg->min_pll_rate;
584 	else if (rate > pll_14nm->phy->cfg->max_pll_rate)
585 		return  pll_14nm->phy->cfg->max_pll_rate;
586 	else
587 		return rate;
588 }
589 
590 static const struct clk_ops clk_ops_dsi_pll_14nm_vco = {
591 	.round_rate = dsi_pll_14nm_clk_round_rate,
592 	.set_rate = dsi_pll_14nm_vco_set_rate,
593 	.recalc_rate = dsi_pll_14nm_vco_recalc_rate,
594 	.prepare = dsi_pll_14nm_vco_prepare,
595 	.unprepare = dsi_pll_14nm_vco_unprepare,
596 };
597 
598 /*
599  * N1 and N2 post-divider clock callbacks
600  */
601 #define div_mask(width)	((1 << (width)) - 1)
602 static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw,
603 						      unsigned long parent_rate)
604 {
605 	struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
606 	struct dsi_pll_14nm *pll_14nm = postdiv->pll;
607 	void __iomem *base = pll_14nm->phy->base;
608 	u8 shift = postdiv->shift;
609 	u8 width = postdiv->width;
610 	u32 val;
611 
612 	DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, parent_rate);
613 
614 	val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift;
615 	val &= div_mask(width);
616 
617 	return divider_recalc_rate(hw, parent_rate, val, NULL,
618 				   postdiv->flags, width);
619 }
620 
621 static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw,
622 					    unsigned long rate,
623 					    unsigned long *prate)
624 {
625 	struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
626 	struct dsi_pll_14nm *pll_14nm = postdiv->pll;
627 
628 	DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, rate);
629 
630 	return divider_round_rate(hw, rate, prate, NULL,
631 				  postdiv->width,
632 				  postdiv->flags);
633 }
634 
635 static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
636 					 unsigned long parent_rate)
637 {
638 	struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
639 	struct dsi_pll_14nm *pll_14nm = postdiv->pll;
640 	void __iomem *base = pll_14nm->phy->base;
641 	spinlock_t *lock = &pll_14nm->postdiv_lock;
642 	u8 shift = postdiv->shift;
643 	u8 width = postdiv->width;
644 	unsigned int value;
645 	unsigned long flags = 0;
646 	u32 val;
647 
648 	DBG("DSI%d PLL parent rate=%lu parent rate %lu", pll_14nm->phy->id, rate,
649 	    parent_rate);
650 
651 	value = divider_get_val(rate, parent_rate, NULL, postdiv->width,
652 				postdiv->flags);
653 
654 	spin_lock_irqsave(lock, flags);
655 
656 	val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
657 	val &= ~(div_mask(width) << shift);
658 
659 	val |= value << shift;
660 	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
661 
662 	/* If we're master in bonded DSI mode, then the slave PLL's post-dividers
663 	 * follow the master's post dividers
664 	 */
665 	if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {
666 		struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
667 		void __iomem *slave_base = pll_14nm_slave->phy->base;
668 
669 		dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
670 	}
671 
672 	spin_unlock_irqrestore(lock, flags);
673 
674 	return 0;
675 }
676 
677 static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = {
678 	.recalc_rate = dsi_pll_14nm_postdiv_recalc_rate,
679 	.round_rate = dsi_pll_14nm_postdiv_round_rate,
680 	.set_rate = dsi_pll_14nm_postdiv_set_rate,
681 };
682 
683 /*
684  * PLL Callbacks
685  */
686 
687 static void dsi_14nm_pll_save_state(struct msm_dsi_phy *phy)
688 {
689 	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
690 	struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
691 	void __iomem *cmn_base = pll_14nm->phy->base;
692 	u32 data;
693 
694 	data = dsi_phy_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
695 
696 	cached_state->n1postdiv = data & 0xf;
697 	cached_state->n2postdiv = (data >> 4) & 0xf;
698 
699 	DBG("DSI%d PLL save state %x %x", pll_14nm->phy->id,
700 	    cached_state->n1postdiv, cached_state->n2postdiv);
701 
702 	cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
703 }
704 
705 static int dsi_14nm_pll_restore_state(struct msm_dsi_phy *phy)
706 {
707 	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
708 	struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
709 	void __iomem *cmn_base = pll_14nm->phy->base;
710 	u32 data;
711 	int ret;
712 
713 	ret = dsi_pll_14nm_vco_set_rate(phy->vco_hw,
714 					cached_state->vco_rate, 0);
715 	if (ret) {
716 		DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev,
717 			      "restore vco rate failed. ret=%d\n", ret);
718 		return ret;
719 	}
720 
721 	data = cached_state->n1postdiv | (cached_state->n2postdiv << 4);
722 
723 	DBG("DSI%d PLL restore state %x %x", pll_14nm->phy->id,
724 	    cached_state->n1postdiv, cached_state->n2postdiv);
725 
726 	dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
727 
728 	/* also restore post-dividers for slave DSI PLL */
729 	if (phy->usecase == MSM_DSI_PHY_MASTER) {
730 		struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
731 		void __iomem *slave_base = pll_14nm_slave->phy->base;
732 
733 		dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
734 	}
735 
736 	return 0;
737 }
738 
739 static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy)
740 {
741 	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
742 	void __iomem *base = phy->pll_base;
743 	u32 clkbuflr_en, bandgap = 0;
744 
745 	switch (phy->usecase) {
746 	case MSM_DSI_PHY_STANDALONE:
747 		clkbuflr_en = 0x1;
748 		break;
749 	case MSM_DSI_PHY_MASTER:
750 		clkbuflr_en = 0x3;
751 		pll_14nm->slave = pll_14nm_list[(pll_14nm->phy->id + 1) % DSI_MAX];
752 		break;
753 	case MSM_DSI_PHY_SLAVE:
754 		clkbuflr_en = 0x0;
755 		bandgap = 0x3;
756 		break;
757 	default:
758 		return -EINVAL;
759 	}
760 
761 	dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN, clkbuflr_en);
762 	if (bandgap)
763 		dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap);
764 
765 	return 0;
766 }
767 
768 static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
769 						const char *name,
770 						const struct clk_hw *parent_hw,
771 						unsigned long flags,
772 						u8 shift)
773 {
774 	struct dsi_pll_14nm_postdiv *pll_postdiv;
775 	struct device *dev = &pll_14nm->phy->pdev->dev;
776 	struct clk_init_data postdiv_init = {
777 		.parent_hws = (const struct clk_hw *[]) { parent_hw },
778 		.num_parents = 1,
779 		.name = name,
780 		.flags = flags,
781 		.ops = &clk_ops_dsi_pll_14nm_postdiv,
782 	};
783 	int ret;
784 
785 	pll_postdiv = devm_kzalloc(dev, sizeof(*pll_postdiv), GFP_KERNEL);
786 	if (!pll_postdiv)
787 		return ERR_PTR(-ENOMEM);
788 
789 	pll_postdiv->pll = pll_14nm;
790 	pll_postdiv->shift = shift;
791 	/* both N1 and N2 postdividers are 4 bits wide */
792 	pll_postdiv->width = 4;
793 	/* range of each divider is from 1 to 15 */
794 	pll_postdiv->flags = CLK_DIVIDER_ONE_BASED;
795 	pll_postdiv->hw.init = &postdiv_init;
796 
797 	ret = devm_clk_hw_register(dev, &pll_postdiv->hw);
798 	if (ret)
799 		return ERR_PTR(ret);
800 
801 	return &pll_postdiv->hw;
802 }
803 
804 static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **provided_clocks)
805 {
806 	char clk_name[32];
807 	struct clk_init_data vco_init = {
808 		.parent_data = &(const struct clk_parent_data) {
809 			.fw_name = "ref",
810 		},
811 		.num_parents = 1,
812 		.name = clk_name,
813 		.flags = CLK_IGNORE_UNUSED,
814 		.ops = &clk_ops_dsi_pll_14nm_vco,
815 	};
816 	struct device *dev = &pll_14nm->phy->pdev->dev;
817 	struct clk_hw *hw, *n1_postdiv, *n1_postdivby2;
818 	int ret;
819 
820 	DBG("DSI%d", pll_14nm->phy->id);
821 
822 	snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_14nm->phy->id);
823 	pll_14nm->clk_hw.init = &vco_init;
824 
825 	ret = devm_clk_hw_register(dev, &pll_14nm->clk_hw);
826 	if (ret)
827 		return ret;
828 
829 	snprintf(clk_name, sizeof(clk_name), "dsi%dn1_postdiv_clk", pll_14nm->phy->id);
830 
831 	/* N1 postdiv, bits 0-3 in REG_DSI_14nm_PHY_CMN_CLK_CFG0 */
832 	n1_postdiv = pll_14nm_postdiv_register(pll_14nm, clk_name,
833 			&pll_14nm->clk_hw, CLK_SET_RATE_PARENT, 0);
834 	if (IS_ERR(n1_postdiv))
835 		return PTR_ERR(n1_postdiv);
836 
837 	snprintf(clk_name, sizeof(clk_name), "dsi%dpllbyte", pll_14nm->phy->id);
838 
839 	/* DSI Byte clock = VCO_CLK / N1 / 8 */
840 	hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name,
841 			n1_postdiv, CLK_SET_RATE_PARENT, 1, 8);
842 	if (IS_ERR(hw))
843 		return PTR_ERR(hw);
844 
845 	provided_clocks[DSI_BYTE_PLL_CLK] = hw;
846 
847 	snprintf(clk_name, sizeof(clk_name), "dsi%dn1_postdivby2_clk", pll_14nm->phy->id);
848 
849 	/*
850 	 * Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider
851 	 * on the way. Don't let it set parent.
852 	 */
853 	n1_postdivby2 = devm_clk_hw_register_fixed_factor_parent_hw(dev,
854 			clk_name, n1_postdiv, 0, 1, 2);
855 	if (IS_ERR(n1_postdivby2))
856 		return PTR_ERR(n1_postdivby2);
857 
858 	snprintf(clk_name, sizeof(clk_name), "dsi%dpll", pll_14nm->phy->id);
859 
860 	/* DSI pixel clock = VCO_CLK / N1 / 2 / N2
861 	 * This is the output of N2 post-divider, bits 4-7 in
862 	 * REG_DSI_14nm_PHY_CMN_CLK_CFG0. Don't let it set parent.
863 	 */
864 	hw = pll_14nm_postdiv_register(pll_14nm, clk_name, n1_postdivby2,
865 			0, 4);
866 	if (IS_ERR(hw))
867 		return PTR_ERR(hw);
868 
869 	provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
870 
871 	return 0;
872 }
873 
874 static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
875 {
876 	struct platform_device *pdev = phy->pdev;
877 	struct dsi_pll_14nm *pll_14nm;
878 	int ret;
879 
880 	if (!pdev)
881 		return -ENODEV;
882 
883 	pll_14nm = devm_kzalloc(&pdev->dev, sizeof(*pll_14nm), GFP_KERNEL);
884 	if (!pll_14nm)
885 		return -ENOMEM;
886 
887 	DBG("PLL%d", phy->id);
888 
889 	pll_14nm_list[phy->id] = pll_14nm;
890 
891 	spin_lock_init(&pll_14nm->postdiv_lock);
892 
893 	pll_14nm->phy = phy;
894 
895 	ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws);
896 	if (ret) {
897 		DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
898 		return ret;
899 	}
900 
901 	phy->vco_hw = &pll_14nm->clk_hw;
902 
903 	return 0;
904 }
905 
906 static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy,
907 				     struct msm_dsi_dphy_timing *timing,
908 				     int lane_idx)
909 {
910 	void __iomem *base = phy->lane_base;
911 	bool clk_ln = (lane_idx == PHY_14NM_CKLN_IDX);
912 	u32 zero = clk_ln ? timing->clk_zero : timing->hs_zero;
913 	u32 prepare = clk_ln ? timing->clk_prepare : timing->hs_prepare;
914 	u32 trail = clk_ln ? timing->clk_trail : timing->hs_trail;
915 	u32 rqst = clk_ln ? timing->hs_rqst_ckln : timing->hs_rqst;
916 	u32 prep_dly = clk_ln ? timing->hs_prep_dly_ckln : timing->hs_prep_dly;
917 	u32 halfbyte_en = clk_ln ? timing->hs_halfbyte_en_ckln :
918 				   timing->hs_halfbyte_en;
919 
920 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(lane_idx),
921 		      DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit));
922 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(lane_idx),
923 		      DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(zero));
924 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(lane_idx),
925 		      DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(prepare));
926 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(lane_idx),
927 		      DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(trail));
928 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(lane_idx),
929 		      DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(rqst));
930 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG0(lane_idx),
931 		      DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(prep_dly));
932 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG1(lane_idx),
933 		      halfbyte_en ? DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN : 0);
934 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(lane_idx),
935 		      DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(timing->ta_go) |
936 		      DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(timing->ta_sure));
937 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(lane_idx),
938 		      DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(timing->ta_get));
939 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(lane_idx),
940 		      DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(0xa0));
941 }
942 
943 static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy,
944 			       struct msm_dsi_phy_clk_request *clk_req)
945 {
946 	struct msm_dsi_dphy_timing *timing = &phy->timing;
947 	u32 data;
948 	int i;
949 	int ret;
950 	void __iomem *base = phy->base;
951 	void __iomem *lane_base = phy->lane_base;
952 	u32 glbl_test_ctrl;
953 
954 	if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) {
955 		DRM_DEV_ERROR(&phy->pdev->dev,
956 			      "%s: D-PHY timing calculation failed\n",
957 			      __func__);
958 		return -EINVAL;
959 	}
960 
961 	data = 0x1c;
962 	if (phy->usecase != MSM_DSI_PHY_STANDALONE)
963 		data |= DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(32);
964 	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data);
965 
966 	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0x1);
967 
968 	/* 4 data lanes + 1 clk lane configuration */
969 	for (i = 0; i < 5; i++) {
970 		dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_VREG_CNTRL(i),
971 			      0x1d);
972 
973 		dsi_phy_write(lane_base +
974 			      REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(i), 0xff);
975 		dsi_phy_write(lane_base +
976 			      REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(i),
977 			      (i == PHY_14NM_CKLN_IDX) ? 0x00 : 0x06);
978 
979 		dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG3(i),
980 			      (i == PHY_14NM_CKLN_IDX) ? 0x8f : 0x0f);
981 		dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG2(i), 0x10);
982 		dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_DATAPATH(i),
983 			      0);
984 		dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_STR(i),
985 			      0x88);
986 
987 		dsi_14nm_dphy_set_timing(phy, timing, i);
988 	}
989 
990 	/* Make sure PLL is not start */
991 	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0x00);
992 
993 	wmb(); /* make sure everything is written before reset and enable */
994 
995 	/* reset digital block */
996 	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x80);
997 	wmb(); /* ensure reset is asserted */
998 	udelay(100);
999 	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00);
1000 
1001 	glbl_test_ctrl = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
1002 	if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_SLAVE)
1003 		glbl_test_ctrl |= DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
1004 	else
1005 		glbl_test_ctrl &= ~DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
1006 	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, glbl_test_ctrl);
1007 	ret = dsi_14nm_set_usecase(phy);
1008 	if (ret) {
1009 		DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
1010 			      __func__, ret);
1011 		return ret;
1012 	}
1013 
1014 	/* Remove power down from PLL and all lanes */
1015 	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0xff);
1016 
1017 	return 0;
1018 }
1019 
1020 static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy)
1021 {
1022 	dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0);
1023 	dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0);
1024 
1025 	/* ensure that the phy is completely disabled */
1026 	wmb();
1027 }
1028 
1029 static const struct regulator_bulk_data dsi_phy_14nm_17mA_regulators[] = {
1030 	{ .supply = "vcca", .init_load_uA = 17000 },
1031 };
1032 
1033 static const struct regulator_bulk_data dsi_phy_14nm_73p4mA_regulators[] = {
1034 	{ .supply = "vcca", .init_load_uA = 73400 },
1035 };
1036 
1037 const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
1038 	.has_phy_lane = true,
1039 	.regulator_data = dsi_phy_14nm_17mA_regulators,
1040 	.num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators),
1041 	.ops = {
1042 		.enable = dsi_14nm_phy_enable,
1043 		.disable = dsi_14nm_phy_disable,
1044 		.pll_init = dsi_pll_14nm_init,
1045 		.save_pll_state = dsi_14nm_pll_save_state,
1046 		.restore_pll_state = dsi_14nm_pll_restore_state,
1047 	},
1048 	.min_pll_rate = VCO_MIN_RATE,
1049 	.max_pll_rate = VCO_MAX_RATE,
1050 	.io_start = { 0x994400, 0x996400 },
1051 	.num_dsi_phy = 2,
1052 };
1053 
1054 const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
1055 	.has_phy_lane = true,
1056 	.regulator_data = dsi_phy_14nm_73p4mA_regulators,
1057 	.num_regulators = ARRAY_SIZE(dsi_phy_14nm_73p4mA_regulators),
1058 	.ops = {
1059 		.enable = dsi_14nm_phy_enable,
1060 		.disable = dsi_14nm_phy_disable,
1061 		.pll_init = dsi_pll_14nm_init,
1062 		.save_pll_state = dsi_14nm_pll_save_state,
1063 		.restore_pll_state = dsi_14nm_pll_restore_state,
1064 	},
1065 	.min_pll_rate = VCO_MIN_RATE,
1066 	.max_pll_rate = VCO_MAX_RATE,
1067 	.io_start = { 0xc994400, 0xc996400 },
1068 	.num_dsi_phy = 2,
1069 };
1070 
1071 const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = {
1072 	.has_phy_lane = true,
1073 	.regulator_data = dsi_phy_14nm_17mA_regulators,
1074 	.num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators),
1075 	.ops = {
1076 		.enable = dsi_14nm_phy_enable,
1077 		.disable = dsi_14nm_phy_disable,
1078 		.pll_init = dsi_pll_14nm_init,
1079 		.save_pll_state = dsi_14nm_pll_save_state,
1080 		.restore_pll_state = dsi_14nm_pll_restore_state,
1081 	},
1082 	.min_pll_rate = VCO_MIN_RATE,
1083 	.max_pll_rate = VCO_MAX_RATE,
1084 	.io_start = { 0x1a94400, 0x1a96400 },
1085 	.num_dsi_phy = 2,
1086 };
1087 
1088 const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = {
1089 	.has_phy_lane = true,
1090 	.ops = {
1091 		.enable = dsi_14nm_phy_enable,
1092 		.disable = dsi_14nm_phy_disable,
1093 		.pll_init = dsi_pll_14nm_init,
1094 		.save_pll_state = dsi_14nm_pll_save_state,
1095 		.restore_pll_state = dsi_14nm_pll_restore_state,
1096 	},
1097 	.min_pll_rate = VCO_MIN_RATE,
1098 	.max_pll_rate = VCO_MAX_RATE,
1099 	.io_start = { 0x5e94400 },
1100 	.num_dsi_phy = 1,
1101 };
1102