1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef __DSI_PHY_H__ 7 #define __DSI_PHY_H__ 8 9 #include <linux/clk-provider.h> 10 #include <linux/delay.h> 11 #include <linux/regulator/consumer.h> 12 13 #include "dsi.h" 14 15 #define dsi_phy_read(offset) msm_readl((offset)) 16 #define dsi_phy_write(offset, data) msm_writel((data), (offset)) 17 #define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_us); } 18 #define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data), (offset)); ndelay(delay_ns); } 19 20 struct msm_dsi_phy_ops { 21 int (*pll_init)(struct msm_dsi_phy *phy); 22 int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, 23 struct msm_dsi_phy_clk_request *clk_req); 24 void (*disable)(struct msm_dsi_phy *phy); 25 void (*save_pll_state)(struct msm_dsi_phy *phy); 26 int (*restore_pll_state)(struct msm_dsi_phy *phy); 27 }; 28 29 struct msm_dsi_phy_cfg { 30 struct dsi_reg_config reg_cfg; 31 struct msm_dsi_phy_ops ops; 32 33 unsigned long min_pll_rate; 34 unsigned long max_pll_rate; 35 36 /* 37 * Each cell {phy_id, pll_id} of the truth table indicates 38 * if the source PLL selection bit should be set for each PHY. 39 * Fill default H/W values in illegal cells, eg. cell {0, 1}. 40 */ 41 bool src_pll_truthtable[DSI_MAX][DSI_MAX]; 42 const resource_size_t io_start[DSI_MAX]; 43 const int num_dsi_phy; 44 const int quirks; 45 bool has_phy_regulator; 46 bool has_phy_lane; 47 }; 48 49 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs; 50 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs; 51 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs; 52 extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; 53 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; 54 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; 55 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; 56 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs; 57 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; 58 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs; 59 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; 60 61 struct msm_dsi_dphy_timing { 62 u32 clk_zero; 63 u32 clk_trail; 64 u32 clk_prepare; 65 u32 hs_exit; 66 u32 hs_zero; 67 u32 hs_prepare; 68 u32 hs_trail; 69 u32 hs_rqst; 70 u32 ta_go; 71 u32 ta_sure; 72 u32 ta_get; 73 74 struct msm_dsi_phy_shared_timings shared_timings; 75 76 /* For PHY v2 only */ 77 u32 hs_rqst_ckln; 78 u32 hs_prep_dly; 79 u32 hs_prep_dly_ckln; 80 u8 hs_halfbyte_en; 81 u8 hs_halfbyte_en_ckln; 82 }; 83 84 #define DSI_BYTE_PLL_CLK 0 85 #define DSI_PIXEL_PLL_CLK 1 86 #define NUM_PROVIDED_CLKS 2 87 88 struct msm_dsi_phy { 89 struct platform_device *pdev; 90 void __iomem *base; 91 void __iomem *reg_base; 92 void __iomem *lane_base; 93 int id; 94 95 struct clk *ahb_clk; 96 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; 97 98 struct msm_dsi_dphy_timing timing; 99 const struct msm_dsi_phy_cfg *cfg; 100 101 enum msm_dsi_phy_usecase usecase; 102 bool regulator_ldo_mode; 103 104 struct clk_hw *vco_hw; 105 bool pll_on; 106 107 struct clk_hw_onecell_data *provided_clocks; 108 109 bool state_saved; 110 }; 111 112 /* 113 * PHY internal functions 114 */ 115 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, 116 struct msm_dsi_phy_clk_request *clk_req); 117 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing, 118 struct msm_dsi_phy_clk_request *clk_req); 119 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing, 120 struct msm_dsi_phy_clk_request *clk_req); 121 int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, 122 struct msm_dsi_phy_clk_request *clk_req); 123 void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg, 124 u32 bit_mask); 125 126 #endif /* __DSI_PHY_H__ */ 127