1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef __DSI_PHY_H__ 7 #define __DSI_PHY_H__ 8 9 #include <linux/regulator/consumer.h> 10 11 #include "dsi.h" 12 13 #define dsi_phy_read(offset) msm_readl((offset)) 14 #define dsi_phy_write(offset, data) msm_writel((data), (offset)) 15 16 struct msm_dsi_phy_ops { 17 int (*pll_init)(struct msm_dsi_phy *phy); 18 int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, 19 struct msm_dsi_phy_clk_request *clk_req); 20 void (*disable)(struct msm_dsi_phy *phy); 21 }; 22 23 struct msm_dsi_pll_ops { 24 int (*enable_seq)(struct msm_dsi_pll *pll); 25 void (*disable_seq)(struct msm_dsi_pll *pll); 26 int (*get_provider)(struct msm_dsi_pll *pll, 27 struct clk **byte_clk_provider, 28 struct clk **pixel_clk_provider); 29 void (*destroy)(struct msm_dsi_pll *pll); 30 void (*save_state)(struct msm_dsi_pll *pll); 31 int (*restore_state)(struct msm_dsi_pll *pll); 32 }; 33 34 struct msm_dsi_phy_cfg { 35 struct dsi_reg_config reg_cfg; 36 struct msm_dsi_phy_ops ops; 37 const struct msm_dsi_pll_ops pll_ops; 38 39 unsigned long min_pll_rate; 40 unsigned long max_pll_rate; 41 42 /* 43 * Each cell {phy_id, pll_id} of the truth table indicates 44 * if the source PLL selection bit should be set for each PHY. 45 * Fill default H/W values in illegal cells, eg. cell {0, 1}. 46 */ 47 bool src_pll_truthtable[DSI_MAX][DSI_MAX]; 48 const resource_size_t io_start[DSI_MAX]; 49 const int num_dsi_phy; 50 const int quirks; 51 bool has_phy_regulator; 52 bool has_phy_lane; 53 }; 54 55 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs; 56 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs; 57 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs; 58 extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; 59 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; 60 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; 61 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; 62 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs; 63 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; 64 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs; 65 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; 66 67 struct msm_dsi_dphy_timing { 68 u32 clk_zero; 69 u32 clk_trail; 70 u32 clk_prepare; 71 u32 hs_exit; 72 u32 hs_zero; 73 u32 hs_prepare; 74 u32 hs_trail; 75 u32 hs_rqst; 76 u32 ta_go; 77 u32 ta_sure; 78 u32 ta_get; 79 80 struct msm_dsi_phy_shared_timings shared_timings; 81 82 /* For PHY v2 only */ 83 u32 hs_rqst_ckln; 84 u32 hs_prep_dly; 85 u32 hs_prep_dly_ckln; 86 u8 hs_halfbyte_en; 87 u8 hs_halfbyte_en_ckln; 88 }; 89 90 struct msm_dsi_phy { 91 struct platform_device *pdev; 92 void __iomem *base; 93 void __iomem *reg_base; 94 void __iomem *lane_base; 95 int id; 96 97 struct clk *ahb_clk; 98 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; 99 100 struct msm_dsi_dphy_timing timing; 101 const struct msm_dsi_phy_cfg *cfg; 102 103 enum msm_dsi_phy_usecase usecase; 104 bool regulator_ldo_mode; 105 106 struct msm_dsi_pll *pll; 107 }; 108 109 /* 110 * PHY internal functions 111 */ 112 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, 113 struct msm_dsi_phy_clk_request *clk_req); 114 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing, 115 struct msm_dsi_phy_clk_request *clk_req); 116 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing, 117 struct msm_dsi_phy_clk_request *clk_req); 118 int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, 119 struct msm_dsi_phy_clk_request *clk_req); 120 void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg, 121 u32 bit_mask); 122 123 #endif /* __DSI_PHY_H__ */ 124 125