1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef __DSI_PHY_H__ 7 #define __DSI_PHY_H__ 8 9 #include <linux/regulator/consumer.h> 10 11 #include "dsi.h" 12 13 #define dsi_phy_read(offset) msm_readl((offset)) 14 #define dsi_phy_write(offset, data) msm_writel((data), (offset)) 15 16 struct msm_dsi_phy_ops { 17 int (*init) (struct msm_dsi_phy *phy); 18 int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, 19 struct msm_dsi_phy_clk_request *clk_req); 20 void (*disable)(struct msm_dsi_phy *phy); 21 }; 22 23 struct msm_dsi_phy_cfg { 24 enum msm_dsi_phy_type type; 25 struct dsi_reg_config reg_cfg; 26 struct msm_dsi_phy_ops ops; 27 28 /* 29 * Each cell {phy_id, pll_id} of the truth table indicates 30 * if the source PLL selection bit should be set for each PHY. 31 * Fill default H/W values in illegal cells, eg. cell {0, 1}. 32 */ 33 bool src_pll_truthtable[DSI_MAX][DSI_MAX]; 34 const resource_size_t io_start[DSI_MAX]; 35 const int num_dsi_phy; 36 }; 37 38 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs; 39 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs; 40 extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; 41 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; 42 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; 43 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs; 44 45 struct msm_dsi_dphy_timing { 46 u32 clk_pre; 47 u32 clk_post; 48 u32 clk_zero; 49 u32 clk_trail; 50 u32 clk_prepare; 51 u32 hs_exit; 52 u32 hs_zero; 53 u32 hs_prepare; 54 u32 hs_trail; 55 u32 hs_rqst; 56 u32 ta_go; 57 u32 ta_sure; 58 u32 ta_get; 59 60 struct msm_dsi_phy_shared_timings shared_timings; 61 62 /* For PHY v2 only */ 63 u32 hs_rqst_ckln; 64 u32 hs_prep_dly; 65 u32 hs_prep_dly_ckln; 66 u8 hs_halfbyte_en; 67 u8 hs_halfbyte_en_ckln; 68 }; 69 70 struct msm_dsi_phy { 71 struct platform_device *pdev; 72 void __iomem *base; 73 void __iomem *reg_base; 74 void __iomem *lane_base; 75 int id; 76 77 struct clk *ahb_clk; 78 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; 79 80 struct msm_dsi_dphy_timing timing; 81 const struct msm_dsi_phy_cfg *cfg; 82 83 enum msm_dsi_phy_usecase usecase; 84 bool regulator_ldo_mode; 85 86 struct msm_dsi_pll *pll; 87 }; 88 89 /* 90 * PHY internal functions 91 */ 92 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, 93 struct msm_dsi_phy_clk_request *clk_req); 94 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing, 95 struct msm_dsi_phy_clk_request *clk_req); 96 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing, 97 struct msm_dsi_phy_clk_request *clk_req); 98 void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg, 99 u32 bit_mask); 100 int msm_dsi_phy_init_common(struct msm_dsi_phy *phy); 101 102 #endif /* __DSI_PHY_H__ */ 103 104