1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef __DSI_PHY_H__ 7 #define __DSI_PHY_H__ 8 9 #include <linux/clk-provider.h> 10 #include <linux/delay.h> 11 #include <linux/regulator/consumer.h> 12 13 #include "dsi.h" 14 15 #define dsi_phy_read(offset) msm_readl((offset)) 16 #define dsi_phy_write(offset, data) msm_writel((data), (offset)) 17 18 struct msm_dsi_phy_ops { 19 int (*pll_init)(struct msm_dsi_phy *phy); 20 int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, 21 struct msm_dsi_phy_clk_request *clk_req); 22 void (*disable)(struct msm_dsi_phy *phy); 23 void (*save_pll_state)(struct msm_dsi_phy *phy); 24 int (*restore_pll_state)(struct msm_dsi_phy *phy); 25 }; 26 27 struct msm_dsi_phy_cfg { 28 struct dsi_reg_config reg_cfg; 29 struct msm_dsi_phy_ops ops; 30 31 unsigned long min_pll_rate; 32 unsigned long max_pll_rate; 33 34 /* 35 * Each cell {phy_id, pll_id} of the truth table indicates 36 * if the source PLL selection bit should be set for each PHY. 37 * Fill default H/W values in illegal cells, eg. cell {0, 1}. 38 */ 39 bool src_pll_truthtable[DSI_MAX][DSI_MAX]; 40 const resource_size_t io_start[DSI_MAX]; 41 const int num_dsi_phy; 42 const int quirks; 43 bool has_phy_regulator; 44 bool has_phy_lane; 45 }; 46 47 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs; 48 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs; 49 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs; 50 extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; 51 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; 52 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; 53 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; 54 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs; 55 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; 56 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs; 57 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; 58 59 struct msm_dsi_dphy_timing { 60 u32 clk_zero; 61 u32 clk_trail; 62 u32 clk_prepare; 63 u32 hs_exit; 64 u32 hs_zero; 65 u32 hs_prepare; 66 u32 hs_trail; 67 u32 hs_rqst; 68 u32 ta_go; 69 u32 ta_sure; 70 u32 ta_get; 71 72 struct msm_dsi_phy_shared_timings shared_timings; 73 74 /* For PHY v2 only */ 75 u32 hs_rqst_ckln; 76 u32 hs_prep_dly; 77 u32 hs_prep_dly_ckln; 78 u8 hs_halfbyte_en; 79 u8 hs_halfbyte_en_ckln; 80 }; 81 82 #define DSI_BYTE_PLL_CLK 0 83 #define DSI_PIXEL_PLL_CLK 1 84 #define NUM_PROVIDED_CLKS 2 85 86 struct msm_dsi_phy { 87 struct platform_device *pdev; 88 void __iomem *base; 89 void __iomem *reg_base; 90 void __iomem *lane_base; 91 int id; 92 93 struct clk *ahb_clk; 94 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; 95 96 struct msm_dsi_dphy_timing timing; 97 const struct msm_dsi_phy_cfg *cfg; 98 99 enum msm_dsi_phy_usecase usecase; 100 bool regulator_ldo_mode; 101 102 struct clk_hw *vco_hw; 103 bool pll_on; 104 105 struct clk_hw_onecell_data *provided_clocks; 106 107 bool state_saved; 108 }; 109 110 /* 111 * PHY internal functions 112 */ 113 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, 114 struct msm_dsi_phy_clk_request *clk_req); 115 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing, 116 struct msm_dsi_phy_clk_request *clk_req); 117 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing, 118 struct msm_dsi_phy_clk_request *clk_req); 119 int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, 120 struct msm_dsi_phy_clk_request *clk_req); 121 void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg, 122 u32 bit_mask); 123 /* PLL accessors */ 124 static inline void pll_write(void __iomem *reg, u32 data) 125 { 126 msm_writel(data, reg); 127 } 128 129 static inline u32 pll_read(const void __iomem *reg) 130 { 131 return msm_readl(reg); 132 } 133 134 static inline void pll_write_udelay(void __iomem *reg, u32 data, u32 delay_us) 135 { 136 pll_write(reg, data); 137 udelay(delay_us); 138 } 139 140 static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns) 141 { 142 pll_write((reg), data); 143 ndelay(delay_ns); 144 } 145 146 #endif /* __DSI_PHY_H__ */ 147