xref: /openbmc/linux/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c (revision b8d312aa)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/platform_device.h>
7 
8 #include "dsi_phy.h"
9 
10 #define S_DIV_ROUND_UP(n, d)	\
11 	(((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
12 
13 static inline s32 linear_inter(s32 tmax, s32 tmin, s32 percent,
14 				s32 min_result, bool even)
15 {
16 	s32 v;
17 
18 	v = (tmax - tmin) * percent;
19 	v = S_DIV_ROUND_UP(v, 100) + tmin;
20 	if (even && (v & 0x1))
21 		return max_t(s32, min_result, v - 1);
22 	else
23 		return max_t(s32, min_result, v);
24 }
25 
26 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing,
27 					s32 ui, s32 coeff, s32 pcnt)
28 {
29 	s32 tmax, tmin, clk_z;
30 	s32 temp;
31 
32 	/* reset */
33 	temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui;
34 	tmin = S_DIV_ROUND_UP(temp, ui) - 2;
35 	if (tmin > 255) {
36 		tmax = 511;
37 		clk_z = linear_inter(2 * tmin, tmin, pcnt, 0, true);
38 	} else {
39 		tmax = 255;
40 		clk_z = linear_inter(tmax, tmin, pcnt, 0, true);
41 	}
42 
43 	/* adjust */
44 	temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7;
45 	timing->clk_zero = clk_z + 8 - temp;
46 }
47 
48 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
49 			     struct msm_dsi_phy_clk_request *clk_req)
50 {
51 	const unsigned long bit_rate = clk_req->bitclk_rate;
52 	const unsigned long esc_rate = clk_req->escclk_rate;
53 	s32 ui, lpx;
54 	s32 tmax, tmin;
55 	s32 pcnt0 = 10;
56 	s32 pcnt1 = (bit_rate > 1200000000) ? 15 : 10;
57 	s32 pcnt2 = 10;
58 	s32 pcnt3 = (bit_rate > 180000000) ? 10 : 40;
59 	s32 coeff = 1000; /* Precision, should avoid overflow */
60 	s32 temp;
61 
62 	if (!bit_rate || !esc_rate)
63 		return -EINVAL;
64 
65 	ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
66 	lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
67 
68 	tmax = S_DIV_ROUND_UP(95 * coeff, ui) - 2;
69 	tmin = S_DIV_ROUND_UP(38 * coeff, ui) - 2;
70 	timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true);
71 
72 	temp = lpx / ui;
73 	if (temp & 0x1)
74 		timing->hs_rqst = temp;
75 	else
76 		timing->hs_rqst = max_t(s32, 0, temp - 2);
77 
78 	/* Calculate clk_zero after clk_prepare and hs_rqst */
79 	dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2);
80 
81 	temp = 105 * coeff + 12 * ui - 20 * coeff;
82 	tmax = S_DIV_ROUND_UP(temp, ui) - 2;
83 	tmin = S_DIV_ROUND_UP(60 * coeff, ui) - 2;
84 	timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
85 
86 	temp = 85 * coeff + 6 * ui;
87 	tmax = S_DIV_ROUND_UP(temp, ui) - 2;
88 	temp = 40 * coeff + 4 * ui;
89 	tmin = S_DIV_ROUND_UP(temp, ui) - 2;
90 	timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, true);
91 
92 	tmax = 255;
93 	temp = ((timing->hs_prepare >> 1) + 1) * 2 * ui + 2 * ui;
94 	temp = 145 * coeff + 10 * ui - temp;
95 	tmin = S_DIV_ROUND_UP(temp, ui) - 2;
96 	timing->hs_zero = linear_inter(tmax, tmin, pcnt2, 24, true);
97 
98 	temp = 105 * coeff + 12 * ui - 20 * coeff;
99 	tmax = S_DIV_ROUND_UP(temp, ui) - 2;
100 	temp = 60 * coeff + 4 * ui;
101 	tmin = DIV_ROUND_UP(temp, ui) - 2;
102 	timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
103 
104 	tmax = 255;
105 	tmin = S_DIV_ROUND_UP(100 * coeff, ui) - 2;
106 	timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, true);
107 
108 	tmax = 63;
109 	temp = ((timing->hs_exit >> 1) + 1) * 2 * ui;
110 	temp = 60 * coeff + 52 * ui - 24 * ui - temp;
111 	tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1;
112 	timing->shared_timings.clk_post = linear_inter(tmax, tmin, pcnt2, 0,
113 						       false);
114 	tmax = 63;
115 	temp = ((timing->clk_prepare >> 1) + 1) * 2 * ui;
116 	temp += ((timing->clk_zero >> 1) + 1) * 2 * ui;
117 	temp += 8 * ui + lpx;
118 	tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1;
119 	if (tmin > tmax) {
120 		temp = linear_inter(2 * tmax, tmin, pcnt2, 0, false);
121 		timing->shared_timings.clk_pre = temp >> 1;
122 		timing->shared_timings.clk_pre_inc_by_2 = true;
123 	} else {
124 		timing->shared_timings.clk_pre =
125 				linear_inter(tmax, tmin, pcnt2, 0, false);
126 		timing->shared_timings.clk_pre_inc_by_2 = false;
127 	}
128 
129 	timing->ta_go = 3;
130 	timing->ta_sure = 0;
131 	timing->ta_get = 4;
132 
133 	DBG("PHY timings: %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
134 		timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
135 		timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
136 		timing->clk_trail, timing->clk_prepare, timing->hs_exit,
137 		timing->hs_zero, timing->hs_prepare, timing->hs_trail,
138 		timing->hs_rqst);
139 
140 	return 0;
141 }
142 
143 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
144 				struct msm_dsi_phy_clk_request *clk_req)
145 {
146 	const unsigned long bit_rate = clk_req->bitclk_rate;
147 	const unsigned long esc_rate = clk_req->escclk_rate;
148 	s32 ui, ui_x8, lpx;
149 	s32 tmax, tmin;
150 	s32 pcnt0 = 50;
151 	s32 pcnt1 = 50;
152 	s32 pcnt2 = 10;
153 	s32 pcnt3 = 30;
154 	s32 pcnt4 = 10;
155 	s32 pcnt5 = 2;
156 	s32 coeff = 1000; /* Precision, should avoid overflow */
157 	s32 hb_en, hb_en_ckln, pd_ckln, pd;
158 	s32 val, val_ckln;
159 	s32 temp;
160 
161 	if (!bit_rate || !esc_rate)
162 		return -EINVAL;
163 
164 	timing->hs_halfbyte_en = 0;
165 	hb_en = 0;
166 	timing->hs_halfbyte_en_ckln = 0;
167 	hb_en_ckln = 0;
168 	timing->hs_prep_dly_ckln = (bit_rate > 100000000) ? 0 : 3;
169 	pd_ckln = timing->hs_prep_dly_ckln;
170 	timing->hs_prep_dly = (bit_rate > 120000000) ? 0 : 1;
171 	pd = timing->hs_prep_dly;
172 
173 	val = (hb_en << 2) + (pd << 1);
174 	val_ckln = (hb_en_ckln << 2) + (pd_ckln << 1);
175 
176 	ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
177 	ui_x8 = ui << 3;
178 	lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
179 
180 	temp = S_DIV_ROUND_UP(38 * coeff - val_ckln * ui, ui_x8);
181 	tmin = max_t(s32, temp, 0);
182 	temp = (95 * coeff - val_ckln * ui) / ui_x8;
183 	tmax = max_t(s32, temp, 0);
184 	timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
185 
186 	temp = 300 * coeff - ((timing->clk_prepare << 3) + val_ckln) * ui;
187 	tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;
188 	tmax = (tmin > 255) ? 511 : 255;
189 	timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
190 
191 	tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
192 	temp = 105 * coeff + 12 * ui - 20 * coeff;
193 	tmax = (temp + 3 * ui) / ui_x8;
194 	timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
195 
196 	temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui - val * ui, ui_x8);
197 	tmin = max_t(s32, temp, 0);
198 	temp = (85 * coeff + 6 * ui - val * ui) / ui_x8;
199 	tmax = max_t(s32, temp, 0);
200 	timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
201 
202 	temp = 145 * coeff + 10 * ui - ((timing->hs_prepare << 3) + val) * ui;
203 	tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;
204 	tmax = 255;
205 	timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
206 
207 	tmin = DIV_ROUND_UP(60 * coeff + 4 * ui + 3 * ui, ui_x8);
208 	temp = 105 * coeff + 12 * ui - 20 * coeff;
209 	tmax = (temp + 3 * ui) / ui_x8;
210 	timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
211 
212 	temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
213 	timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
214 
215 	tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
216 	tmax = 255;
217 	timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
218 
219 	temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui;
220 	timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
221 
222 	temp = 60 * coeff + 52 * ui - 43 * ui;
223 	tmin = DIV_ROUND_UP(temp, ui_x8) - 1;
224 	tmax = 63;
225 	timing->shared_timings.clk_post =
226 				linear_inter(tmax, tmin, pcnt2, 0, false);
227 
228 	temp = 8 * ui + ((timing->clk_prepare << 3) + val_ckln) * ui;
229 	temp += (((timing->clk_zero + 3) << 3) + 11 - (pd_ckln << 1)) * ui;
230 	temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
231 				(((timing->hs_rqst_ckln << 3) + 8) * ui);
232 	tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
233 	tmax = 63;
234 	if (tmin > tmax) {
235 		temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false);
236 		timing->shared_timings.clk_pre = temp >> 1;
237 		timing->shared_timings.clk_pre_inc_by_2 = 1;
238 	} else {
239 		timing->shared_timings.clk_pre =
240 				linear_inter(tmax, tmin, pcnt2, 0, false);
241 		timing->shared_timings.clk_pre_inc_by_2 = 0;
242 	}
243 
244 	timing->ta_go = 3;
245 	timing->ta_sure = 0;
246 	timing->ta_get = 4;
247 
248 	DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
249 	    timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
250 	    timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
251 	    timing->clk_trail, timing->clk_prepare, timing->hs_exit,
252 	    timing->hs_zero, timing->hs_prepare, timing->hs_trail,
253 	    timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en,
254 	    timing->hs_halfbyte_en_ckln, timing->hs_prep_dly,
255 	    timing->hs_prep_dly_ckln);
256 
257 	return 0;
258 }
259 
260 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
261 	struct msm_dsi_phy_clk_request *clk_req)
262 {
263 	const unsigned long bit_rate = clk_req->bitclk_rate;
264 	const unsigned long esc_rate = clk_req->escclk_rate;
265 	s32 ui, ui_x8, lpx;
266 	s32 tmax, tmin;
267 	s32 pcnt0 = 50;
268 	s32 pcnt1 = 50;
269 	s32 pcnt2 = 10;
270 	s32 pcnt3 = 30;
271 	s32 pcnt4 = 10;
272 	s32 pcnt5 = 2;
273 	s32 coeff = 1000; /* Precision, should avoid overflow */
274 	s32 hb_en, hb_en_ckln;
275 	s32 temp;
276 
277 	if (!bit_rate || !esc_rate)
278 		return -EINVAL;
279 
280 	timing->hs_halfbyte_en = 0;
281 	hb_en = 0;
282 	timing->hs_halfbyte_en_ckln = 0;
283 	hb_en_ckln = 0;
284 
285 	ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
286 	ui_x8 = ui << 3;
287 	lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
288 
289 	temp = S_DIV_ROUND_UP(38 * coeff, ui_x8);
290 	tmin = max_t(s32, temp, 0);
291 	temp = (95 * coeff) / ui_x8;
292 	tmax = max_t(s32, temp, 0);
293 	timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
294 
295 	temp = 300 * coeff - (timing->clk_prepare << 3) * ui;
296 	tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
297 	tmax = (tmin > 255) ? 511 : 255;
298 	timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
299 
300 	tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
301 	temp = 105 * coeff + 12 * ui - 20 * coeff;
302 	tmax = (temp + 3 * ui) / ui_x8;
303 	timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
304 
305 	temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui, ui_x8);
306 	tmin = max_t(s32, temp, 0);
307 	temp = (85 * coeff + 6 * ui) / ui_x8;
308 	tmax = max_t(s32, temp, 0);
309 	timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
310 
311 	temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;
312 	tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
313 	tmax = 255;
314 	timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
315 
316 	tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1;
317 	temp = 105 * coeff + 12 * ui - 20 * coeff;
318 	tmax = (temp / ui_x8) - 1;
319 	timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
320 
321 	temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
322 	timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
323 
324 	tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
325 	tmax = 255;
326 	timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
327 
328 	temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui;
329 	timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
330 
331 	temp = 60 * coeff + 52 * ui - 43 * ui;
332 	tmin = DIV_ROUND_UP(temp, ui_x8) - 1;
333 	tmax = 63;
334 	timing->shared_timings.clk_post =
335 		linear_inter(tmax, tmin, pcnt2, 0, false);
336 
337 	temp = 8 * ui + (timing->clk_prepare << 3) * ui;
338 	temp += (((timing->clk_zero + 3) << 3) + 11) * ui;
339 	temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
340 		(((timing->hs_rqst_ckln << 3) + 8) * ui);
341 	tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
342 	tmax = 63;
343 	if (tmin > tmax) {
344 		temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false);
345 		timing->shared_timings.clk_pre = temp >> 1;
346 		timing->shared_timings.clk_pre_inc_by_2 = 1;
347 	} else {
348 		timing->shared_timings.clk_pre =
349 			linear_inter(tmax, tmin, pcnt2, 0, false);
350 			timing->shared_timings.clk_pre_inc_by_2 = 0;
351 	}
352 
353 	timing->ta_go = 3;
354 	timing->ta_sure = 0;
355 	timing->ta_get = 4;
356 
357 	DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
358 		timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
359 		timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
360 		timing->clk_trail, timing->clk_prepare, timing->hs_exit,
361 		timing->hs_zero, timing->hs_prepare, timing->hs_trail,
362 		timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en,
363 		timing->hs_halfbyte_en_ckln, timing->hs_prep_dly,
364 		timing->hs_prep_dly_ckln);
365 
366 	return 0;
367 }
368 
369 void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
370 				u32 bit_mask)
371 {
372 	int phy_id = phy->id;
373 	u32 val;
374 
375 	if ((phy_id >= DSI_MAX) || (pll_id >= DSI_MAX))
376 		return;
377 
378 	val = dsi_phy_read(phy->base + reg);
379 
380 	if (phy->cfg->src_pll_truthtable[phy_id][pll_id])
381 		dsi_phy_write(phy->base + reg, val | bit_mask);
382 	else
383 		dsi_phy_write(phy->base + reg, val & (~bit_mask));
384 }
385 
386 static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)
387 {
388 	struct regulator_bulk_data *s = phy->supplies;
389 	const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
390 	struct device *dev = &phy->pdev->dev;
391 	int num = phy->cfg->reg_cfg.num;
392 	int i, ret;
393 
394 	for (i = 0; i < num; i++)
395 		s[i].supply = regs[i].name;
396 
397 	ret = devm_regulator_bulk_get(dev, num, s);
398 	if (ret < 0) {
399 		DRM_DEV_ERROR(dev, "%s: failed to init regulator, ret=%d\n",
400 						__func__, ret);
401 		return ret;
402 	}
403 
404 	return 0;
405 }
406 
407 static void dsi_phy_regulator_disable(struct msm_dsi_phy *phy)
408 {
409 	struct regulator_bulk_data *s = phy->supplies;
410 	const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
411 	int num = phy->cfg->reg_cfg.num;
412 	int i;
413 
414 	DBG("");
415 	for (i = num - 1; i >= 0; i--)
416 		if (regs[i].disable_load >= 0)
417 			regulator_set_load(s[i].consumer, regs[i].disable_load);
418 
419 	regulator_bulk_disable(num, s);
420 }
421 
422 static int dsi_phy_regulator_enable(struct msm_dsi_phy *phy)
423 {
424 	struct regulator_bulk_data *s = phy->supplies;
425 	const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
426 	struct device *dev = &phy->pdev->dev;
427 	int num = phy->cfg->reg_cfg.num;
428 	int ret, i;
429 
430 	DBG("");
431 	for (i = 0; i < num; i++) {
432 		if (regs[i].enable_load >= 0) {
433 			ret = regulator_set_load(s[i].consumer,
434 							regs[i].enable_load);
435 			if (ret < 0) {
436 				DRM_DEV_ERROR(dev,
437 					"regulator %d set op mode failed, %d\n",
438 					i, ret);
439 				goto fail;
440 			}
441 		}
442 	}
443 
444 	ret = regulator_bulk_enable(num, s);
445 	if (ret < 0) {
446 		DRM_DEV_ERROR(dev, "regulator enable failed, %d\n", ret);
447 		goto fail;
448 	}
449 
450 	return 0;
451 
452 fail:
453 	for (i--; i >= 0; i--)
454 		regulator_set_load(s[i].consumer, regs[i].disable_load);
455 	return ret;
456 }
457 
458 static int dsi_phy_enable_resource(struct msm_dsi_phy *phy)
459 {
460 	struct device *dev = &phy->pdev->dev;
461 	int ret;
462 
463 	pm_runtime_get_sync(dev);
464 
465 	ret = clk_prepare_enable(phy->ahb_clk);
466 	if (ret) {
467 		DRM_DEV_ERROR(dev, "%s: can't enable ahb clk, %d\n", __func__, ret);
468 		pm_runtime_put_sync(dev);
469 	}
470 
471 	return ret;
472 }
473 
474 static void dsi_phy_disable_resource(struct msm_dsi_phy *phy)
475 {
476 	clk_disable_unprepare(phy->ahb_clk);
477 	pm_runtime_put_autosuspend(&phy->pdev->dev);
478 }
479 
480 static const struct of_device_id dsi_phy_dt_match[] = {
481 #ifdef CONFIG_DRM_MSM_DSI_28NM_PHY
482 	{ .compatible = "qcom,dsi-phy-28nm-hpm",
483 	  .data = &dsi_phy_28nm_hpm_cfgs },
484 	{ .compatible = "qcom,dsi-phy-28nm-lp",
485 	  .data = &dsi_phy_28nm_lp_cfgs },
486 #endif
487 #ifdef CONFIG_DRM_MSM_DSI_20NM_PHY
488 	{ .compatible = "qcom,dsi-phy-20nm",
489 	  .data = &dsi_phy_20nm_cfgs },
490 #endif
491 #ifdef CONFIG_DRM_MSM_DSI_28NM_8960_PHY
492 	{ .compatible = "qcom,dsi-phy-28nm-8960",
493 	  .data = &dsi_phy_28nm_8960_cfgs },
494 #endif
495 #ifdef CONFIG_DRM_MSM_DSI_14NM_PHY
496 	{ .compatible = "qcom,dsi-phy-14nm",
497 	  .data = &dsi_phy_14nm_cfgs },
498 #endif
499 #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
500 	{ .compatible = "qcom,dsi-phy-10nm",
501 	  .data = &dsi_phy_10nm_cfgs },
502 	{ .compatible = "qcom,dsi-phy-10nm-8998",
503 	  .data = &dsi_phy_10nm_8998_cfgs },
504 #endif
505 	{}
506 };
507 
508 /*
509  * Currently, we only support one SoC for each PHY type. When we have multiple
510  * SoCs for the same PHY, we can try to make the index searching a bit more
511  * clever.
512  */
513 static int dsi_phy_get_id(struct msm_dsi_phy *phy)
514 {
515 	struct platform_device *pdev = phy->pdev;
516 	const struct msm_dsi_phy_cfg *cfg = phy->cfg;
517 	struct resource *res;
518 	int i;
519 
520 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_phy");
521 	if (!res)
522 		return -EINVAL;
523 
524 	for (i = 0; i < cfg->num_dsi_phy; i++) {
525 		if (cfg->io_start[i] == res->start)
526 			return i;
527 	}
528 
529 	return -EINVAL;
530 }
531 
532 int msm_dsi_phy_init_common(struct msm_dsi_phy *phy)
533 {
534 	struct platform_device *pdev = phy->pdev;
535 	int ret = 0;
536 
537 	phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",
538 				"DSI_PHY_REG");
539 	if (IS_ERR(phy->reg_base)) {
540 		DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n",
541 			__func__);
542 		ret = -ENOMEM;
543 		goto fail;
544 	}
545 
546 fail:
547 	return ret;
548 }
549 
550 static int dsi_phy_driver_probe(struct platform_device *pdev)
551 {
552 	struct msm_dsi_phy *phy;
553 	struct device *dev = &pdev->dev;
554 	const struct of_device_id *match;
555 	int ret;
556 
557 	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
558 	if (!phy)
559 		return -ENOMEM;
560 
561 	match = of_match_node(dsi_phy_dt_match, dev->of_node);
562 	if (!match)
563 		return -ENODEV;
564 
565 	phy->cfg = match->data;
566 	phy->pdev = pdev;
567 
568 	phy->id = dsi_phy_get_id(phy);
569 	if (phy->id < 0) {
570 		ret = phy->id;
571 		DRM_DEV_ERROR(dev, "%s: couldn't identify PHY index, %d\n",
572 			__func__, ret);
573 		goto fail;
574 	}
575 
576 	phy->regulator_ldo_mode = of_property_read_bool(dev->of_node,
577 				"qcom,dsi-phy-regulator-ldo-mode");
578 
579 	phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
580 	if (IS_ERR(phy->base)) {
581 		DRM_DEV_ERROR(dev, "%s: failed to map phy base\n", __func__);
582 		ret = -ENOMEM;
583 		goto fail;
584 	}
585 
586 	ret = dsi_phy_regulator_init(phy);
587 	if (ret) {
588 		DRM_DEV_ERROR(dev, "%s: failed to init regulator\n", __func__);
589 		goto fail;
590 	}
591 
592 	phy->ahb_clk = msm_clk_get(pdev, "iface");
593 	if (IS_ERR(phy->ahb_clk)) {
594 		DRM_DEV_ERROR(dev, "%s: Unable to get ahb clk\n", __func__);
595 		ret = PTR_ERR(phy->ahb_clk);
596 		goto fail;
597 	}
598 
599 	if (phy->cfg->ops.init) {
600 		ret = phy->cfg->ops.init(phy);
601 		if (ret)
602 			goto fail;
603 	}
604 
605 	/* PLL init will call into clk_register which requires
606 	 * register access, so we need to enable power and ahb clock.
607 	 */
608 	ret = dsi_phy_enable_resource(phy);
609 	if (ret)
610 		goto fail;
611 
612 	phy->pll = msm_dsi_pll_init(pdev, phy->cfg->type, phy->id);
613 	if (IS_ERR_OR_NULL(phy->pll)) {
614 		DRM_DEV_INFO(dev,
615 			"%s: pll init failed: %ld, need separate pll clk driver\n",
616 			__func__, PTR_ERR(phy->pll));
617 		phy->pll = NULL;
618 	}
619 
620 	dsi_phy_disable_resource(phy);
621 
622 	platform_set_drvdata(pdev, phy);
623 
624 	return 0;
625 
626 fail:
627 	return ret;
628 }
629 
630 static int dsi_phy_driver_remove(struct platform_device *pdev)
631 {
632 	struct msm_dsi_phy *phy = platform_get_drvdata(pdev);
633 
634 	if (phy && phy->pll) {
635 		msm_dsi_pll_destroy(phy->pll);
636 		phy->pll = NULL;
637 	}
638 
639 	platform_set_drvdata(pdev, NULL);
640 
641 	return 0;
642 }
643 
644 static struct platform_driver dsi_phy_platform_driver = {
645 	.probe      = dsi_phy_driver_probe,
646 	.remove     = dsi_phy_driver_remove,
647 	.driver     = {
648 		.name   = "msm_dsi_phy",
649 		.of_match_table = dsi_phy_dt_match,
650 	},
651 };
652 
653 void __init msm_dsi_phy_driver_register(void)
654 {
655 	platform_driver_register(&dsi_phy_platform_driver);
656 }
657 
658 void __exit msm_dsi_phy_driver_unregister(void)
659 {
660 	platform_driver_unregister(&dsi_phy_platform_driver);
661 }
662 
663 int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
664 			struct msm_dsi_phy_clk_request *clk_req)
665 {
666 	struct device *dev = &phy->pdev->dev;
667 	int ret;
668 
669 	if (!phy || !phy->cfg->ops.enable)
670 		return -EINVAL;
671 
672 	ret = dsi_phy_enable_resource(phy);
673 	if (ret) {
674 		DRM_DEV_ERROR(dev, "%s: resource enable failed, %d\n",
675 			__func__, ret);
676 		goto res_en_fail;
677 	}
678 
679 	ret = dsi_phy_regulator_enable(phy);
680 	if (ret) {
681 		DRM_DEV_ERROR(dev, "%s: regulator enable failed, %d\n",
682 			__func__, ret);
683 		goto reg_en_fail;
684 	}
685 
686 	ret = phy->cfg->ops.enable(phy, src_pll_id, clk_req);
687 	if (ret) {
688 		DRM_DEV_ERROR(dev, "%s: phy enable failed, %d\n", __func__, ret);
689 		goto phy_en_fail;
690 	}
691 
692 	/*
693 	 * Resetting DSI PHY silently changes its PLL registers to reset status,
694 	 * which will confuse clock driver and result in wrong output rate of
695 	 * link clocks. Restore PLL status if its PLL is being used as clock
696 	 * source.
697 	 */
698 	if (phy->usecase != MSM_DSI_PHY_SLAVE) {
699 		ret = msm_dsi_pll_restore_state(phy->pll);
700 		if (ret) {
701 			DRM_DEV_ERROR(dev, "%s: failed to restore pll state, %d\n",
702 				__func__, ret);
703 			goto pll_restor_fail;
704 		}
705 	}
706 
707 	return 0;
708 
709 pll_restor_fail:
710 	if (phy->cfg->ops.disable)
711 		phy->cfg->ops.disable(phy);
712 phy_en_fail:
713 	dsi_phy_regulator_disable(phy);
714 reg_en_fail:
715 	dsi_phy_disable_resource(phy);
716 res_en_fail:
717 	return ret;
718 }
719 
720 void msm_dsi_phy_disable(struct msm_dsi_phy *phy)
721 {
722 	if (!phy || !phy->cfg->ops.disable)
723 		return;
724 
725 	/* Save PLL status if it is a clock source */
726 	if (phy->usecase != MSM_DSI_PHY_SLAVE)
727 		msm_dsi_pll_save_state(phy->pll);
728 
729 	phy->cfg->ops.disable(phy);
730 
731 	dsi_phy_regulator_disable(phy);
732 	dsi_phy_disable_resource(phy);
733 }
734 
735 void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
736 			struct msm_dsi_phy_shared_timings *shared_timings)
737 {
738 	memcpy(shared_timings, &phy->timing.shared_timings,
739 	       sizeof(*shared_timings));
740 }
741 
742 struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy)
743 {
744 	if (!phy)
745 		return NULL;
746 
747 	return phy->pll;
748 }
749 
750 void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
751 			     enum msm_dsi_phy_usecase uc)
752 {
753 	if (phy)
754 		phy->usecase = uc;
755 }
756