1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/platform_device.h> 7 8 #include "dsi_phy.h" 9 10 #define S_DIV_ROUND_UP(n, d) \ 11 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d))) 12 13 static inline s32 linear_inter(s32 tmax, s32 tmin, s32 percent, 14 s32 min_result, bool even) 15 { 16 s32 v; 17 18 v = (tmax - tmin) * percent; 19 v = S_DIV_ROUND_UP(v, 100) + tmin; 20 if (even && (v & 0x1)) 21 return max_t(s32, min_result, v - 1); 22 else 23 return max_t(s32, min_result, v); 24 } 25 26 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing, 27 s32 ui, s32 coeff, s32 pcnt) 28 { 29 s32 tmax, tmin, clk_z; 30 s32 temp; 31 32 /* reset */ 33 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; 34 tmin = S_DIV_ROUND_UP(temp, ui) - 2; 35 if (tmin > 255) { 36 tmax = 511; 37 clk_z = linear_inter(2 * tmin, tmin, pcnt, 0, true); 38 } else { 39 tmax = 255; 40 clk_z = linear_inter(tmax, tmin, pcnt, 0, true); 41 } 42 43 /* adjust */ 44 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; 45 timing->clk_zero = clk_z + 8 - temp; 46 } 47 48 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, 49 struct msm_dsi_phy_clk_request *clk_req) 50 { 51 const unsigned long bit_rate = clk_req->bitclk_rate; 52 const unsigned long esc_rate = clk_req->escclk_rate; 53 s32 ui, lpx; 54 s32 tmax, tmin; 55 s32 pcnt0 = 10; 56 s32 pcnt1 = (bit_rate > 1200000000) ? 15 : 10; 57 s32 pcnt2 = 10; 58 s32 pcnt3 = (bit_rate > 180000000) ? 10 : 40; 59 s32 coeff = 1000; /* Precision, should avoid overflow */ 60 s32 temp; 61 62 if (!bit_rate || !esc_rate) 63 return -EINVAL; 64 65 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000); 66 lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000); 67 68 tmax = S_DIV_ROUND_UP(95 * coeff, ui) - 2; 69 tmin = S_DIV_ROUND_UP(38 * coeff, ui) - 2; 70 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true); 71 72 temp = lpx / ui; 73 if (temp & 0x1) 74 timing->hs_rqst = temp; 75 else 76 timing->hs_rqst = max_t(s32, 0, temp - 2); 77 78 /* Calculate clk_zero after clk_prepare and hs_rqst */ 79 dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2); 80 81 temp = 105 * coeff + 12 * ui - 20 * coeff; 82 tmax = S_DIV_ROUND_UP(temp, ui) - 2; 83 tmin = S_DIV_ROUND_UP(60 * coeff, ui) - 2; 84 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true); 85 86 temp = 85 * coeff + 6 * ui; 87 tmax = S_DIV_ROUND_UP(temp, ui) - 2; 88 temp = 40 * coeff + 4 * ui; 89 tmin = S_DIV_ROUND_UP(temp, ui) - 2; 90 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, true); 91 92 tmax = 255; 93 temp = ((timing->hs_prepare >> 1) + 1) * 2 * ui + 2 * ui; 94 temp = 145 * coeff + 10 * ui - temp; 95 tmin = S_DIV_ROUND_UP(temp, ui) - 2; 96 timing->hs_zero = linear_inter(tmax, tmin, pcnt2, 24, true); 97 98 temp = 105 * coeff + 12 * ui - 20 * coeff; 99 tmax = S_DIV_ROUND_UP(temp, ui) - 2; 100 temp = 60 * coeff + 4 * ui; 101 tmin = DIV_ROUND_UP(temp, ui) - 2; 102 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, true); 103 104 tmax = 255; 105 tmin = S_DIV_ROUND_UP(100 * coeff, ui) - 2; 106 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, true); 107 108 tmax = 63; 109 temp = ((timing->hs_exit >> 1) + 1) * 2 * ui; 110 temp = 60 * coeff + 52 * ui - 24 * ui - temp; 111 tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1; 112 timing->shared_timings.clk_post = linear_inter(tmax, tmin, pcnt2, 0, 113 false); 114 tmax = 63; 115 temp = ((timing->clk_prepare >> 1) + 1) * 2 * ui; 116 temp += ((timing->clk_zero >> 1) + 1) * 2 * ui; 117 temp += 8 * ui + lpx; 118 tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1; 119 if (tmin > tmax) { 120 temp = linear_inter(2 * tmax, tmin, pcnt2, 0, false); 121 timing->shared_timings.clk_pre = temp >> 1; 122 timing->shared_timings.clk_pre_inc_by_2 = true; 123 } else { 124 timing->shared_timings.clk_pre = 125 linear_inter(tmax, tmin, pcnt2, 0, false); 126 timing->shared_timings.clk_pre_inc_by_2 = false; 127 } 128 129 timing->ta_go = 3; 130 timing->ta_sure = 0; 131 timing->ta_get = 4; 132 133 DBG("PHY timings: %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d", 134 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, 135 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, 136 timing->clk_trail, timing->clk_prepare, timing->hs_exit, 137 timing->hs_zero, timing->hs_prepare, timing->hs_trail, 138 timing->hs_rqst); 139 140 return 0; 141 } 142 143 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing, 144 struct msm_dsi_phy_clk_request *clk_req) 145 { 146 const unsigned long bit_rate = clk_req->bitclk_rate; 147 const unsigned long esc_rate = clk_req->escclk_rate; 148 s32 ui, ui_x8; 149 s32 tmax, tmin; 150 s32 pcnt0 = 50; 151 s32 pcnt1 = 50; 152 s32 pcnt2 = 10; 153 s32 pcnt3 = 30; 154 s32 pcnt4 = 10; 155 s32 pcnt5 = 2; 156 s32 coeff = 1000; /* Precision, should avoid overflow */ 157 s32 hb_en, hb_en_ckln, pd_ckln, pd; 158 s32 val, val_ckln; 159 s32 temp; 160 161 if (!bit_rate || !esc_rate) 162 return -EINVAL; 163 164 timing->hs_halfbyte_en = 0; 165 hb_en = 0; 166 timing->hs_halfbyte_en_ckln = 0; 167 hb_en_ckln = 0; 168 timing->hs_prep_dly_ckln = (bit_rate > 100000000) ? 0 : 3; 169 pd_ckln = timing->hs_prep_dly_ckln; 170 timing->hs_prep_dly = (bit_rate > 120000000) ? 0 : 1; 171 pd = timing->hs_prep_dly; 172 173 val = (hb_en << 2) + (pd << 1); 174 val_ckln = (hb_en_ckln << 2) + (pd_ckln << 1); 175 176 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000); 177 ui_x8 = ui << 3; 178 179 temp = S_DIV_ROUND_UP(38 * coeff - val_ckln * ui, ui_x8); 180 tmin = max_t(s32, temp, 0); 181 temp = (95 * coeff - val_ckln * ui) / ui_x8; 182 tmax = max_t(s32, temp, 0); 183 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false); 184 185 temp = 300 * coeff - ((timing->clk_prepare << 3) + val_ckln) * ui; 186 tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3; 187 tmax = (tmin > 255) ? 511 : 255; 188 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false); 189 190 tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8); 191 temp = 105 * coeff + 12 * ui - 20 * coeff; 192 tmax = (temp + 3 * ui) / ui_x8; 193 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false); 194 195 temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui - val * ui, ui_x8); 196 tmin = max_t(s32, temp, 0); 197 temp = (85 * coeff + 6 * ui - val * ui) / ui_x8; 198 tmax = max_t(s32, temp, 0); 199 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false); 200 201 temp = 145 * coeff + 10 * ui - ((timing->hs_prepare << 3) + val) * ui; 202 tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3; 203 tmax = 255; 204 timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false); 205 206 tmin = DIV_ROUND_UP(60 * coeff + 4 * ui + 3 * ui, ui_x8); 207 temp = 105 * coeff + 12 * ui - 20 * coeff; 208 tmax = (temp + 3 * ui) / ui_x8; 209 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false); 210 211 temp = 50 * coeff + ((hb_en << 2) - 8) * ui; 212 timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8); 213 214 tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1; 215 tmax = 255; 216 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false); 217 218 temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui; 219 timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8); 220 221 temp = 60 * coeff + 52 * ui - 43 * ui; 222 tmin = DIV_ROUND_UP(temp, ui_x8) - 1; 223 tmax = 63; 224 timing->shared_timings.clk_post = 225 linear_inter(tmax, tmin, pcnt2, 0, false); 226 227 temp = 8 * ui + ((timing->clk_prepare << 3) + val_ckln) * ui; 228 temp += (((timing->clk_zero + 3) << 3) + 11 - (pd_ckln << 1)) * ui; 229 temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) : 230 (((timing->hs_rqst_ckln << 3) + 8) * ui); 231 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; 232 tmax = 63; 233 if (tmin > tmax) { 234 temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false); 235 timing->shared_timings.clk_pre = temp >> 1; 236 timing->shared_timings.clk_pre_inc_by_2 = 1; 237 } else { 238 timing->shared_timings.clk_pre = 239 linear_inter(tmax, tmin, pcnt2, 0, false); 240 timing->shared_timings.clk_pre_inc_by_2 = 0; 241 } 242 243 timing->ta_go = 3; 244 timing->ta_sure = 0; 245 timing->ta_get = 4; 246 247 DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d", 248 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, 249 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, 250 timing->clk_trail, timing->clk_prepare, timing->hs_exit, 251 timing->hs_zero, timing->hs_prepare, timing->hs_trail, 252 timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en, 253 timing->hs_halfbyte_en_ckln, timing->hs_prep_dly, 254 timing->hs_prep_dly_ckln); 255 256 return 0; 257 } 258 259 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing, 260 struct msm_dsi_phy_clk_request *clk_req) 261 { 262 const unsigned long bit_rate = clk_req->bitclk_rate; 263 const unsigned long esc_rate = clk_req->escclk_rate; 264 s32 ui, ui_x8; 265 s32 tmax, tmin; 266 s32 pcnt0 = 50; 267 s32 pcnt1 = 50; 268 s32 pcnt2 = 10; 269 s32 pcnt3 = 30; 270 s32 pcnt4 = 10; 271 s32 pcnt5 = 2; 272 s32 coeff = 1000; /* Precision, should avoid overflow */ 273 s32 hb_en, hb_en_ckln; 274 s32 temp; 275 276 if (!bit_rate || !esc_rate) 277 return -EINVAL; 278 279 timing->hs_halfbyte_en = 0; 280 hb_en = 0; 281 timing->hs_halfbyte_en_ckln = 0; 282 hb_en_ckln = 0; 283 284 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000); 285 ui_x8 = ui << 3; 286 287 temp = S_DIV_ROUND_UP(38 * coeff, ui_x8); 288 tmin = max_t(s32, temp, 0); 289 temp = (95 * coeff) / ui_x8; 290 tmax = max_t(s32, temp, 0); 291 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false); 292 293 temp = 300 * coeff - (timing->clk_prepare << 3) * ui; 294 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; 295 tmax = (tmin > 255) ? 511 : 255; 296 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false); 297 298 tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8); 299 temp = 105 * coeff + 12 * ui - 20 * coeff; 300 tmax = (temp + 3 * ui) / ui_x8; 301 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false); 302 303 temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui, ui_x8); 304 tmin = max_t(s32, temp, 0); 305 temp = (85 * coeff + 6 * ui) / ui_x8; 306 tmax = max_t(s32, temp, 0); 307 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false); 308 309 temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui; 310 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; 311 tmax = 255; 312 timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false); 313 314 tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1; 315 temp = 105 * coeff + 12 * ui - 20 * coeff; 316 tmax = (temp / ui_x8) - 1; 317 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false); 318 319 temp = 50 * coeff + ((hb_en << 2) - 8) * ui; 320 timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8); 321 322 tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1; 323 tmax = 255; 324 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false); 325 326 temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui; 327 timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8); 328 329 temp = 60 * coeff + 52 * ui - 43 * ui; 330 tmin = DIV_ROUND_UP(temp, ui_x8) - 1; 331 tmax = 63; 332 timing->shared_timings.clk_post = 333 linear_inter(tmax, tmin, pcnt2, 0, false); 334 335 temp = 8 * ui + (timing->clk_prepare << 3) * ui; 336 temp += (((timing->clk_zero + 3) << 3) + 11) * ui; 337 temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) : 338 (((timing->hs_rqst_ckln << 3) + 8) * ui); 339 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; 340 tmax = 63; 341 if (tmin > tmax) { 342 temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false); 343 timing->shared_timings.clk_pre = temp >> 1; 344 timing->shared_timings.clk_pre_inc_by_2 = 1; 345 } else { 346 timing->shared_timings.clk_pre = 347 linear_inter(tmax, tmin, pcnt2, 0, false); 348 timing->shared_timings.clk_pre_inc_by_2 = 0; 349 } 350 351 timing->ta_go = 3; 352 timing->ta_sure = 0; 353 timing->ta_get = 4; 354 355 DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d", 356 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, 357 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, 358 timing->clk_trail, timing->clk_prepare, timing->hs_exit, 359 timing->hs_zero, timing->hs_prepare, timing->hs_trail, 360 timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en, 361 timing->hs_halfbyte_en_ckln, timing->hs_prep_dly, 362 timing->hs_prep_dly_ckln); 363 364 return 0; 365 } 366 367 void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg, 368 u32 bit_mask) 369 { 370 int phy_id = phy->id; 371 u32 val; 372 373 if ((phy_id >= DSI_MAX) || (pll_id >= DSI_MAX)) 374 return; 375 376 val = dsi_phy_read(phy->base + reg); 377 378 if (phy->cfg->src_pll_truthtable[phy_id][pll_id]) 379 dsi_phy_write(phy->base + reg, val | bit_mask); 380 else 381 dsi_phy_write(phy->base + reg, val & (~bit_mask)); 382 } 383 384 static int dsi_phy_regulator_init(struct msm_dsi_phy *phy) 385 { 386 struct regulator_bulk_data *s = phy->supplies; 387 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs; 388 struct device *dev = &phy->pdev->dev; 389 int num = phy->cfg->reg_cfg.num; 390 int i, ret; 391 392 for (i = 0; i < num; i++) 393 s[i].supply = regs[i].name; 394 395 ret = devm_regulator_bulk_get(dev, num, s); 396 if (ret < 0) { 397 if (ret != -EPROBE_DEFER) { 398 DRM_DEV_ERROR(dev, 399 "%s: failed to init regulator, ret=%d\n", 400 __func__, ret); 401 } 402 403 return ret; 404 } 405 406 return 0; 407 } 408 409 static void dsi_phy_regulator_disable(struct msm_dsi_phy *phy) 410 { 411 struct regulator_bulk_data *s = phy->supplies; 412 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs; 413 int num = phy->cfg->reg_cfg.num; 414 int i; 415 416 DBG(""); 417 for (i = num - 1; i >= 0; i--) 418 if (regs[i].disable_load >= 0) 419 regulator_set_load(s[i].consumer, regs[i].disable_load); 420 421 regulator_bulk_disable(num, s); 422 } 423 424 static int dsi_phy_regulator_enable(struct msm_dsi_phy *phy) 425 { 426 struct regulator_bulk_data *s = phy->supplies; 427 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs; 428 struct device *dev = &phy->pdev->dev; 429 int num = phy->cfg->reg_cfg.num; 430 int ret, i; 431 432 DBG(""); 433 for (i = 0; i < num; i++) { 434 if (regs[i].enable_load >= 0) { 435 ret = regulator_set_load(s[i].consumer, 436 regs[i].enable_load); 437 if (ret < 0) { 438 DRM_DEV_ERROR(dev, 439 "regulator %d set op mode failed, %d\n", 440 i, ret); 441 goto fail; 442 } 443 } 444 } 445 446 ret = regulator_bulk_enable(num, s); 447 if (ret < 0) { 448 DRM_DEV_ERROR(dev, "regulator enable failed, %d\n", ret); 449 goto fail; 450 } 451 452 return 0; 453 454 fail: 455 for (i--; i >= 0; i--) 456 regulator_set_load(s[i].consumer, regs[i].disable_load); 457 return ret; 458 } 459 460 static int dsi_phy_enable_resource(struct msm_dsi_phy *phy) 461 { 462 struct device *dev = &phy->pdev->dev; 463 int ret; 464 465 pm_runtime_get_sync(dev); 466 467 ret = clk_prepare_enable(phy->ahb_clk); 468 if (ret) { 469 DRM_DEV_ERROR(dev, "%s: can't enable ahb clk, %d\n", __func__, ret); 470 pm_runtime_put_sync(dev); 471 } 472 473 return ret; 474 } 475 476 static void dsi_phy_disable_resource(struct msm_dsi_phy *phy) 477 { 478 clk_disable_unprepare(phy->ahb_clk); 479 pm_runtime_put_autosuspend(&phy->pdev->dev); 480 } 481 482 static const struct of_device_id dsi_phy_dt_match[] = { 483 #ifdef CONFIG_DRM_MSM_DSI_28NM_PHY 484 { .compatible = "qcom,dsi-phy-28nm-hpm", 485 .data = &dsi_phy_28nm_hpm_cfgs }, 486 { .compatible = "qcom,dsi-phy-28nm-hpm-fam-b", 487 .data = &dsi_phy_28nm_hpm_famb_cfgs }, 488 { .compatible = "qcom,dsi-phy-28nm-lp", 489 .data = &dsi_phy_28nm_lp_cfgs }, 490 #endif 491 #ifdef CONFIG_DRM_MSM_DSI_20NM_PHY 492 { .compatible = "qcom,dsi-phy-20nm", 493 .data = &dsi_phy_20nm_cfgs }, 494 #endif 495 #ifdef CONFIG_DRM_MSM_DSI_28NM_8960_PHY 496 { .compatible = "qcom,dsi-phy-28nm-8960", 497 .data = &dsi_phy_28nm_8960_cfgs }, 498 #endif 499 #ifdef CONFIG_DRM_MSM_DSI_14NM_PHY 500 { .compatible = "qcom,dsi-phy-14nm", 501 .data = &dsi_phy_14nm_cfgs }, 502 { .compatible = "qcom,dsi-phy-14nm-660", 503 .data = &dsi_phy_14nm_660_cfgs }, 504 #endif 505 #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY 506 { .compatible = "qcom,dsi-phy-10nm", 507 .data = &dsi_phy_10nm_cfgs }, 508 { .compatible = "qcom,dsi-phy-10nm-8998", 509 .data = &dsi_phy_10nm_8998_cfgs }, 510 #endif 511 {} 512 }; 513 514 /* 515 * Currently, we only support one SoC for each PHY type. When we have multiple 516 * SoCs for the same PHY, we can try to make the index searching a bit more 517 * clever. 518 */ 519 static int dsi_phy_get_id(struct msm_dsi_phy *phy) 520 { 521 struct platform_device *pdev = phy->pdev; 522 const struct msm_dsi_phy_cfg *cfg = phy->cfg; 523 struct resource *res; 524 int i; 525 526 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_phy"); 527 if (!res) 528 return -EINVAL; 529 530 for (i = 0; i < cfg->num_dsi_phy; i++) { 531 if (cfg->io_start[i] == res->start) 532 return i; 533 } 534 535 return -EINVAL; 536 } 537 538 int msm_dsi_phy_init_common(struct msm_dsi_phy *phy) 539 { 540 struct platform_device *pdev = phy->pdev; 541 int ret = 0; 542 543 phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", 544 "DSI_PHY_REG"); 545 if (IS_ERR(phy->reg_base)) { 546 DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n", 547 __func__); 548 ret = -ENOMEM; 549 goto fail; 550 } 551 552 fail: 553 return ret; 554 } 555 556 static int dsi_phy_driver_probe(struct platform_device *pdev) 557 { 558 struct msm_dsi_phy *phy; 559 struct device *dev = &pdev->dev; 560 const struct of_device_id *match; 561 int ret; 562 563 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); 564 if (!phy) 565 return -ENOMEM; 566 567 match = of_match_node(dsi_phy_dt_match, dev->of_node); 568 if (!match) 569 return -ENODEV; 570 571 phy->cfg = match->data; 572 phy->pdev = pdev; 573 574 phy->id = dsi_phy_get_id(phy); 575 if (phy->id < 0) { 576 ret = phy->id; 577 DRM_DEV_ERROR(dev, "%s: couldn't identify PHY index, %d\n", 578 __func__, ret); 579 goto fail; 580 } 581 582 phy->regulator_ldo_mode = of_property_read_bool(dev->of_node, 583 "qcom,dsi-phy-regulator-ldo-mode"); 584 585 phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); 586 if (IS_ERR(phy->base)) { 587 DRM_DEV_ERROR(dev, "%s: failed to map phy base\n", __func__); 588 ret = -ENOMEM; 589 goto fail; 590 } 591 592 ret = dsi_phy_regulator_init(phy); 593 if (ret) 594 goto fail; 595 596 phy->ahb_clk = msm_clk_get(pdev, "iface"); 597 if (IS_ERR(phy->ahb_clk)) { 598 DRM_DEV_ERROR(dev, "%s: Unable to get ahb clk\n", __func__); 599 ret = PTR_ERR(phy->ahb_clk); 600 goto fail; 601 } 602 603 if (phy->cfg->ops.init) { 604 ret = phy->cfg->ops.init(phy); 605 if (ret) 606 goto fail; 607 } 608 609 /* PLL init will call into clk_register which requires 610 * register access, so we need to enable power and ahb clock. 611 */ 612 ret = dsi_phy_enable_resource(phy); 613 if (ret) 614 goto fail; 615 616 phy->pll = msm_dsi_pll_init(pdev, phy->cfg->type, phy->id); 617 if (IS_ERR_OR_NULL(phy->pll)) { 618 DRM_DEV_INFO(dev, 619 "%s: pll init failed: %ld, need separate pll clk driver\n", 620 __func__, PTR_ERR(phy->pll)); 621 phy->pll = NULL; 622 } 623 624 dsi_phy_disable_resource(phy); 625 626 platform_set_drvdata(pdev, phy); 627 628 return 0; 629 630 fail: 631 return ret; 632 } 633 634 static int dsi_phy_driver_remove(struct platform_device *pdev) 635 { 636 struct msm_dsi_phy *phy = platform_get_drvdata(pdev); 637 638 if (phy && phy->pll) { 639 msm_dsi_pll_destroy(phy->pll); 640 phy->pll = NULL; 641 } 642 643 platform_set_drvdata(pdev, NULL); 644 645 return 0; 646 } 647 648 static struct platform_driver dsi_phy_platform_driver = { 649 .probe = dsi_phy_driver_probe, 650 .remove = dsi_phy_driver_remove, 651 .driver = { 652 .name = "msm_dsi_phy", 653 .of_match_table = dsi_phy_dt_match, 654 }, 655 }; 656 657 void __init msm_dsi_phy_driver_register(void) 658 { 659 platform_driver_register(&dsi_phy_platform_driver); 660 } 661 662 void __exit msm_dsi_phy_driver_unregister(void) 663 { 664 platform_driver_unregister(&dsi_phy_platform_driver); 665 } 666 667 int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, 668 struct msm_dsi_phy_clk_request *clk_req) 669 { 670 struct device *dev = &phy->pdev->dev; 671 int ret; 672 673 if (!phy || !phy->cfg->ops.enable) 674 return -EINVAL; 675 676 ret = dsi_phy_enable_resource(phy); 677 if (ret) { 678 DRM_DEV_ERROR(dev, "%s: resource enable failed, %d\n", 679 __func__, ret); 680 goto res_en_fail; 681 } 682 683 ret = dsi_phy_regulator_enable(phy); 684 if (ret) { 685 DRM_DEV_ERROR(dev, "%s: regulator enable failed, %d\n", 686 __func__, ret); 687 goto reg_en_fail; 688 } 689 690 ret = phy->cfg->ops.enable(phy, src_pll_id, clk_req); 691 if (ret) { 692 DRM_DEV_ERROR(dev, "%s: phy enable failed, %d\n", __func__, ret); 693 goto phy_en_fail; 694 } 695 696 /* 697 * Resetting DSI PHY silently changes its PLL registers to reset status, 698 * which will confuse clock driver and result in wrong output rate of 699 * link clocks. Restore PLL status if its PLL is being used as clock 700 * source. 701 */ 702 if (phy->usecase != MSM_DSI_PHY_SLAVE) { 703 ret = msm_dsi_pll_restore_state(phy->pll); 704 if (ret) { 705 DRM_DEV_ERROR(dev, "%s: failed to restore pll state, %d\n", 706 __func__, ret); 707 goto pll_restor_fail; 708 } 709 } 710 711 return 0; 712 713 pll_restor_fail: 714 if (phy->cfg->ops.disable) 715 phy->cfg->ops.disable(phy); 716 phy_en_fail: 717 dsi_phy_regulator_disable(phy); 718 reg_en_fail: 719 dsi_phy_disable_resource(phy); 720 res_en_fail: 721 return ret; 722 } 723 724 void msm_dsi_phy_disable(struct msm_dsi_phy *phy) 725 { 726 if (!phy || !phy->cfg->ops.disable) 727 return; 728 729 phy->cfg->ops.disable(phy); 730 731 dsi_phy_regulator_disable(phy); 732 dsi_phy_disable_resource(phy); 733 } 734 735 void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy, 736 struct msm_dsi_phy_shared_timings *shared_timings) 737 { 738 memcpy(shared_timings, &phy->timing.shared_timings, 739 sizeof(*shared_timings)); 740 } 741 742 struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy) 743 { 744 if (!phy) 745 return NULL; 746 747 return phy->pll; 748 } 749 750 void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy, 751 enum msm_dsi_phy_usecase uc) 752 { 753 if (phy) 754 phy->usecase = uc; 755 } 756