1 #ifndef MMSS_CC_XML 2 #define MMSS_CC_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/tmp/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-03-03 01:18:13) 12 - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32) 13 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-01-30 18:25:22) 14 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-01-30 18:25:22) 15 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-01-30 18:25:22) 16 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi.xml ( 17560 bytes, from 2021-09-16 22:37:02) 17 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-07-22 15:21:56) 18 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-07-22 15:21:56) 19 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-07-22 15:21:56) 20 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-07-22 15:21:56) 21 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-07-22 15:21:56) 22 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-07-22 15:21:56) 23 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-03 01:18:13) 24 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-01-30 18:25:22) 25 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-01-30 18:25:22) 26 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-01-30 18:25:22) 27 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-01-30 18:25:22) 28 - /home/robclark/tmp/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-01-30 18:25:22) 29 30 Copyright (C) 2013-2021 by the following authors: 31 - Rob Clark <robdclark@gmail.com> (robclark) 32 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 33 34 Permission is hereby granted, free of charge, to any person obtaining 35 a copy of this software and associated documentation files (the 36 "Software"), to deal in the Software without restriction, including 37 without limitation the rights to use, copy, modify, merge, publish, 38 distribute, sublicense, and/or sell copies of the Software, and to 39 permit persons to whom the Software is furnished to do so, subject to 40 the following conditions: 41 42 The above copyright notice and this permission notice (including the 43 next paragraph) shall be included in all copies or substantial 44 portions of the Software. 45 46 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 47 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 48 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 49 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 50 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 51 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 52 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 53 */ 54 55 56 enum mmss_cc_clk { 57 CLK = 0, 58 PCLK = 1, 59 }; 60 61 #define REG_MMSS_CC_AHB 0x00000008 62 63 static inline uint32_t __offset_CLK(enum mmss_cc_clk idx) 64 { 65 switch (idx) { 66 case CLK: return 0x0000004c; 67 case PCLK: return 0x00000130; 68 default: return INVALID_IDX(idx); 69 } 70 } 71 static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } 72 73 static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } 74 #define MMSS_CC_CLK_CC_CLK_EN 0x00000001 75 #define MMSS_CC_CLK_CC_ROOT_EN 0x00000004 76 #define MMSS_CC_CLK_CC_MND_EN 0x00000020 77 #define MMSS_CC_CLK_CC_MND_MODE__MASK 0x000000c0 78 #define MMSS_CC_CLK_CC_MND_MODE__SHIFT 6 79 static inline uint32_t MMSS_CC_CLK_CC_MND_MODE(uint32_t val) 80 { 81 return ((val) << MMSS_CC_CLK_CC_MND_MODE__SHIFT) & MMSS_CC_CLK_CC_MND_MODE__MASK; 82 } 83 #define MMSS_CC_CLK_CC_PMXO_SEL__MASK 0x00000300 84 #define MMSS_CC_CLK_CC_PMXO_SEL__SHIFT 8 85 static inline uint32_t MMSS_CC_CLK_CC_PMXO_SEL(uint32_t val) 86 { 87 return ((val) << MMSS_CC_CLK_CC_PMXO_SEL__SHIFT) & MMSS_CC_CLK_CC_PMXO_SEL__MASK; 88 } 89 90 static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0); } 91 #define MMSS_CC_CLK_MD_D__MASK 0x000000ff 92 #define MMSS_CC_CLK_MD_D__SHIFT 0 93 static inline uint32_t MMSS_CC_CLK_MD_D(uint32_t val) 94 { 95 return ((val) << MMSS_CC_CLK_MD_D__SHIFT) & MMSS_CC_CLK_MD_D__MASK; 96 } 97 #define MMSS_CC_CLK_MD_M__MASK 0x0000ff00 98 #define MMSS_CC_CLK_MD_M__SHIFT 8 99 static inline uint32_t MMSS_CC_CLK_MD_M(uint32_t val) 100 { 101 return ((val) << MMSS_CC_CLK_MD_M__SHIFT) & MMSS_CC_CLK_MD_M__MASK; 102 } 103 104 static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0); } 105 #define MMSS_CC_CLK_NS_SRC__MASK 0x0000000f 106 #define MMSS_CC_CLK_NS_SRC__SHIFT 0 107 static inline uint32_t MMSS_CC_CLK_NS_SRC(uint32_t val) 108 { 109 return ((val) << MMSS_CC_CLK_NS_SRC__SHIFT) & MMSS_CC_CLK_NS_SRC__MASK; 110 } 111 #define MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK 0x00fff000 112 #define MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT 12 113 static inline uint32_t MMSS_CC_CLK_NS_PRE_DIV_FUNC(uint32_t val) 114 { 115 return ((val) << MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT) & MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK; 116 } 117 #define MMSS_CC_CLK_NS_VAL__MASK 0xff000000 118 #define MMSS_CC_CLK_NS_VAL__SHIFT 24 119 static inline uint32_t MMSS_CC_CLK_NS_VAL(uint32_t val) 120 { 121 return ((val) << MMSS_CC_CLK_NS_VAL__SHIFT) & MMSS_CC_CLK_NS_VAL__MASK; 122 } 123 124 #define REG_MMSS_CC_DSI2_PIXEL_CC 0x00000094 125 126 #define REG_MMSS_CC_DSI2_PIXEL_NS 0x000000e4 127 128 #define REG_MMSS_CC_DSI2_PIXEL_CC2 0x00000264 129 130 131 #endif /* MMSS_CC_XML */ 132