1 #ifndef MMSS_CC_XML 2 #define MMSS_CC_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) 12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) 13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) 14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) 15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) 16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) 17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) 18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) 19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) 20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) 21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) 22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) 23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) 24 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) 25 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) 26 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) 27 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) 28 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) 29 - /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) 30 31 Copyright (C) 2013-2021 by the following authors: 32 - Rob Clark <robdclark@gmail.com> (robclark) 33 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 34 35 Permission is hereby granted, free of charge, to any person obtaining 36 a copy of this software and associated documentation files (the 37 "Software"), to deal in the Software without restriction, including 38 without limitation the rights to use, copy, modify, merge, publish, 39 distribute, sublicense, and/or sell copies of the Software, and to 40 permit persons to whom the Software is furnished to do so, subject to 41 the following conditions: 42 43 The above copyright notice and this permission notice (including the 44 next paragraph) shall be included in all copies or substantial 45 portions of the Software. 46 47 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 48 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 49 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 50 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 51 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 52 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 53 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 54 */ 55 56 57 enum mmss_cc_clk { 58 CLK = 0, 59 PCLK = 1, 60 }; 61 62 #define REG_MMSS_CC_AHB 0x00000008 63 64 static inline uint32_t __offset_CLK(enum mmss_cc_clk idx) 65 { 66 switch (idx) { 67 case CLK: return 0x0000004c; 68 case PCLK: return 0x00000130; 69 default: return INVALID_IDX(idx); 70 } 71 } 72 static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } 73 74 static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } 75 #define MMSS_CC_CLK_CC_CLK_EN 0x00000001 76 #define MMSS_CC_CLK_CC_ROOT_EN 0x00000004 77 #define MMSS_CC_CLK_CC_MND_EN 0x00000020 78 #define MMSS_CC_CLK_CC_MND_MODE__MASK 0x000000c0 79 #define MMSS_CC_CLK_CC_MND_MODE__SHIFT 6 80 static inline uint32_t MMSS_CC_CLK_CC_MND_MODE(uint32_t val) 81 { 82 return ((val) << MMSS_CC_CLK_CC_MND_MODE__SHIFT) & MMSS_CC_CLK_CC_MND_MODE__MASK; 83 } 84 #define MMSS_CC_CLK_CC_PMXO_SEL__MASK 0x00000300 85 #define MMSS_CC_CLK_CC_PMXO_SEL__SHIFT 8 86 static inline uint32_t MMSS_CC_CLK_CC_PMXO_SEL(uint32_t val) 87 { 88 return ((val) << MMSS_CC_CLK_CC_PMXO_SEL__SHIFT) & MMSS_CC_CLK_CC_PMXO_SEL__MASK; 89 } 90 91 static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0); } 92 #define MMSS_CC_CLK_MD_D__MASK 0x000000ff 93 #define MMSS_CC_CLK_MD_D__SHIFT 0 94 static inline uint32_t MMSS_CC_CLK_MD_D(uint32_t val) 95 { 96 return ((val) << MMSS_CC_CLK_MD_D__SHIFT) & MMSS_CC_CLK_MD_D__MASK; 97 } 98 #define MMSS_CC_CLK_MD_M__MASK 0x0000ff00 99 #define MMSS_CC_CLK_MD_M__SHIFT 8 100 static inline uint32_t MMSS_CC_CLK_MD_M(uint32_t val) 101 { 102 return ((val) << MMSS_CC_CLK_MD_M__SHIFT) & MMSS_CC_CLK_MD_M__MASK; 103 } 104 105 static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0); } 106 #define MMSS_CC_CLK_NS_SRC__MASK 0x0000000f 107 #define MMSS_CC_CLK_NS_SRC__SHIFT 0 108 static inline uint32_t MMSS_CC_CLK_NS_SRC(uint32_t val) 109 { 110 return ((val) << MMSS_CC_CLK_NS_SRC__SHIFT) & MMSS_CC_CLK_NS_SRC__MASK; 111 } 112 #define MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK 0x00fff000 113 #define MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT 12 114 static inline uint32_t MMSS_CC_CLK_NS_PRE_DIV_FUNC(uint32_t val) 115 { 116 return ((val) << MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT) & MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK; 117 } 118 #define MMSS_CC_CLK_NS_VAL__MASK 0xff000000 119 #define MMSS_CC_CLK_NS_VAL__SHIFT 24 120 static inline uint32_t MMSS_CC_CLK_NS_VAL(uint32_t val) 121 { 122 return ((val) << MMSS_CC_CLK_NS_VAL__SHIFT) & MMSS_CC_CLK_NS_VAL__MASK; 123 } 124 125 #define REG_MMSS_CC_DSI2_PIXEL_CC 0x00000094 126 127 #define REG_MMSS_CC_DSI2_PIXEL_NS 0x000000e4 128 129 #define REG_MMSS_CC_DSI2_PIXEL_CC2 0x00000264 130 131 132 #endif /* MMSS_CC_XML */ 133