1 #ifndef DSI_PHY_7NM_XML 2 #define DSI_PHY_7NM_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46) 12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) 13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42) 14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42) 15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42) 16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36) 17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42) 18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42) 19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42) 20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42) 21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42) 22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42) 23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42) 24 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42) 25 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42) 26 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42) 27 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56) 28 - /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42) 29 30 Copyright (C) 2013-2022 by the following authors: 31 - Rob Clark <robdclark@gmail.com> (robclark) 32 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 33 34 Permission is hereby granted, free of charge, to any person obtaining 35 a copy of this software and associated documentation files (the 36 "Software"), to deal in the Software without restriction, including 37 without limitation the rights to use, copy, modify, merge, publish, 38 distribute, sublicense, and/or sell copies of the Software, and to 39 permit persons to whom the Software is furnished to do so, subject to 40 the following conditions: 41 42 The above copyright notice and this permission notice (including the 43 next paragraph) shall be included in all copies or substantial 44 portions of the Software. 45 46 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 47 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 48 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 49 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 50 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 51 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 52 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 53 */ 54 55 56 #define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000 57 58 #define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004 59 60 #define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008 61 62 #define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c 63 64 #define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010 65 66 #define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014 67 68 #define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018 69 70 #define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c 71 72 #define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020 73 74 #define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024 75 76 #define REG_DSI_7nm_PHY_CMN_CTRL_1 0x00000028 77 78 #define REG_DSI_7nm_PHY_CMN_CTRL_2 0x0000002c 79 80 #define REG_DSI_7nm_PHY_CMN_CTRL_3 0x00000030 81 82 #define REG_DSI_7nm_PHY_CMN_LANE_CFG0 0x00000034 83 84 #define REG_DSI_7nm_PHY_CMN_LANE_CFG1 0x00000038 85 86 #define REG_DSI_7nm_PHY_CMN_PLL_CNTRL 0x0000003c 87 88 #define REG_DSI_7nm_PHY_CMN_DPHY_SOT 0x00000040 89 90 #define REG_DSI_7nm_PHY_CMN_LANE_CTRL0 0x000000a0 91 92 #define REG_DSI_7nm_PHY_CMN_LANE_CTRL1 0x000000a4 93 94 #define REG_DSI_7nm_PHY_CMN_LANE_CTRL2 0x000000a8 95 96 #define REG_DSI_7nm_PHY_CMN_LANE_CTRL3 0x000000ac 97 98 #define REG_DSI_7nm_PHY_CMN_LANE_CTRL4 0x000000b0 99 100 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0 0x000000b4 101 102 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1 0x000000b8 103 104 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2 0x000000bc 105 106 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 0x000000c0 107 108 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4 0x000000c4 109 110 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 0x000000c8 111 112 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6 0x000000cc 113 114 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7 0x000000d0 115 116 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8 0x000000d4 117 118 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9 0x000000d8 119 120 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10 0x000000dc 121 122 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11 0x000000e0 123 124 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12 0x000000e4 125 126 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13 0x000000e8 127 128 #define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec 129 130 #define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0 131 132 #define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4 133 134 #define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8 135 136 #define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc 137 138 #define REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100 139 140 #define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104 141 142 #define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108 143 144 #define REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c 145 146 #define REG_DSI_7nm_PHY_CMN_VREG_CTRL_1 0x00000110 147 148 #define REG_DSI_7nm_PHY_CMN_CTRL_4 0x00000114 149 150 #define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4 0x00000128 151 152 #define REG_DSI_7nm_PHY_CMN_PHY_STATUS 0x00000140 153 154 #define REG_DSI_7nm_PHY_CMN_LANE_STATUS0 0x00000148 155 156 #define REG_DSI_7nm_PHY_CMN_LANE_STATUS1 0x0000014c 157 158 #define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10 0x000001ac 159 160 static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } 161 162 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } 163 164 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } 165 166 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } 167 168 static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; } 169 170 static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; } 171 172 static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; } 173 174 static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; } 175 176 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000 177 178 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004 179 180 #define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008 181 182 #define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c 183 184 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010 185 186 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014 187 188 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018 189 190 #define REG_DSI_7nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c 191 192 #define REG_DSI_7nm_PHY_PLL_DSM_DIVIDER 0x00000020 193 194 #define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024 195 196 #define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES 0x00000028 197 198 #define REG_DSI_7nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c 199 200 #define REG_DSI_7nm_PHY_PLL_CMODE 0x00000030 201 202 #define REG_DSI_7nm_PHY_PLL_PSM_CTRL 0x00000034 203 204 #define REG_DSI_7nm_PHY_PLL_RSM_CTRL 0x00000038 205 206 #define REG_DSI_7nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c 207 208 #define REG_DSI_7nm_PHY_PLL_PLL_CNTRL 0x00000040 209 210 #define REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044 211 212 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048 213 214 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c 215 216 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050 217 218 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_MIN 0x00000054 219 220 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_MAX 0x00000058 221 222 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c 223 224 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_IFILT 0x00000060 225 226 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064 227 228 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068 229 230 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c 231 232 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070 233 234 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074 235 236 #define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078 237 238 #define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c 239 240 #define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080 241 242 #define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084 243 244 #define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088 245 246 #define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c 247 248 #define REG_DSI_7nm_PHY_PLL_PFILT 0x00000090 249 250 #define REG_DSI_7nm_PHY_PLL_IFILT 0x00000094 251 252 #define REG_DSI_7nm_PHY_PLL_PLL_GAIN 0x00000098 253 254 #define REG_DSI_7nm_PHY_PLL_ICODE_LOW 0x0000009c 255 256 #define REG_DSI_7nm_PHY_PLL_ICODE_HIGH 0x000000a0 257 258 #define REG_DSI_7nm_PHY_PLL_LOCKDET 0x000000a4 259 260 #define REG_DSI_7nm_PHY_PLL_OUTDIV 0x000000a8 261 262 #define REG_DSI_7nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac 263 264 #define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0 265 266 #define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4 267 268 #define REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE 0x000000b8 269 270 #define REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc 271 272 #define REG_DSI_7nm_PHY_PLL_RATE_CHANGE 0x000000c0 273 274 #define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4 275 276 #define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8 277 278 #define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc 279 280 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0 281 282 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4 283 284 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8 285 286 #define REG_DSI_7nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc 287 288 #define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0 289 290 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4 291 292 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8 293 294 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec 295 296 #define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0 297 298 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4 299 300 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8 301 302 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc 303 304 #define REG_DSI_7nm_PHY_PLL_MASH_CONTROL 0x00000100 305 306 #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104 307 308 #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108 309 310 #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c 311 312 #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110 313 314 #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114 315 316 #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118 317 318 #define REG_DSI_7nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c 319 320 #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120 321 322 #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124 323 324 #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128 325 326 #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c 327 328 #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130 329 330 #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134 331 332 #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138 333 334 #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c 335 336 #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140 337 338 #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144 339 340 #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148 341 342 #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c 343 344 #define REG_DSI_7nm_PHY_PLL_SSC_CONTROL 0x00000150 345 346 #define REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154 347 348 #define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158 349 350 #define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c 351 352 #define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160 353 354 #define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164 355 356 #define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168 357 358 #define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c 359 360 #define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170 361 362 #define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174 363 364 #define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178 365 366 #define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c 367 368 #define REG_DSI_7nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180 369 370 #define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184 371 372 #define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188 373 374 #define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c 375 376 #define REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190 377 378 #define REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194 379 380 #define REG_DSI_7nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198 381 382 #define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c 383 384 #define REG_DSI_7nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0 385 386 #define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4 387 388 #define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8 389 390 #define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac 391 392 #define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0 393 394 #define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4 395 396 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL 0x000001b8 397 398 #define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc 399 400 #define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0 401 402 #define REG_DSI_7nm_PHY_PLL_FD_OUT_LOW 0x000001c4 403 404 #define REG_DSI_7nm_PHY_PLL_FD_OUT_HIGH 0x000001c8 405 406 #define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc 407 408 #define REG_DSI_7nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0 409 410 #define REG_DSI_7nm_PHY_PLL_FLL_CONFIG 0x000001d4 411 412 #define REG_DSI_7nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8 413 414 #define REG_DSI_7nm_PHY_PLL_FLL_CODE0 0x000001dc 415 416 #define REG_DSI_7nm_PHY_PLL_FLL_CODE1 0x000001e0 417 418 #define REG_DSI_7nm_PHY_PLL_FLL_GAIN0 0x000001e4 419 420 #define REG_DSI_7nm_PHY_PLL_FLL_GAIN1 0x000001e8 421 422 #define REG_DSI_7nm_PHY_PLL_SW_RESET 0x000001ec 423 424 #define REG_DSI_7nm_PHY_PLL_FAST_PWRUP 0x000001f0 425 426 #define REG_DSI_7nm_PHY_PLL_LOCKTIME0 0x000001f4 427 428 #define REG_DSI_7nm_PHY_PLL_LOCKTIME1 0x000001f8 429 430 #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc 431 432 #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS0 0x00000200 433 434 #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS1 0x00000204 435 436 #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS2 0x00000208 437 438 #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS3 0x0000020c 439 440 #define REG_DSI_7nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210 441 442 #define REG_DSI_7nm_PHY_PLL_VCO_CONFIG 0x00000214 443 444 #define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218 445 446 #define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c 447 448 #define REG_DSI_7nm_PHY_PLL_RESET_SM_STATUS 0x00000220 449 450 #define REG_DSI_7nm_PHY_PLL_TDC_OFFSET 0x00000224 451 452 #define REG_DSI_7nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228 453 454 #define REG_DSI_7nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c 455 456 #define REG_DSI_7nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230 457 458 #define REG_DSI_7nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234 459 460 #define REG_DSI_7nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238 461 462 #define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c 463 464 #define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1 0x00000240 465 466 #define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_2 0x00000244 467 468 #define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248 469 470 #define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c 471 472 #define REG_DSI_7nm_PHY_PLL_CMODE_1 0x00000250 473 474 #define REG_DSI_7nm_PHY_PLL_CMODE_2 0x00000254 475 476 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258 477 478 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c 479 480 #define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE 0x00000260 481 482 483 #endif /* DSI_PHY_7NM_XML */ 484