1 #ifndef DSI_PHY_28NM_8960_XML 2 #define DSI_PHY_28NM_8960_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) 12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) 13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) 14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) 15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) 16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) 17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) 18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) 19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) 20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) 21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) 22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) 23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) 24 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) 25 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) 26 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) 27 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) 28 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) 29 - /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) 30 31 Copyright (C) 2013-2021 by the following authors: 32 - Rob Clark <robdclark@gmail.com> (robclark) 33 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 34 35 Permission is hereby granted, free of charge, to any person obtaining 36 a copy of this software and associated documentation files (the 37 "Software"), to deal in the Software without restriction, including 38 without limitation the rights to use, copy, modify, merge, publish, 39 distribute, sublicense, and/or sell copies of the Software, and to 40 permit persons to whom the Software is furnished to do so, subject to 41 the following conditions: 42 43 The above copyright notice and this permission notice (including the 44 next paragraph) shall be included in all copies or substantial 45 portions of the Software. 46 47 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 48 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 49 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 50 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 51 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 52 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 53 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 54 */ 55 56 57 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } 58 59 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } 60 61 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } 62 63 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } 64 65 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; } 66 67 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; } 68 69 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; } 70 71 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100 72 73 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104 74 75 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108 76 77 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c 78 79 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114 80 81 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118 82 83 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140 84 #define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff 85 #define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 86 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) 87 { 88 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; 89 } 90 91 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144 92 #define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff 93 #define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 94 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) 95 { 96 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; 97 } 98 99 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148 100 #define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff 101 #define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 102 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) 103 { 104 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; 105 } 106 107 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c 108 109 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150 110 #define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff 111 #define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 112 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) 113 { 114 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK; 115 } 116 117 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154 118 #define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff 119 #define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 120 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) 121 { 122 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK; 123 } 124 125 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158 126 #define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff 127 #define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 128 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) 129 { 130 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; 131 } 132 133 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c 134 #define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff 135 #define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 136 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) 137 { 138 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; 139 } 140 141 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160 142 #define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff 143 #define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 144 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) 145 { 146 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK; 147 } 148 149 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164 150 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 151 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 152 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) 153 { 154 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK; 155 } 156 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 157 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 158 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) 159 { 160 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK; 161 } 162 163 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168 164 #define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 165 #define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 166 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) 167 { 168 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK; 169 } 170 171 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c 172 #define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff 173 #define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 174 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) 175 { 176 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; 177 } 178 179 #define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170 180 181 #define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174 182 183 #define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178 184 185 #define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c 186 187 #define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180 188 189 #define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184 190 191 #define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188 192 193 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c 194 195 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190 196 197 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194 198 199 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198 200 201 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c 202 203 #define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0 204 205 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000 206 207 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004 208 209 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008 210 211 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c 212 213 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010 214 215 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014 216 217 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018 218 219 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028 220 221 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c 222 223 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030 224 225 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034 226 227 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038 228 229 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c 230 231 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040 232 233 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044 234 235 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048 236 237 #define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050 238 #define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010 239 240 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000 241 #define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001 242 243 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004 244 245 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008 246 247 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c 248 249 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010 250 251 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014 252 253 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018 254 255 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c 256 257 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020 258 259 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024 260 261 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028 262 263 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c 264 265 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030 266 267 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034 268 269 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038 270 271 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c 272 273 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040 274 275 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044 276 277 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048 278 279 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c 280 281 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050 282 283 #define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080 284 #define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001 285 286 287 #endif /* DSI_PHY_28NM_8960_XML */ 288