1 #ifndef DSI_PHY_28NM_XML 2 #define DSI_PHY_28NM_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) 12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) 13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) 14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) 15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) 16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) 17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) 18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) 19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) 20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) 21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) 22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) 23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) 24 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) 25 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) 26 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) 27 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) 28 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) 29 - /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) 30 31 Copyright (C) 2013-2021 by the following authors: 32 - Rob Clark <robdclark@gmail.com> (robclark) 33 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 34 35 Permission is hereby granted, free of charge, to any person obtaining 36 a copy of this software and associated documentation files (the 37 "Software"), to deal in the Software without restriction, including 38 without limitation the rights to use, copy, modify, merge, publish, 39 distribute, sublicense, and/or sell copies of the Software, and to 40 permit persons to whom the Software is furnished to do so, subject to 41 the following conditions: 42 43 The above copyright notice and this permission notice (including the 44 next paragraph) shall be included in all copies or substantial 45 portions of the Software. 46 47 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 48 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 49 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 50 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 51 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 52 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 53 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 54 */ 55 56 57 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } 58 59 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } 60 61 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } 62 63 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } 64 65 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } 66 67 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } 68 69 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } 70 71 static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } 72 73 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } 74 75 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } 76 77 #define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100 78 79 #define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104 80 81 #define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108 82 83 #define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c 84 85 #define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110 86 87 #define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114 88 89 #define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118 90 91 #define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c 92 93 #define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120 94 95 #define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140 96 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff 97 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 98 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) 99 { 100 return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; 101 } 102 103 #define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144 104 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff 105 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 106 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) 107 { 108 return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; 109 } 110 111 #define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148 112 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff 113 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 114 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) 115 { 116 return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; 117 } 118 119 #define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c 120 #define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001 121 122 #define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150 123 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff 124 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 125 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) 126 { 127 return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; 128 } 129 130 #define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154 131 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff 132 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 133 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) 134 { 135 return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; 136 } 137 138 #define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158 139 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff 140 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 141 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) 142 { 143 return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; 144 } 145 146 #define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c 147 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff 148 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 149 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) 150 { 151 return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; 152 } 153 154 #define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160 155 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff 156 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 157 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) 158 { 159 return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; 160 } 161 162 #define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164 163 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 164 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 165 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) 166 { 167 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK; 168 } 169 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 170 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 171 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) 172 { 173 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; 174 } 175 176 #define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168 177 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 178 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 179 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) 180 { 181 return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK; 182 } 183 184 #define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c 185 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff 186 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 187 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) 188 { 189 return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; 190 } 191 192 #define REG_DSI_28nm_PHY_CTRL_0 0x00000170 193 194 #define REG_DSI_28nm_PHY_CTRL_1 0x00000174 195 196 #define REG_DSI_28nm_PHY_CTRL_2 0x00000178 197 198 #define REG_DSI_28nm_PHY_CTRL_3 0x0000017c 199 200 #define REG_DSI_28nm_PHY_CTRL_4 0x00000180 201 202 #define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184 203 204 #define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188 205 206 #define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4 207 208 #define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8 209 210 #define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc 211 212 #define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0 213 214 #define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4 215 216 #define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8 217 218 #define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4 219 #define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001 220 221 #define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc 222 223 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000 224 225 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004 226 227 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008 228 229 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c 230 231 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010 232 233 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014 234 235 #define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018 236 237 #define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000 238 #define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001 239 240 #define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004 241 242 #define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008 243 244 #define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c 245 246 #define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010 247 #define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002 248 249 #define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014 250 251 #define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018 252 253 #define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c 254 255 #define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020 256 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001 257 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002 258 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004 259 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008 260 261 #define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024 262 263 #define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028 264 265 #define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c 266 267 #define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030 268 269 #define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034 270 271 #define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038 272 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f 273 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0 274 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val) 275 { 276 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK; 277 } 278 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040 279 280 #define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c 281 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f 282 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0 283 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val) 284 { 285 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; 286 } 287 #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040 288 #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6 289 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val) 290 { 291 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK; 292 } 293 294 #define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040 295 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff 296 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0 297 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val) 298 { 299 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK; 300 } 301 302 #define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044 303 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff 304 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0 305 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val) 306 { 307 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK; 308 } 309 310 #define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048 311 312 #define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c 313 314 #define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050 315 316 #define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054 317 318 #define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058 319 320 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c 321 322 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060 323 324 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064 325 326 #define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068 327 #define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001 328 329 #define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c 330 331 #define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070 332 333 #define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074 334 335 #define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078 336 337 #define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c 338 339 #define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080 340 341 #define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084 342 343 #define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088 344 345 #define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c 346 347 #define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090 348 349 #define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094 350 351 #define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098 352 353 #define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c 354 355 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0 356 357 #define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4 358 359 #define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8 360 361 #define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac 362 363 #define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0 364 365 #define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4 366 367 #define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8 368 369 #define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc 370 371 #define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0 372 #define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001 373 374 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4 375 376 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8 377 378 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc 379 380 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0 381 382 #define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4 383 384 385 #endif /* DSI_PHY_28NM_XML */ 386