1 #ifndef DSI_PHY_14NM_XML
2 #define DSI_PHY_14NM_XML
3 
4 /* Autogenerated file, DO NOT EDIT manually!
5 
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9 
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml                   (    944 bytes, from 2022-07-23 20:21:46)
12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml   (   1572 bytes, from 2022-07-23 20:21:46)
13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml              (  20912 bytes, from 2022-03-08 17:40:42)
14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml        (   2849 bytes, from 2022-03-08 17:40:42)
15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml              (  37461 bytes, from 2022-03-08 17:40:42)
16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml               (  18746 bytes, from 2022-04-28 17:29:36)
17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml        (   3236 bytes, from 2022-03-08 17:40:42)
18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml (   4935 bytes, from 2022-03-08 17:40:42)
19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml      (   7004 bytes, from 2022-03-08 17:40:42)
20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml      (   3712 bytes, from 2022-03-08 17:40:42)
21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml      (   5381 bytes, from 2022-03-08 17:40:42)
22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml      (   4499 bytes, from 2022-03-08 17:40:42)
23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml       (  11007 bytes, from 2022-03-08 17:40:42)
24 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml              (    602 bytes, from 2022-03-08 17:40:42)
25 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml           (   1686 bytes, from 2022-03-08 17:40:42)
26 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml           (    600 bytes, from 2022-03-08 17:40:42)
27 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml             (  42350 bytes, from 2022-09-20 17:45:56)
28 - /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml               (  10416 bytes, from 2022-03-08 17:40:42)
29 
30 Copyright (C) 2013-2022 by the following authors:
31 - Rob Clark <robdclark@gmail.com> (robclark)
32 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
33 
34 Permission is hereby granted, free of charge, to any person obtaining
35 a copy of this software and associated documentation files (the
36 "Software"), to deal in the Software without restriction, including
37 without limitation the rights to use, copy, modify, merge, publish,
38 distribute, sublicense, and/or sell copies of the Software, and to
39 permit persons to whom the Software is furnished to do so, subject to
40 the following conditions:
41 
42 The above copyright notice and this permission notice (including the
43 next paragraph) shall be included in all copies or substantial
44 portions of the Software.
45 
46 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
47 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
48 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
49 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
50 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
51 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
52 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
53 */
54 
55 
56 #define REG_DSI_14nm_PHY_CMN_REVISION_ID0			0x00000000
57 
58 #define REG_DSI_14nm_PHY_CMN_REVISION_ID1			0x00000004
59 
60 #define REG_DSI_14nm_PHY_CMN_REVISION_ID2			0x00000008
61 
62 #define REG_DSI_14nm_PHY_CMN_REVISION_ID3			0x0000000c
63 
64 #define REG_DSI_14nm_PHY_CMN_CLK_CFG0				0x00000010
65 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK		0x000000f0
66 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT		4
67 static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)
68 {
69 	return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK;
70 }
71 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK		0x000000f0
72 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT		4
73 static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)
74 {
75 	return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK;
76 }
77 
78 #define REG_DSI_14nm_PHY_CMN_CLK_CFG1				0x00000014
79 #define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL			0x00000001
80 
81 #define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL			0x00000018
82 #define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL		0x00000004
83 
84 #define REG_DSI_14nm_PHY_CMN_CTRL_0				0x0000001c
85 
86 #define REG_DSI_14nm_PHY_CMN_CTRL_1				0x00000020
87 
88 #define REG_DSI_14nm_PHY_CMN_HW_TRIGGER				0x00000024
89 
90 #define REG_DSI_14nm_PHY_CMN_SW_CFG0				0x00000028
91 
92 #define REG_DSI_14nm_PHY_CMN_SW_CFG1				0x0000002c
93 
94 #define REG_DSI_14nm_PHY_CMN_SW_CFG2				0x00000030
95 
96 #define REG_DSI_14nm_PHY_CMN_HW_CFG0				0x00000034
97 
98 #define REG_DSI_14nm_PHY_CMN_HW_CFG1				0x00000038
99 
100 #define REG_DSI_14nm_PHY_CMN_HW_CFG2				0x0000003c
101 
102 #define REG_DSI_14nm_PHY_CMN_HW_CFG3				0x00000040
103 
104 #define REG_DSI_14nm_PHY_CMN_HW_CFG4				0x00000044
105 
106 #define REG_DSI_14nm_PHY_CMN_PLL_CNTRL				0x00000048
107 #define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START			0x00000001
108 
109 #define REG_DSI_14nm_PHY_CMN_LDO_CNTRL				0x0000004c
110 #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK		0x0000003f
111 #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT		0
112 static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)
113 {
114 	return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK;
115 }
116 
117 static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
118 
119 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
120 #define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK			0x000000c0
121 #define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT			6
122 static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)
123 {
124 	return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK;
125 }
126 
127 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
128 #define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN			0x00000001
129 
130 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
131 
132 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
133 
134 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
135 
136 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }
137 
138 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; }
139 #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK		0x000000ff
140 #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT		0
141 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)
142 {
143 	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK;
144 }
145 
146 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; }
147 #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK		0x000000ff
148 #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT		0
149 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)
150 {
151 	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK;
152 }
153 
154 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; }
155 #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK		0x000000ff
156 #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT		0
157 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
158 {
159 	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK;
160 }
161 
162 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; }
163 #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK		0x000000ff
164 #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT		0
165 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
166 {
167 	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK;
168 }
169 
170 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; }
171 #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK		0x000000ff
172 #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT		0
173 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)
174 {
175 	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK;
176 }
177 
178 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; }
179 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK		0x00000007
180 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT		0
181 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)
182 {
183 	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK;
184 }
185 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK		0x00000070
186 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT		4
187 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)
188 {
189 	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK;
190 }
191 
192 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; }
193 #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK		0x00000007
194 #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT		0
195 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)
196 {
197 	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK;
198 }
199 
200 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; }
201 #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK		0x000000ff
202 #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT		0
203 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
204 {
205 	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK;
206 }
207 
208 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; }
209 
210 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; }
211 
212 static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }
213 
214 #define REG_DSI_14nm_PHY_PLL_IE_TRIM				0x00000000
215 
216 #define REG_DSI_14nm_PHY_PLL_IP_TRIM				0x00000004
217 
218 #define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM				0x00000010
219 
220 #define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN			0x0000001c
221 
222 #define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET			0x00000028
223 
224 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL			0x0000002c
225 
226 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2			0x00000030
227 
228 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3			0x00000034
229 
230 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4			0x00000038
231 
232 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5			0x0000003c
233 
234 #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1			0x00000040
235 
236 #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2			0x00000044
237 
238 #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1			0x00000048
239 
240 #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2			0x0000004c
241 
242 #define REG_DSI_14nm_PHY_PLL_VREF_CFG1				0x0000005c
243 
244 #define REG_DSI_14nm_PHY_PLL_KVCO_CODE				0x00000058
245 
246 #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1			0x0000006c
247 
248 #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2			0x00000070
249 
250 #define REG_DSI_14nm_PHY_PLL_VCO_COUNT1				0x00000074
251 
252 #define REG_DSI_14nm_PHY_PLL_VCO_COUNT2				0x00000078
253 
254 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1			0x0000007c
255 
256 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2			0x00000080
257 
258 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3			0x00000084
259 
260 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN			0x00000088
261 
262 #define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE			0x0000008c
263 
264 #define REG_DSI_14nm_PHY_PLL_DEC_START				0x00000090
265 
266 #define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER			0x00000094
267 
268 #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1			0x00000098
269 
270 #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2			0x0000009c
271 
272 #define REG_DSI_14nm_PHY_PLL_SSC_PER1				0x000000a0
273 
274 #define REG_DSI_14nm_PHY_PLL_SSC_PER2				0x000000a4
275 
276 #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1			0x000000a8
277 
278 #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2			0x000000ac
279 
280 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1			0x000000b4
281 
282 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2			0x000000b8
283 
284 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3			0x000000bc
285 
286 #define REG_DSI_14nm_PHY_PLL_TXCLK_EN				0x000000c0
287 
288 #define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL				0x000000c4
289 
290 #define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS		0x000000cc
291 
292 #define REG_DSI_14nm_PHY_PLL_PLL_MISC1				0x000000e8
293 
294 #define REG_DSI_14nm_PHY_PLL_CP_SET_CUR				0x000000f0
295 
296 #define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET			0x000000f4
297 
298 #define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET			0x000000f8
299 
300 #define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET			0x000000fc
301 
302 #define REG_DSI_14nm_PHY_PLL_PLL_LPF1				0x00000100
303 
304 #define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV			0x00000104
305 
306 #define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP			0x00000108
307 
308 
309 #endif /* DSI_PHY_14NM_XML */
310