1 #ifndef DSI_PHY_10NM_XML 2 #define DSI_PHY_10NM_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) 12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) 13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) 14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) 15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) 16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) 17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) 18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) 19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) 20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) 21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) 22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) 23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) 24 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) 25 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) 26 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) 27 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) 28 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) 29 - /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) 30 31 Copyright (C) 2013-2021 by the following authors: 32 - Rob Clark <robdclark@gmail.com> (robclark) 33 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 34 35 Permission is hereby granted, free of charge, to any person obtaining 36 a copy of this software and associated documentation files (the 37 "Software"), to deal in the Software without restriction, including 38 without limitation the rights to use, copy, modify, merge, publish, 39 distribute, sublicense, and/or sell copies of the Software, and to 40 permit persons to whom the Software is furnished to do so, subject to 41 the following conditions: 42 43 The above copyright notice and this permission notice (including the 44 next paragraph) shall be included in all copies or substantial 45 portions of the Software. 46 47 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 48 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 49 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 50 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 51 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 52 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 53 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 54 */ 55 56 57 #define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000 58 59 #define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004 60 61 #define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008 62 63 #define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c 64 65 #define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010 66 67 #define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014 68 69 #define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018 70 71 #define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c 72 73 #define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020 74 75 #define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024 76 77 #define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028 78 79 #define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c 80 81 #define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030 82 83 #define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034 84 85 #define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038 86 87 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098 88 89 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c 90 91 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0 92 93 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4 94 95 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8 96 97 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac 98 99 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0 100 101 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4 102 103 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8 104 105 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc 106 107 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0 108 109 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4 110 111 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8 112 113 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc 114 115 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0 116 117 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4 118 119 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8 120 121 #define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec 122 123 #define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4 124 125 #define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8 126 127 static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } 128 129 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } 130 131 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } 132 133 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } 134 135 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } 136 137 static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; } 138 139 static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; } 140 141 static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; } 142 143 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; } 144 145 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; } 146 147 static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; } 148 149 static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; } 150 151 static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; } 152 153 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000 154 155 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004 156 157 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010 158 159 #define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c 160 161 #define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020 162 163 #define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024 164 165 #define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c 166 167 #define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030 168 169 #define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054 170 171 #define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064 172 173 #define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c 174 175 #define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080 176 177 #define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094 178 179 #define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4 180 181 #define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8 182 183 #define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4 184 185 #define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc 186 187 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0 188 189 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4 190 191 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8 192 193 #define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c 194 195 #define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110 196 197 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114 198 199 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118 200 201 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c 202 203 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120 204 205 #define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c 206 207 #define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140 208 209 #define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144 210 211 #define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c 212 213 #define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154 214 215 #define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c 216 217 #define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164 218 219 #define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180 220 221 #define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184 222 223 #define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c 224 225 #define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0 226 227 228 #endif /* DSI_PHY_10NM_XML */ 229