1 #ifndef DSI_PHY_10NM_XML 2 #define DSI_PHY_10NM_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/tmp/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-03-03 01:18:13) 12 - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32) 13 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-01-30 18:25:22) 14 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-01-30 18:25:22) 15 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-01-30 18:25:22) 16 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi.xml ( 17560 bytes, from 2021-09-16 22:37:02) 17 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-07-22 15:21:56) 18 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-07-22 15:21:56) 19 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-07-22 15:21:56) 20 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-07-22 15:21:56) 21 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-07-22 15:21:56) 22 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-07-22 15:21:56) 23 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-03 01:18:13) 24 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-01-30 18:25:22) 25 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-01-30 18:25:22) 26 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-01-30 18:25:22) 27 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-01-30 18:25:22) 28 - /home/robclark/tmp/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-01-30 18:25:22) 29 30 Copyright (C) 2013-2021 by the following authors: 31 - Rob Clark <robdclark@gmail.com> (robclark) 32 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 33 34 Permission is hereby granted, free of charge, to any person obtaining 35 a copy of this software and associated documentation files (the 36 "Software"), to deal in the Software without restriction, including 37 without limitation the rights to use, copy, modify, merge, publish, 38 distribute, sublicense, and/or sell copies of the Software, and to 39 permit persons to whom the Software is furnished to do so, subject to 40 the following conditions: 41 42 The above copyright notice and this permission notice (including the 43 next paragraph) shall be included in all copies or substantial 44 portions of the Software. 45 46 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 47 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 48 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 49 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 50 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 51 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 52 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 53 */ 54 55 56 #define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000 57 58 #define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004 59 60 #define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008 61 62 #define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c 63 64 #define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010 65 66 #define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014 67 68 #define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018 69 70 #define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c 71 72 #define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020 73 74 #define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024 75 76 #define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028 77 78 #define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c 79 80 #define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030 81 82 #define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034 83 84 #define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038 85 86 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098 87 88 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c 89 90 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0 91 92 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4 93 94 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8 95 96 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac 97 98 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0 99 100 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4 101 102 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8 103 104 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc 105 106 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0 107 108 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4 109 110 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8 111 112 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc 113 114 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0 115 116 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4 117 118 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8 119 120 #define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec 121 122 #define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4 123 124 #define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8 125 126 static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } 127 128 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } 129 130 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } 131 132 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } 133 134 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } 135 136 static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; } 137 138 static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; } 139 140 static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; } 141 142 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; } 143 144 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; } 145 146 static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; } 147 148 static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; } 149 150 static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; } 151 152 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000 153 154 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004 155 156 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010 157 158 #define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c 159 160 #define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020 161 162 #define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024 163 164 #define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c 165 166 #define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030 167 168 #define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054 169 170 #define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064 171 172 #define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c 173 174 #define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080 175 176 #define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094 177 178 #define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4 179 180 #define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8 181 182 #define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4 183 184 #define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc 185 186 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0 187 188 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4 189 190 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8 191 192 #define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c 193 194 #define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110 195 196 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114 197 198 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118 199 200 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c 201 202 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120 203 204 #define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c 205 206 #define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140 207 208 #define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144 209 210 #define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c 211 212 #define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154 213 214 #define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c 215 216 #define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164 217 218 #define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180 219 220 #define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184 221 222 #define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c 223 224 #define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0 225 226 227 #endif /* DSI_PHY_10NM_XML */ 228