1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/err.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/interrupt.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/of_device.h> 14 #include <linux/of_graph.h> 15 #include <linux/of_irq.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/pm_opp.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spinlock.h> 21 22 #include <video/mipi_display.h> 23 24 #include <drm/drm_of.h> 25 26 #include "dsi.h" 27 #include "dsi.xml.h" 28 #include "sfpb.xml.h" 29 #include "dsi_cfg.h" 30 #include "msm_kms.h" 31 #include "msm_gem.h" 32 #include "phy/dsi_phy.h" 33 34 #define DSI_RESET_TOGGLE_DELAY_MS 20 35 36 static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc); 37 38 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 39 { 40 u32 ver; 41 42 if (!major || !minor) 43 return -EINVAL; 44 45 /* 46 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 47 * makes all other registers 4-byte shifted down. 48 * 49 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and 50 * older, we read the DSI_VERSION register without any shift(offset 51 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In 52 * the case of DSI6G, this has to be zero (the offset points to a 53 * scratch register which we never touch) 54 */ 55 56 ver = msm_readl(base + REG_DSI_VERSION); 57 if (ver) { 58 /* older dsi host, there is no register shift */ 59 ver = FIELD(ver, DSI_VERSION_MAJOR); 60 if (ver <= MSM_DSI_VER_MAJOR_V2) { 61 /* old versions */ 62 *major = ver; 63 *minor = 0; 64 return 0; 65 } else { 66 return -EINVAL; 67 } 68 } else { 69 /* 70 * newer host, offset 0 has 6G_HW_VERSION, the rest of the 71 * registers are shifted down, read DSI_VERSION again with 72 * the shifted offset 73 */ 74 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 75 ver = FIELD(ver, DSI_VERSION_MAJOR); 76 if (ver == MSM_DSI_VER_MAJOR_6G) { 77 /* 6G version */ 78 *major = ver; 79 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION); 80 return 0; 81 } else { 82 return -EINVAL; 83 } 84 } 85 } 86 87 #define DSI_ERR_STATE_ACK 0x0000 88 #define DSI_ERR_STATE_TIMEOUT 0x0001 89 #define DSI_ERR_STATE_DLN0_PHY 0x0002 90 #define DSI_ERR_STATE_FIFO 0x0004 91 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 92 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 93 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 94 95 #define DSI_CLK_CTRL_ENABLE_CLKS \ 96 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 97 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 98 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 99 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 100 101 struct msm_dsi_host { 102 struct mipi_dsi_host base; 103 104 struct platform_device *pdev; 105 struct drm_device *dev; 106 107 int id; 108 109 void __iomem *ctrl_base; 110 phys_addr_t ctrl_size; 111 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; 112 113 int num_bus_clks; 114 struct clk_bulk_data bus_clks[DSI_BUS_CLK_MAX]; 115 116 struct clk *byte_clk; 117 struct clk *esc_clk; 118 struct clk *pixel_clk; 119 struct clk *byte_clk_src; 120 struct clk *pixel_clk_src; 121 struct clk *byte_intf_clk; 122 123 unsigned long byte_clk_rate; 124 unsigned long pixel_clk_rate; 125 unsigned long esc_clk_rate; 126 127 /* DSI v2 specific clocks */ 128 struct clk *src_clk; 129 struct clk *esc_clk_src; 130 struct clk *dsi_clk_src; 131 132 unsigned long src_clk_rate; 133 134 struct gpio_desc *disp_en_gpio; 135 struct gpio_desc *te_gpio; 136 137 const struct msm_dsi_cfg_handler *cfg_hnd; 138 139 struct completion dma_comp; 140 struct completion video_comp; 141 struct mutex dev_mutex; 142 struct mutex cmd_mutex; 143 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 144 145 u32 err_work_state; 146 struct work_struct err_work; 147 struct work_struct hpd_work; 148 struct workqueue_struct *workqueue; 149 150 /* DSI 6G TX buffer*/ 151 struct drm_gem_object *tx_gem_obj; 152 153 /* DSI v2 TX buffer */ 154 void *tx_buf; 155 dma_addr_t tx_buf_paddr; 156 157 int tx_size; 158 159 u8 *rx_buf; 160 161 struct regmap *sfpb; 162 163 struct drm_display_mode *mode; 164 struct msm_display_dsc_config *dsc; 165 166 /* connected device info */ 167 struct device_node *device_node; 168 unsigned int channel; 169 unsigned int lanes; 170 enum mipi_dsi_pixel_format format; 171 unsigned long mode_flags; 172 173 /* lane data parsed via DT */ 174 int dlane_swap; 175 int num_data_lanes; 176 177 /* from phy DT */ 178 bool cphy_mode; 179 180 u32 dma_cmd_ctrl_restore; 181 182 bool registered; 183 bool power_on; 184 bool enabled; 185 int irq; 186 }; 187 188 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt) 189 { 190 switch (fmt) { 191 case MIPI_DSI_FMT_RGB565: return 16; 192 case MIPI_DSI_FMT_RGB666_PACKED: return 18; 193 case MIPI_DSI_FMT_RGB666: 194 case MIPI_DSI_FMT_RGB888: 195 default: return 24; 196 } 197 } 198 199 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 200 { 201 return msm_readl(msm_host->ctrl_base + reg); 202 } 203 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 204 { 205 msm_writel(data, msm_host->ctrl_base + reg); 206 } 207 208 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host); 209 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host); 210 211 static const struct msm_dsi_cfg_handler *dsi_get_config( 212 struct msm_dsi_host *msm_host) 213 { 214 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 215 struct device *dev = &msm_host->pdev->dev; 216 struct clk *ahb_clk; 217 int ret; 218 u32 major = 0, minor = 0; 219 220 cfg_hnd = device_get_match_data(dev); 221 if (cfg_hnd) 222 return cfg_hnd; 223 224 ahb_clk = msm_clk_get(msm_host->pdev, "iface"); 225 if (IS_ERR(ahb_clk)) { 226 pr_err("%s: cannot get interface clock\n", __func__); 227 goto exit; 228 } 229 230 pm_runtime_get_sync(dev); 231 232 ret = clk_prepare_enable(ahb_clk); 233 if (ret) { 234 pr_err("%s: unable to enable ahb_clk\n", __func__); 235 goto runtime_put; 236 } 237 238 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 239 if (ret) { 240 pr_err("%s: Invalid version\n", __func__); 241 goto disable_clks; 242 } 243 244 cfg_hnd = msm_dsi_cfg_get(major, minor); 245 246 DBG("%s: Version %x:%x\n", __func__, major, minor); 247 248 disable_clks: 249 clk_disable_unprepare(ahb_clk); 250 runtime_put: 251 pm_runtime_put_sync(dev); 252 exit: 253 return cfg_hnd; 254 } 255 256 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 257 { 258 return container_of(host, struct msm_dsi_host, base); 259 } 260 261 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host) 262 { 263 struct regulator_bulk_data *s = msm_host->supplies; 264 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 265 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 266 int i; 267 268 DBG(""); 269 for (i = num - 1; i >= 0; i--) 270 if (regs[i].disable_load >= 0) 271 regulator_set_load(s[i].consumer, 272 regs[i].disable_load); 273 274 regulator_bulk_disable(num, s); 275 } 276 277 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host) 278 { 279 struct regulator_bulk_data *s = msm_host->supplies; 280 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 281 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 282 int ret, i; 283 284 DBG(""); 285 for (i = 0; i < num; i++) { 286 if (regs[i].enable_load >= 0) { 287 ret = regulator_set_load(s[i].consumer, 288 regs[i].enable_load); 289 if (ret < 0) { 290 pr_err("regulator %d set op mode failed, %d\n", 291 i, ret); 292 goto fail; 293 } 294 } 295 } 296 297 ret = regulator_bulk_enable(num, s); 298 if (ret < 0) { 299 pr_err("regulator enable failed, %d\n", ret); 300 goto fail; 301 } 302 303 return 0; 304 305 fail: 306 for (i--; i >= 0; i--) 307 regulator_set_load(s[i].consumer, regs[i].disable_load); 308 return ret; 309 } 310 311 static int dsi_regulator_init(struct msm_dsi_host *msm_host) 312 { 313 struct regulator_bulk_data *s = msm_host->supplies; 314 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 315 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 316 int i, ret; 317 318 for (i = 0; i < num; i++) 319 s[i].supply = regs[i].name; 320 321 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s); 322 if (ret < 0) { 323 pr_err("%s: failed to init regulator, ret=%d\n", 324 __func__, ret); 325 return ret; 326 } 327 328 return 0; 329 } 330 331 int dsi_clk_init_v2(struct msm_dsi_host *msm_host) 332 { 333 struct platform_device *pdev = msm_host->pdev; 334 int ret = 0; 335 336 msm_host->src_clk = msm_clk_get(pdev, "src"); 337 338 if (IS_ERR(msm_host->src_clk)) { 339 ret = PTR_ERR(msm_host->src_clk); 340 pr_err("%s: can't find src clock. ret=%d\n", 341 __func__, ret); 342 msm_host->src_clk = NULL; 343 return ret; 344 } 345 346 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk); 347 if (!msm_host->esc_clk_src) { 348 ret = -ENODEV; 349 pr_err("%s: can't get esc clock parent. ret=%d\n", 350 __func__, ret); 351 return ret; 352 } 353 354 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk); 355 if (!msm_host->dsi_clk_src) { 356 ret = -ENODEV; 357 pr_err("%s: can't get src clock parent. ret=%d\n", 358 __func__, ret); 359 } 360 361 return ret; 362 } 363 364 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) 365 { 366 struct platform_device *pdev = msm_host->pdev; 367 int ret = 0; 368 369 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); 370 if (IS_ERR(msm_host->byte_intf_clk)) { 371 ret = PTR_ERR(msm_host->byte_intf_clk); 372 pr_err("%s: can't find byte_intf clock. ret=%d\n", 373 __func__, ret); 374 } 375 376 return ret; 377 } 378 379 static int dsi_clk_init(struct msm_dsi_host *msm_host) 380 { 381 struct platform_device *pdev = msm_host->pdev; 382 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 383 const struct msm_dsi_config *cfg = cfg_hnd->cfg; 384 int i, ret = 0; 385 386 /* get bus clocks */ 387 for (i = 0; i < cfg->num_bus_clks; i++) 388 msm_host->bus_clks[i].id = cfg->bus_clk_names[i]; 389 msm_host->num_bus_clks = cfg->num_bus_clks; 390 391 ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks); 392 if (ret < 0) { 393 dev_err(&pdev->dev, "Unable to get clocks, ret = %d\n", ret); 394 goto exit; 395 } 396 397 /* get link and source clocks */ 398 msm_host->byte_clk = msm_clk_get(pdev, "byte"); 399 if (IS_ERR(msm_host->byte_clk)) { 400 ret = PTR_ERR(msm_host->byte_clk); 401 pr_err("%s: can't find dsi_byte clock. ret=%d\n", 402 __func__, ret); 403 msm_host->byte_clk = NULL; 404 goto exit; 405 } 406 407 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); 408 if (IS_ERR(msm_host->pixel_clk)) { 409 ret = PTR_ERR(msm_host->pixel_clk); 410 pr_err("%s: can't find dsi_pixel clock. ret=%d\n", 411 __func__, ret); 412 msm_host->pixel_clk = NULL; 413 goto exit; 414 } 415 416 msm_host->esc_clk = msm_clk_get(pdev, "core"); 417 if (IS_ERR(msm_host->esc_clk)) { 418 ret = PTR_ERR(msm_host->esc_clk); 419 pr_err("%s: can't find dsi_esc clock. ret=%d\n", 420 __func__, ret); 421 msm_host->esc_clk = NULL; 422 goto exit; 423 } 424 425 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk); 426 if (IS_ERR(msm_host->byte_clk_src)) { 427 ret = PTR_ERR(msm_host->byte_clk_src); 428 pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret); 429 goto exit; 430 } 431 432 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk); 433 if (IS_ERR(msm_host->pixel_clk_src)) { 434 ret = PTR_ERR(msm_host->pixel_clk_src); 435 pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret); 436 goto exit; 437 } 438 439 if (cfg_hnd->ops->clk_init_ver) 440 ret = cfg_hnd->ops->clk_init_ver(msm_host); 441 exit: 442 return ret; 443 } 444 445 int msm_dsi_runtime_suspend(struct device *dev) 446 { 447 struct platform_device *pdev = to_platform_device(dev); 448 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 449 struct mipi_dsi_host *host = msm_dsi->host; 450 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 451 452 if (!msm_host->cfg_hnd) 453 return 0; 454 455 clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks); 456 457 return 0; 458 } 459 460 int msm_dsi_runtime_resume(struct device *dev) 461 { 462 struct platform_device *pdev = to_platform_device(dev); 463 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 464 struct mipi_dsi_host *host = msm_dsi->host; 465 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 466 467 if (!msm_host->cfg_hnd) 468 return 0; 469 470 return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks); 471 } 472 473 int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) 474 { 475 unsigned long byte_intf_rate; 476 int ret; 477 478 DBG("Set clk rates: pclk=%d, byteclk=%lu", 479 msm_host->mode->clock, msm_host->byte_clk_rate); 480 481 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, 482 msm_host->byte_clk_rate); 483 if (ret) { 484 pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret); 485 return ret; 486 } 487 488 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 489 if (ret) { 490 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 491 return ret; 492 } 493 494 if (msm_host->byte_intf_clk) { 495 /* For CPHY, byte_intf_clk is same as byte_clk */ 496 if (msm_host->cphy_mode) 497 byte_intf_rate = msm_host->byte_clk_rate; 498 else 499 byte_intf_rate = msm_host->byte_clk_rate / 2; 500 501 ret = clk_set_rate(msm_host->byte_intf_clk, byte_intf_rate); 502 if (ret) { 503 pr_err("%s: Failed to set rate byte intf clk, %d\n", 504 __func__, ret); 505 return ret; 506 } 507 } 508 509 return 0; 510 } 511 512 513 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) 514 { 515 int ret; 516 517 ret = clk_prepare_enable(msm_host->esc_clk); 518 if (ret) { 519 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 520 goto error; 521 } 522 523 ret = clk_prepare_enable(msm_host->byte_clk); 524 if (ret) { 525 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 526 goto byte_clk_err; 527 } 528 529 ret = clk_prepare_enable(msm_host->pixel_clk); 530 if (ret) { 531 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 532 goto pixel_clk_err; 533 } 534 535 ret = clk_prepare_enable(msm_host->byte_intf_clk); 536 if (ret) { 537 pr_err("%s: Failed to enable byte intf clk\n", 538 __func__); 539 goto byte_intf_clk_err; 540 } 541 542 return 0; 543 544 byte_intf_clk_err: 545 clk_disable_unprepare(msm_host->pixel_clk); 546 pixel_clk_err: 547 clk_disable_unprepare(msm_host->byte_clk); 548 byte_clk_err: 549 clk_disable_unprepare(msm_host->esc_clk); 550 error: 551 return ret; 552 } 553 554 int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host) 555 { 556 int ret; 557 558 DBG("Set clk rates: pclk=%d, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu", 559 msm_host->mode->clock, msm_host->byte_clk_rate, 560 msm_host->esc_clk_rate, msm_host->src_clk_rate); 561 562 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 563 if (ret) { 564 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 565 return ret; 566 } 567 568 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); 569 if (ret) { 570 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); 571 return ret; 572 } 573 574 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); 575 if (ret) { 576 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); 577 return ret; 578 } 579 580 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 581 if (ret) { 582 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 583 return ret; 584 } 585 586 return 0; 587 } 588 589 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) 590 { 591 int ret; 592 593 ret = clk_prepare_enable(msm_host->byte_clk); 594 if (ret) { 595 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 596 goto error; 597 } 598 599 ret = clk_prepare_enable(msm_host->esc_clk); 600 if (ret) { 601 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 602 goto esc_clk_err; 603 } 604 605 ret = clk_prepare_enable(msm_host->src_clk); 606 if (ret) { 607 pr_err("%s: Failed to enable dsi src clk\n", __func__); 608 goto src_clk_err; 609 } 610 611 ret = clk_prepare_enable(msm_host->pixel_clk); 612 if (ret) { 613 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 614 goto pixel_clk_err; 615 } 616 617 return 0; 618 619 pixel_clk_err: 620 clk_disable_unprepare(msm_host->src_clk); 621 src_clk_err: 622 clk_disable_unprepare(msm_host->esc_clk); 623 esc_clk_err: 624 clk_disable_unprepare(msm_host->byte_clk); 625 error: 626 return ret; 627 } 628 629 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) 630 { 631 /* Drop the performance state vote */ 632 dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); 633 clk_disable_unprepare(msm_host->esc_clk); 634 clk_disable_unprepare(msm_host->pixel_clk); 635 clk_disable_unprepare(msm_host->byte_intf_clk); 636 clk_disable_unprepare(msm_host->byte_clk); 637 } 638 639 void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) 640 { 641 clk_disable_unprepare(msm_host->pixel_clk); 642 clk_disable_unprepare(msm_host->src_clk); 643 clk_disable_unprepare(msm_host->esc_clk); 644 clk_disable_unprepare(msm_host->byte_clk); 645 } 646 647 static unsigned long dsi_get_pclk_rate(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 648 { 649 struct drm_display_mode *mode = msm_host->mode; 650 unsigned long pclk_rate; 651 652 pclk_rate = mode->clock * 1000; 653 654 /* 655 * For bonded DSI mode, the current DRM mode has the complete width of the 656 * panel. Since, the complete panel is driven by two DSI controllers, 657 * the clock rates have to be split between the two dsi controllers. 658 * Adjust the byte and pixel clock rates for each dsi host accordingly. 659 */ 660 if (is_bonded_dsi) 661 pclk_rate /= 2; 662 663 return pclk_rate; 664 } 665 666 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 667 { 668 u8 lanes = msm_host->lanes; 669 u32 bpp = dsi_get_bpp(msm_host->format); 670 unsigned long pclk_rate = dsi_get_pclk_rate(msm_host, is_bonded_dsi); 671 u64 pclk_bpp = (u64)pclk_rate * bpp; 672 673 if (lanes == 0) { 674 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 675 lanes = 1; 676 } 677 678 /* CPHY "byte_clk" is in units of 16 bits */ 679 if (msm_host->cphy_mode) 680 do_div(pclk_bpp, (16 * lanes)); 681 else 682 do_div(pclk_bpp, (8 * lanes)); 683 684 msm_host->pixel_clk_rate = pclk_rate; 685 msm_host->byte_clk_rate = pclk_bpp; 686 687 DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate, 688 msm_host->byte_clk_rate); 689 690 } 691 692 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 693 { 694 if (!msm_host->mode) { 695 pr_err("%s: mode not set\n", __func__); 696 return -EINVAL; 697 } 698 699 dsi_calc_pclk(msm_host, is_bonded_dsi); 700 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); 701 return 0; 702 } 703 704 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 705 { 706 u32 bpp = dsi_get_bpp(msm_host->format); 707 u64 pclk_bpp; 708 unsigned int esc_mhz, esc_div; 709 unsigned long byte_mhz; 710 711 dsi_calc_pclk(msm_host, is_bonded_dsi); 712 713 pclk_bpp = (u64)dsi_get_pclk_rate(msm_host, is_bonded_dsi) * bpp; 714 do_div(pclk_bpp, 8); 715 msm_host->src_clk_rate = pclk_bpp; 716 717 /* 718 * esc clock is byte clock followed by a 4 bit divider, 719 * we need to find an escape clock frequency within the 720 * mipi DSI spec range within the maximum divider limit 721 * We iterate here between an escape clock frequencey 722 * between 20 Mhz to 5 Mhz and pick up the first one 723 * that can be supported by our divider 724 */ 725 726 byte_mhz = msm_host->byte_clk_rate / 1000000; 727 728 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { 729 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); 730 731 /* 732 * TODO: Ideally, we shouldn't know what sort of divider 733 * is available in mmss_cc, we're just assuming that 734 * it'll always be a 4 bit divider. Need to come up with 735 * a better way here. 736 */ 737 if (esc_div >= 1 && esc_div <= 16) 738 break; 739 } 740 741 if (esc_mhz < 5) 742 return -EINVAL; 743 744 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; 745 746 DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate, 747 msm_host->src_clk_rate); 748 749 return 0; 750 } 751 752 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 753 { 754 u32 intr; 755 unsigned long flags; 756 757 spin_lock_irqsave(&msm_host->intr_lock, flags); 758 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 759 760 if (enable) 761 intr |= mask; 762 else 763 intr &= ~mask; 764 765 DBG("intr=%x enable=%d", intr, enable); 766 767 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 768 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 769 } 770 771 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 772 { 773 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 774 return BURST_MODE; 775 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 776 return NON_BURST_SYNCH_PULSE; 777 778 return NON_BURST_SYNCH_EVENT; 779 } 780 781 static inline enum dsi_vid_dst_format dsi_get_vid_fmt( 782 const enum mipi_dsi_pixel_format mipi_fmt) 783 { 784 switch (mipi_fmt) { 785 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 786 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 787 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 788 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 789 default: return VID_DST_FORMAT_RGB888; 790 } 791 } 792 793 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( 794 const enum mipi_dsi_pixel_format mipi_fmt) 795 { 796 switch (mipi_fmt) { 797 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 798 case MIPI_DSI_FMT_RGB666_PACKED: 799 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; 800 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 801 default: return CMD_DST_FORMAT_RGB888; 802 } 803 } 804 805 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, 806 struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy) 807 { 808 u32 flags = msm_host->mode_flags; 809 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 810 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 811 u32 data = 0, lane_ctrl = 0; 812 813 if (!enable) { 814 dsi_write(msm_host, REG_DSI_CTRL, 0); 815 return; 816 } 817 818 if (flags & MIPI_DSI_MODE_VIDEO) { 819 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 820 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 821 if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 822 data |= DSI_VID_CFG0_HFP_POWER_STOP; 823 if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 824 data |= DSI_VID_CFG0_HBP_POWER_STOP; 825 if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 826 data |= DSI_VID_CFG0_HSA_POWER_STOP; 827 /* Always set low power stop mode for BLLP 828 * to let command engine send packets 829 */ 830 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 831 DSI_VID_CFG0_BLLP_POWER_STOP; 832 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 833 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 834 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 835 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 836 837 /* Do not swap RGB colors */ 838 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 839 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 840 } else { 841 /* Do not swap RGB colors */ 842 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 843 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 844 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 845 846 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 847 DSI_CMD_CFG1_WR_MEM_CONTINUE( 848 MIPI_DCS_WRITE_MEMORY_CONTINUE); 849 /* Always insert DCS command */ 850 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 851 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 852 } 853 854 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 855 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 856 DSI_CMD_DMA_CTRL_LOW_POWER); 857 858 data = 0; 859 /* Always assume dedicated TE pin */ 860 data |= DSI_TRIG_CTRL_TE; 861 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 862 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 863 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 864 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 865 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 866 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 867 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 868 869 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | 870 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); 871 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 872 873 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 874 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && 875 phy_shared_timings->clk_pre_inc_by_2) 876 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND, 877 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); 878 879 data = 0; 880 if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET)) 881 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 882 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 883 884 /* allow only ack-err-status to generate interrupt */ 885 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 886 887 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 888 889 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 890 891 data = DSI_CTRL_CLK_EN; 892 893 DBG("lane number=%d", msm_host->lanes); 894 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); 895 896 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 897 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); 898 899 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) { 900 lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL); 901 902 if (msm_dsi_phy_set_continuous_clock(phy, enable)) 903 lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY; 904 905 dsi_write(msm_host, REG_DSI_LANE_CTRL, 906 lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); 907 } 908 909 data |= DSI_CTRL_ENABLE; 910 911 dsi_write(msm_host, REG_DSI_CTRL, data); 912 913 if (msm_host->cphy_mode) 914 dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0)); 915 } 916 917 static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay) 918 { 919 struct msm_display_dsc_config *dsc = msm_host->dsc; 920 u32 reg, intf_width, reg_ctrl, reg_ctrl2; 921 u32 slice_per_intf, total_bytes_per_intf; 922 u32 pkt_per_line; 923 u32 bytes_in_slice; 924 u32 eol_byte_num; 925 926 /* first calculate dsc parameters and then program 927 * compress mode registers 928 */ 929 intf_width = hdisplay; 930 slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width); 931 932 /* If slice_per_pkt is greater than slice_per_intf 933 * then default to 1. This can happen during partial 934 * update. 935 */ 936 if (slice_per_intf > dsc->drm->slice_count) 937 dsc->drm->slice_count = 1; 938 939 slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm->slice_width); 940 bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * dsc->drm->bits_per_pixel, 8); 941 942 dsc->drm->slice_chunk_size = bytes_in_slice; 943 944 total_bytes_per_intf = bytes_in_slice * slice_per_intf; 945 946 eol_byte_num = total_bytes_per_intf % 3; 947 pkt_per_line = slice_per_intf / dsc->drm->slice_count; 948 949 if (is_cmd_mode) /* packet data type */ 950 reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE); 951 else 952 reg = DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(MIPI_DSI_COMPRESSED_PIXEL_STREAM); 953 954 /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE 955 * registers have similar offsets, so for below common code use 956 * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits 957 */ 958 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); 959 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); 960 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN; 961 962 if (is_cmd_mode) { 963 reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); 964 reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); 965 966 reg_ctrl &= ~0xffff; 967 reg_ctrl |= reg; 968 969 reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; 970 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(bytes_in_slice); 971 972 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); 973 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); 974 } else { 975 dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); 976 } 977 } 978 979 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 980 { 981 struct drm_display_mode *mode = msm_host->mode; 982 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 983 u32 h_total = mode->htotal; 984 u32 v_total = mode->vtotal; 985 u32 hs_end = mode->hsync_end - mode->hsync_start; 986 u32 vs_end = mode->vsync_end - mode->vsync_start; 987 u32 ha_start = h_total - mode->hsync_start; 988 u32 ha_end = ha_start + mode->hdisplay; 989 u32 va_start = v_total - mode->vsync_start; 990 u32 va_end = va_start + mode->vdisplay; 991 u32 hdisplay = mode->hdisplay; 992 u32 wc; 993 994 DBG(""); 995 996 /* 997 * For bonded DSI mode, the current DRM mode has 998 * the complete width of the panel. Since, the complete 999 * panel is driven by two DSI controllers, the horizontal 1000 * timings have to be split between the two dsi controllers. 1001 * Adjust the DSI host timing values accordingly. 1002 */ 1003 if (is_bonded_dsi) { 1004 h_total /= 2; 1005 hs_end /= 2; 1006 ha_start /= 2; 1007 ha_end /= 2; 1008 hdisplay /= 2; 1009 } 1010 1011 if (msm_host->dsc) { 1012 struct msm_display_dsc_config *dsc = msm_host->dsc; 1013 1014 /* update dsc params with timing params */ 1015 if (!dsc || !mode->hdisplay || !mode->vdisplay) { 1016 pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", 1017 mode->hdisplay, mode->vdisplay); 1018 return; 1019 } 1020 1021 dsc->drm->pic_width = mode->hdisplay; 1022 dsc->drm->pic_height = mode->vdisplay; 1023 DBG("Mode %dx%d\n", dsc->drm->pic_width, dsc->drm->pic_height); 1024 1025 /* we do the calculations for dsc parameters here so that 1026 * panel can use these parameters 1027 */ 1028 dsi_populate_dsc_params(dsc); 1029 1030 /* Divide the display by 3 but keep back/font porch and 1031 * pulse width same 1032 */ 1033 h_total -= hdisplay; 1034 hdisplay /= 3; 1035 h_total += hdisplay; 1036 ha_end = ha_start + hdisplay; 1037 } 1038 1039 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 1040 if (msm_host->dsc) 1041 dsi_update_dsc_timing(msm_host, false, mode->hdisplay); 1042 1043 dsi_write(msm_host, REG_DSI_ACTIVE_H, 1044 DSI_ACTIVE_H_START(ha_start) | 1045 DSI_ACTIVE_H_END(ha_end)); 1046 dsi_write(msm_host, REG_DSI_ACTIVE_V, 1047 DSI_ACTIVE_V_START(va_start) | 1048 DSI_ACTIVE_V_END(va_end)); 1049 dsi_write(msm_host, REG_DSI_TOTAL, 1050 DSI_TOTAL_H_TOTAL(h_total - 1) | 1051 DSI_TOTAL_V_TOTAL(v_total - 1)); 1052 1053 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 1054 DSI_ACTIVE_HSYNC_START(hs_start) | 1055 DSI_ACTIVE_HSYNC_END(hs_end)); 1056 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 1057 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 1058 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 1059 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 1060 } else { /* command mode */ 1061 if (msm_host->dsc) 1062 dsi_update_dsc_timing(msm_host, true, mode->hdisplay); 1063 1064 /* image data and 1 byte write_memory_start cmd */ 1065 if (!msm_host->dsc) 1066 wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; 1067 else 1068 wc = mode->hdisplay / 2 + 1; 1069 1070 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, 1071 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | 1072 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( 1073 msm_host->channel) | 1074 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( 1075 MIPI_DSI_DCS_LONG_WRITE)); 1076 1077 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, 1078 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | 1079 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); 1080 } 1081 } 1082 1083 static void dsi_sw_reset(struct msm_dsi_host *msm_host) 1084 { 1085 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1086 wmb(); /* clocks need to be enabled before reset */ 1087 1088 dsi_write(msm_host, REG_DSI_RESET, 1); 1089 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 1090 dsi_write(msm_host, REG_DSI_RESET, 0); 1091 } 1092 1093 static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 1094 bool video_mode, bool enable) 1095 { 1096 u32 dsi_ctrl; 1097 1098 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1099 1100 if (!enable) { 1101 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 1102 DSI_CTRL_CMD_MODE_EN); 1103 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 1104 DSI_IRQ_MASK_VIDEO_DONE, 0); 1105 } else { 1106 if (video_mode) { 1107 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 1108 } else { /* command mode */ 1109 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 1110 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 1111 } 1112 dsi_ctrl |= DSI_CTRL_ENABLE; 1113 } 1114 1115 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 1116 } 1117 1118 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 1119 { 1120 u32 data; 1121 1122 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 1123 1124 if (mode == 0) 1125 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 1126 else 1127 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 1128 1129 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 1130 } 1131 1132 static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 1133 { 1134 u32 ret = 0; 1135 struct device *dev = &msm_host->pdev->dev; 1136 1137 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 1138 1139 reinit_completion(&msm_host->video_comp); 1140 1141 ret = wait_for_completion_timeout(&msm_host->video_comp, 1142 msecs_to_jiffies(70)); 1143 1144 if (ret == 0) 1145 DRM_DEV_ERROR(dev, "wait for video done timed out\n"); 1146 1147 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 1148 } 1149 1150 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 1151 { 1152 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 1153 return; 1154 1155 if (msm_host->power_on && msm_host->enabled) { 1156 dsi_wait4video_done(msm_host); 1157 /* delay 4 ms to skip BLLP */ 1158 usleep_range(2000, 4000); 1159 } 1160 } 1161 1162 int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) 1163 { 1164 struct drm_device *dev = msm_host->dev; 1165 struct msm_drm_private *priv = dev->dev_private; 1166 uint64_t iova; 1167 u8 *data; 1168 1169 data = msm_gem_kernel_new(dev, size, MSM_BO_WC, 1170 priv->kms->aspace, 1171 &msm_host->tx_gem_obj, &iova); 1172 1173 if (IS_ERR(data)) { 1174 msm_host->tx_gem_obj = NULL; 1175 return PTR_ERR(data); 1176 } 1177 1178 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem"); 1179 1180 msm_host->tx_size = msm_host->tx_gem_obj->size; 1181 1182 return 0; 1183 } 1184 1185 int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) 1186 { 1187 struct drm_device *dev = msm_host->dev; 1188 1189 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, 1190 &msm_host->tx_buf_paddr, GFP_KERNEL); 1191 if (!msm_host->tx_buf) 1192 return -ENOMEM; 1193 1194 msm_host->tx_size = size; 1195 1196 return 0; 1197 } 1198 1199 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host) 1200 { 1201 struct drm_device *dev = msm_host->dev; 1202 struct msm_drm_private *priv; 1203 1204 /* 1205 * This is possible if we're tearing down before we've had a chance to 1206 * fully initialize. A very real possibility if our probe is deferred, 1207 * in which case we'll hit msm_dsi_host_destroy() without having run 1208 * through the dsi_tx_buf_alloc(). 1209 */ 1210 if (!dev) 1211 return; 1212 1213 priv = dev->dev_private; 1214 if (msm_host->tx_gem_obj) { 1215 msm_gem_unpin_iova(msm_host->tx_gem_obj, priv->kms->aspace); 1216 drm_gem_object_put(msm_host->tx_gem_obj); 1217 msm_host->tx_gem_obj = NULL; 1218 } 1219 1220 if (msm_host->tx_buf) 1221 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, 1222 msm_host->tx_buf_paddr); 1223 } 1224 1225 void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host) 1226 { 1227 return msm_gem_get_vaddr(msm_host->tx_gem_obj); 1228 } 1229 1230 void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host) 1231 { 1232 return msm_host->tx_buf; 1233 } 1234 1235 void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host) 1236 { 1237 msm_gem_put_vaddr(msm_host->tx_gem_obj); 1238 } 1239 1240 /* 1241 * prepare cmd buffer to be txed 1242 */ 1243 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, 1244 const struct mipi_dsi_msg *msg) 1245 { 1246 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1247 struct mipi_dsi_packet packet; 1248 int len; 1249 int ret; 1250 u8 *data; 1251 1252 ret = mipi_dsi_create_packet(&packet, msg); 1253 if (ret) { 1254 pr_err("%s: create packet failed, %d\n", __func__, ret); 1255 return ret; 1256 } 1257 len = (packet.size + 3) & (~0x3); 1258 1259 if (len > msm_host->tx_size) { 1260 pr_err("%s: packet size is too big\n", __func__); 1261 return -EINVAL; 1262 } 1263 1264 data = cfg_hnd->ops->tx_buf_get(msm_host); 1265 if (IS_ERR(data)) { 1266 ret = PTR_ERR(data); 1267 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 1268 return ret; 1269 } 1270 1271 /* MSM specific command format in memory */ 1272 data[0] = packet.header[1]; 1273 data[1] = packet.header[2]; 1274 data[2] = packet.header[0]; 1275 data[3] = BIT(7); /* Last packet */ 1276 if (mipi_dsi_packet_format_is_long(msg->type)) 1277 data[3] |= BIT(6); 1278 if (msg->rx_buf && msg->rx_len) 1279 data[3] |= BIT(5); 1280 1281 /* Long packet */ 1282 if (packet.payload && packet.payload_length) 1283 memcpy(data + 4, packet.payload, packet.payload_length); 1284 1285 /* Append 0xff to the end */ 1286 if (packet.size < len) 1287 memset(data + packet.size, 0xff, len - packet.size); 1288 1289 if (cfg_hnd->ops->tx_buf_put) 1290 cfg_hnd->ops->tx_buf_put(msm_host); 1291 1292 return len; 1293 } 1294 1295 /* 1296 * dsi_short_read1_resp: 1 parameter 1297 */ 1298 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1299 { 1300 u8 *data = msg->rx_buf; 1301 if (data && (msg->rx_len >= 1)) { 1302 *data = buf[1]; /* strip out dcs type */ 1303 return 1; 1304 } else { 1305 pr_err("%s: read data does not match with rx_buf len %zu\n", 1306 __func__, msg->rx_len); 1307 return -EINVAL; 1308 } 1309 } 1310 1311 /* 1312 * dsi_short_read2_resp: 2 parameter 1313 */ 1314 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1315 { 1316 u8 *data = msg->rx_buf; 1317 if (data && (msg->rx_len >= 2)) { 1318 data[0] = buf[1]; /* strip out dcs type */ 1319 data[1] = buf[2]; 1320 return 2; 1321 } else { 1322 pr_err("%s: read data does not match with rx_buf len %zu\n", 1323 __func__, msg->rx_len); 1324 return -EINVAL; 1325 } 1326 } 1327 1328 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1329 { 1330 /* strip out 4 byte dcs header */ 1331 if (msg->rx_buf && msg->rx_len) 1332 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 1333 1334 return msg->rx_len; 1335 } 1336 1337 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1338 { 1339 struct drm_device *dev = msm_host->dev; 1340 struct msm_drm_private *priv = dev->dev_private; 1341 1342 if (!dma_base) 1343 return -EINVAL; 1344 1345 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, 1346 priv->kms->aspace, dma_base); 1347 } 1348 1349 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1350 { 1351 if (!dma_base) 1352 return -EINVAL; 1353 1354 *dma_base = msm_host->tx_buf_paddr; 1355 return 0; 1356 } 1357 1358 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 1359 { 1360 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1361 int ret; 1362 uint64_t dma_base; 1363 bool triggered; 1364 1365 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); 1366 if (ret) { 1367 pr_err("%s: failed to get iova: %d\n", __func__, ret); 1368 return ret; 1369 } 1370 1371 reinit_completion(&msm_host->dma_comp); 1372 1373 dsi_wait4video_eng_busy(msm_host); 1374 1375 triggered = msm_dsi_manager_cmd_xfer_trigger( 1376 msm_host->id, dma_base, len); 1377 if (triggered) { 1378 ret = wait_for_completion_timeout(&msm_host->dma_comp, 1379 msecs_to_jiffies(200)); 1380 DBG("ret=%d", ret); 1381 if (ret == 0) 1382 ret = -ETIMEDOUT; 1383 else 1384 ret = len; 1385 } else 1386 ret = len; 1387 1388 return ret; 1389 } 1390 1391 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1392 u8 *buf, int rx_byte, int pkt_size) 1393 { 1394 u32 *temp, data; 1395 int i, j = 0, cnt; 1396 u32 read_cnt; 1397 u8 reg[16]; 1398 int repeated_bytes = 0; 1399 int buf_offset = buf - msm_host->rx_buf; 1400 1401 temp = (u32 *)reg; 1402 cnt = (rx_byte + 3) >> 2; 1403 if (cnt > 4) 1404 cnt = 4; /* 4 x 32 bits registers only */ 1405 1406 if (rx_byte == 4) 1407 read_cnt = 4; 1408 else 1409 read_cnt = pkt_size + 6; 1410 1411 /* 1412 * In case of multiple reads from the panel, after the first read, there 1413 * is possibility that there are some bytes in the payload repeating in 1414 * the RDBK_DATA registers. Since we read all the parameters from the 1415 * panel right from the first byte for every pass. We need to skip the 1416 * repeating bytes and then append the new parameters to the rx buffer. 1417 */ 1418 if (read_cnt > 16) { 1419 int bytes_shifted; 1420 /* Any data more than 16 bytes will be shifted out. 1421 * The temp read buffer should already contain these bytes. 1422 * The remaining bytes in read buffer are the repeated bytes. 1423 */ 1424 bytes_shifted = read_cnt - 16; 1425 repeated_bytes = buf_offset - bytes_shifted; 1426 } 1427 1428 for (i = cnt - 1; i >= 0; i--) { 1429 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1430 *temp++ = ntohl(data); /* to host byte order */ 1431 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1432 } 1433 1434 for (i = repeated_bytes; i < 16; i++) 1435 buf[j++] = reg[i]; 1436 1437 return j; 1438 } 1439 1440 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1441 const struct mipi_dsi_msg *msg) 1442 { 1443 int len, ret; 1444 int bllp_len = msm_host->mode->hdisplay * 1445 dsi_get_bpp(msm_host->format) / 8; 1446 1447 len = dsi_cmd_dma_add(msm_host, msg); 1448 if (len < 0) { 1449 pr_err("%s: failed to add cmd type = 0x%x\n", 1450 __func__, msg->type); 1451 return len; 1452 } 1453 1454 /* for video mode, do not send cmds more than 1455 * one pixel line, since it only transmit it 1456 * during BLLP. 1457 */ 1458 /* TODO: if the command is sent in LP mode, the bit rate is only 1459 * half of esc clk rate. In this case, if the video is already 1460 * actively streaming, we need to check more carefully if the 1461 * command can be fit into one BLLP. 1462 */ 1463 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1464 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1465 __func__, len); 1466 return -EINVAL; 1467 } 1468 1469 ret = dsi_cmd_dma_tx(msm_host, len); 1470 if (ret < 0) { 1471 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n", 1472 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret); 1473 return ret; 1474 } else if (ret < len) { 1475 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n", 1476 __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len); 1477 return -EIO; 1478 } 1479 1480 return len; 1481 } 1482 1483 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host) 1484 { 1485 u32 data0, data1; 1486 1487 data0 = dsi_read(msm_host, REG_DSI_CTRL); 1488 data1 = data0; 1489 data1 &= ~DSI_CTRL_ENABLE; 1490 dsi_write(msm_host, REG_DSI_CTRL, data1); 1491 /* 1492 * dsi controller need to be disabled before 1493 * clocks turned on 1494 */ 1495 wmb(); 1496 1497 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1498 wmb(); /* make sure clocks enabled */ 1499 1500 /* dsi controller can only be reset while clocks are running */ 1501 dsi_write(msm_host, REG_DSI_RESET, 1); 1502 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 1503 dsi_write(msm_host, REG_DSI_RESET, 0); 1504 wmb(); /* controller out of reset */ 1505 dsi_write(msm_host, REG_DSI_CTRL, data0); 1506 wmb(); /* make sure dsi controller enabled again */ 1507 } 1508 1509 static void dsi_hpd_worker(struct work_struct *work) 1510 { 1511 struct msm_dsi_host *msm_host = 1512 container_of(work, struct msm_dsi_host, hpd_work); 1513 1514 drm_helper_hpd_irq_event(msm_host->dev); 1515 } 1516 1517 static void dsi_err_worker(struct work_struct *work) 1518 { 1519 struct msm_dsi_host *msm_host = 1520 container_of(work, struct msm_dsi_host, err_work); 1521 u32 status = msm_host->err_work_state; 1522 1523 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1524 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1525 dsi_sw_reset_restore(msm_host); 1526 1527 /* It is safe to clear here because error irq is disabled. */ 1528 msm_host->err_work_state = 0; 1529 1530 /* enable dsi error interrupt */ 1531 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1532 } 1533 1534 static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1535 { 1536 u32 status; 1537 1538 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1539 1540 if (status) { 1541 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1542 /* Writing of an extra 0 needed to clear error bits */ 1543 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1544 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1545 } 1546 } 1547 1548 static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1549 { 1550 u32 status; 1551 1552 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1553 1554 if (status) { 1555 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1556 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1557 } 1558 } 1559 1560 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1561 { 1562 u32 status; 1563 1564 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1565 1566 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | 1567 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | 1568 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | 1569 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | 1570 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { 1571 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1572 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1573 } 1574 } 1575 1576 static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1577 { 1578 u32 status; 1579 1580 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1581 1582 /* fifo underflow, overflow */ 1583 if (status) { 1584 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1585 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1586 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1587 msm_host->err_work_state |= 1588 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1589 } 1590 } 1591 1592 static void dsi_status(struct msm_dsi_host *msm_host) 1593 { 1594 u32 status; 1595 1596 status = dsi_read(msm_host, REG_DSI_STATUS0); 1597 1598 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1599 dsi_write(msm_host, REG_DSI_STATUS0, status); 1600 msm_host->err_work_state |= 1601 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1602 } 1603 } 1604 1605 static void dsi_clk_status(struct msm_dsi_host *msm_host) 1606 { 1607 u32 status; 1608 1609 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1610 1611 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1612 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1613 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1614 } 1615 } 1616 1617 static void dsi_error(struct msm_dsi_host *msm_host) 1618 { 1619 /* disable dsi error interrupt */ 1620 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1621 1622 dsi_clk_status(msm_host); 1623 dsi_fifo_status(msm_host); 1624 dsi_ack_err_status(msm_host); 1625 dsi_timeout_status(msm_host); 1626 dsi_status(msm_host); 1627 dsi_dln0_phy_err(msm_host); 1628 1629 queue_work(msm_host->workqueue, &msm_host->err_work); 1630 } 1631 1632 static irqreturn_t dsi_host_irq(int irq, void *ptr) 1633 { 1634 struct msm_dsi_host *msm_host = ptr; 1635 u32 isr; 1636 unsigned long flags; 1637 1638 if (!msm_host->ctrl_base) 1639 return IRQ_HANDLED; 1640 1641 spin_lock_irqsave(&msm_host->intr_lock, flags); 1642 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1643 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1644 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1645 1646 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1647 1648 if (isr & DSI_IRQ_ERROR) 1649 dsi_error(msm_host); 1650 1651 if (isr & DSI_IRQ_VIDEO_DONE) 1652 complete(&msm_host->video_comp); 1653 1654 if (isr & DSI_IRQ_CMD_DMA_DONE) 1655 complete(&msm_host->dma_comp); 1656 1657 return IRQ_HANDLED; 1658 } 1659 1660 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, 1661 struct device *panel_device) 1662 { 1663 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device, 1664 "disp-enable", 1665 GPIOD_OUT_LOW); 1666 if (IS_ERR(msm_host->disp_en_gpio)) { 1667 DBG("cannot get disp-enable-gpios %ld", 1668 PTR_ERR(msm_host->disp_en_gpio)); 1669 return PTR_ERR(msm_host->disp_en_gpio); 1670 } 1671 1672 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te", 1673 GPIOD_IN); 1674 if (IS_ERR(msm_host->te_gpio)) { 1675 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); 1676 return PTR_ERR(msm_host->te_gpio); 1677 } 1678 1679 return 0; 1680 } 1681 1682 static int dsi_host_attach(struct mipi_dsi_host *host, 1683 struct mipi_dsi_device *dsi) 1684 { 1685 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1686 int ret; 1687 1688 if (dsi->lanes > msm_host->num_data_lanes) 1689 return -EINVAL; 1690 1691 msm_host->channel = dsi->channel; 1692 msm_host->lanes = dsi->lanes; 1693 msm_host->format = dsi->format; 1694 msm_host->mode_flags = dsi->mode_flags; 1695 1696 /* Some gpios defined in panel DT need to be controlled by host */ 1697 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); 1698 if (ret) 1699 return ret; 1700 1701 ret = dsi_dev_attach(msm_host->pdev); 1702 if (ret) 1703 return ret; 1704 1705 DBG("id=%d", msm_host->id); 1706 if (msm_host->dev) 1707 queue_work(msm_host->workqueue, &msm_host->hpd_work); 1708 1709 return 0; 1710 } 1711 1712 static int dsi_host_detach(struct mipi_dsi_host *host, 1713 struct mipi_dsi_device *dsi) 1714 { 1715 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1716 1717 dsi_dev_detach(msm_host->pdev); 1718 1719 msm_host->device_node = NULL; 1720 1721 DBG("id=%d", msm_host->id); 1722 if (msm_host->dev) 1723 queue_work(msm_host->workqueue, &msm_host->hpd_work); 1724 1725 return 0; 1726 } 1727 1728 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1729 const struct mipi_dsi_msg *msg) 1730 { 1731 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1732 int ret; 1733 1734 if (!msg || !msm_host->power_on) 1735 return -EINVAL; 1736 1737 mutex_lock(&msm_host->cmd_mutex); 1738 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1739 mutex_unlock(&msm_host->cmd_mutex); 1740 1741 return ret; 1742 } 1743 1744 static const struct mipi_dsi_host_ops dsi_host_ops = { 1745 .attach = dsi_host_attach, 1746 .detach = dsi_host_detach, 1747 .transfer = dsi_host_transfer, 1748 }; 1749 1750 /* 1751 * List of supported physical to logical lane mappings. 1752 * For example, the 2nd entry represents the following mapping: 1753 * 1754 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; 1755 */ 1756 static const int supported_data_lane_swaps[][4] = { 1757 { 0, 1, 2, 3 }, 1758 { 3, 0, 1, 2 }, 1759 { 2, 3, 0, 1 }, 1760 { 1, 2, 3, 0 }, 1761 { 0, 3, 2, 1 }, 1762 { 1, 0, 3, 2 }, 1763 { 2, 1, 0, 3 }, 1764 { 3, 2, 1, 0 }, 1765 }; 1766 1767 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, 1768 struct device_node *ep) 1769 { 1770 struct device *dev = &msm_host->pdev->dev; 1771 struct property *prop; 1772 u32 lane_map[4]; 1773 int ret, i, len, num_lanes; 1774 1775 prop = of_find_property(ep, "data-lanes", &len); 1776 if (!prop) { 1777 DRM_DEV_DEBUG(dev, 1778 "failed to find data lane mapping, using default\n"); 1779 /* Set the number of date lanes to 4 by default. */ 1780 msm_host->num_data_lanes = 4; 1781 return 0; 1782 } 1783 1784 num_lanes = drm_of_get_data_lanes_count(ep, 1, 4); 1785 if (num_lanes < 0) { 1786 DRM_DEV_ERROR(dev, "bad number of data lanes\n"); 1787 return num_lanes; 1788 } 1789 1790 msm_host->num_data_lanes = num_lanes; 1791 1792 ret = of_property_read_u32_array(ep, "data-lanes", lane_map, 1793 num_lanes); 1794 if (ret) { 1795 DRM_DEV_ERROR(dev, "failed to read lane data\n"); 1796 return ret; 1797 } 1798 1799 /* 1800 * compare DT specified physical-logical lane mappings with the ones 1801 * supported by hardware 1802 */ 1803 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { 1804 const int *swap = supported_data_lane_swaps[i]; 1805 int j; 1806 1807 /* 1808 * the data-lanes array we get from DT has a logical->physical 1809 * mapping. The "data lane swap" register field represents 1810 * supported configurations in a physical->logical mapping. 1811 * Translate the DT mapping to what we understand and find a 1812 * configuration that works. 1813 */ 1814 for (j = 0; j < num_lanes; j++) { 1815 if (lane_map[j] < 0 || lane_map[j] > 3) 1816 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n", 1817 lane_map[j]); 1818 1819 if (swap[lane_map[j]] != j) 1820 break; 1821 } 1822 1823 if (j == num_lanes) { 1824 msm_host->dlane_swap = i; 1825 return 0; 1826 } 1827 } 1828 1829 return -EINVAL; 1830 } 1831 1832 static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = { 1833 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62, 1834 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e 1835 }; 1836 1837 /* only 8bpc, 8bpp added */ 1838 static char min_qp[DSC_NUM_BUF_RANGES] = { 1839 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13 1840 }; 1841 1842 static char max_qp[DSC_NUM_BUF_RANGES] = { 1843 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15 1844 }; 1845 1846 static char bpg_offset[DSC_NUM_BUF_RANGES] = { 1847 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 1848 }; 1849 1850 static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc) 1851 { 1852 int mux_words_size; 1853 int groups_per_line, groups_total; 1854 int min_rate_buffer_size; 1855 int hrd_delay; 1856 int pre_num_extra_mux_bits, num_extra_mux_bits; 1857 int slice_bits; 1858 int target_bpp_x16; 1859 int data; 1860 int final_value, final_scale; 1861 int i; 1862 1863 dsc->drm->rc_model_size = 8192; 1864 dsc->drm->first_line_bpg_offset = 12; 1865 dsc->drm->rc_edge_factor = 6; 1866 dsc->drm->rc_tgt_offset_high = 3; 1867 dsc->drm->rc_tgt_offset_low = 3; 1868 dsc->drm->simple_422 = 0; 1869 dsc->drm->convert_rgb = 1; 1870 dsc->drm->vbr_enable = 0; 1871 1872 /* handle only bpp = bpc = 8 */ 1873 for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) 1874 dsc->drm->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i]; 1875 1876 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 1877 dsc->drm->rc_range_params[i].range_min_qp = min_qp[i]; 1878 dsc->drm->rc_range_params[i].range_max_qp = max_qp[i]; 1879 dsc->drm->rc_range_params[i].range_bpg_offset = bpg_offset[i]; 1880 } 1881 1882 dsc->drm->initial_offset = 6144; /* Not bpp 12 */ 1883 if (dsc->drm->bits_per_pixel != 8) 1884 dsc->drm->initial_offset = 2048; /* bpp = 12 */ 1885 1886 mux_words_size = 48; /* bpc == 8/10 */ 1887 if (dsc->drm->bits_per_component == 12) 1888 mux_words_size = 64; 1889 1890 dsc->drm->initial_xmit_delay = 512; 1891 dsc->drm->initial_scale_value = 32; 1892 dsc->drm->first_line_bpg_offset = 12; 1893 dsc->drm->line_buf_depth = dsc->drm->bits_per_component + 1; 1894 1895 /* bpc 8 */ 1896 dsc->drm->flatness_min_qp = 3; 1897 dsc->drm->flatness_max_qp = 12; 1898 dsc->drm->rc_quant_incr_limit0 = 11; 1899 dsc->drm->rc_quant_incr_limit1 = 11; 1900 dsc->drm->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; 1901 1902 /* FIXME: need to call drm_dsc_compute_rc_parameters() so that rest of 1903 * params are calculated 1904 */ 1905 groups_per_line = DIV_ROUND_UP(dsc->drm->slice_width, 3); 1906 dsc->drm->slice_chunk_size = dsc->drm->slice_width * dsc->drm->bits_per_pixel / 8; 1907 if ((dsc->drm->slice_width * dsc->drm->bits_per_pixel) % 8) 1908 dsc->drm->slice_chunk_size++; 1909 1910 /* rbs-min */ 1911 min_rate_buffer_size = dsc->drm->rc_model_size - dsc->drm->initial_offset + 1912 dsc->drm->initial_xmit_delay * dsc->drm->bits_per_pixel + 1913 groups_per_line * dsc->drm->first_line_bpg_offset; 1914 1915 hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->drm->bits_per_pixel); 1916 1917 dsc->drm->initial_dec_delay = hrd_delay - dsc->drm->initial_xmit_delay; 1918 1919 dsc->drm->initial_scale_value = 8 * dsc->drm->rc_model_size / 1920 (dsc->drm->rc_model_size - dsc->drm->initial_offset); 1921 1922 slice_bits = 8 * dsc->drm->slice_chunk_size * dsc->drm->slice_height; 1923 1924 groups_total = groups_per_line * dsc->drm->slice_height; 1925 1926 data = dsc->drm->first_line_bpg_offset * 2048; 1927 1928 dsc->drm->nfl_bpg_offset = DIV_ROUND_UP(data, (dsc->drm->slice_height - 1)); 1929 1930 pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * dsc->drm->bits_per_component + 4) - 2); 1931 1932 num_extra_mux_bits = pre_num_extra_mux_bits - (mux_words_size - 1933 ((slice_bits - pre_num_extra_mux_bits) % mux_words_size)); 1934 1935 data = 2048 * (dsc->drm->rc_model_size - dsc->drm->initial_offset + num_extra_mux_bits); 1936 dsc->drm->slice_bpg_offset = DIV_ROUND_UP(data, groups_total); 1937 1938 /* bpp * 16 + 0.5 */ 1939 data = dsc->drm->bits_per_pixel * 16; 1940 data *= 2; 1941 data++; 1942 data /= 2; 1943 target_bpp_x16 = data; 1944 1945 data = (dsc->drm->initial_xmit_delay * target_bpp_x16) / 16; 1946 final_value = dsc->drm->rc_model_size - data + num_extra_mux_bits; 1947 dsc->drm->final_offset = final_value; 1948 1949 final_scale = 8 * dsc->drm->rc_model_size / (dsc->drm->rc_model_size - final_value); 1950 1951 data = (final_scale - 9) * (dsc->drm->nfl_bpg_offset + dsc->drm->slice_bpg_offset); 1952 dsc->drm->scale_increment_interval = (2048 * dsc->drm->final_offset) / data; 1953 1954 dsc->drm->scale_decrement_interval = groups_per_line / (dsc->drm->initial_scale_value - 8); 1955 1956 return 0; 1957 } 1958 1959 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) 1960 { 1961 struct device *dev = &msm_host->pdev->dev; 1962 struct device_node *np = dev->of_node; 1963 struct device_node *endpoint, *device_node; 1964 int ret = 0; 1965 1966 /* 1967 * Get the endpoint of the output port of the DSI host. In our case, 1968 * this is mapped to port number with reg = 1. Don't return an error if 1969 * the remote endpoint isn't defined. It's possible that there is 1970 * nothing connected to the dsi output. 1971 */ 1972 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1973 if (!endpoint) { 1974 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__); 1975 return 0; 1976 } 1977 1978 ret = dsi_host_parse_lane_data(msm_host, endpoint); 1979 if (ret) { 1980 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", 1981 __func__, ret); 1982 ret = -EINVAL; 1983 goto err; 1984 } 1985 1986 /* Get panel node from the output port's endpoint data */ 1987 device_node = of_graph_get_remote_node(np, 1, 0); 1988 if (!device_node) { 1989 DRM_DEV_DEBUG(dev, "%s: no valid device\n", __func__); 1990 ret = -ENODEV; 1991 goto err; 1992 } 1993 1994 msm_host->device_node = device_node; 1995 1996 if (of_property_read_bool(np, "syscon-sfpb")) { 1997 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, 1998 "syscon-sfpb"); 1999 if (IS_ERR(msm_host->sfpb)) { 2000 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n", 2001 __func__); 2002 ret = PTR_ERR(msm_host->sfpb); 2003 } 2004 } 2005 2006 of_node_put(device_node); 2007 2008 err: 2009 of_node_put(endpoint); 2010 2011 return ret; 2012 } 2013 2014 static int dsi_host_get_id(struct msm_dsi_host *msm_host) 2015 { 2016 struct platform_device *pdev = msm_host->pdev; 2017 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 2018 struct resource *res; 2019 int i; 2020 2021 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); 2022 if (!res) 2023 return -EINVAL; 2024 2025 for (i = 0; i < cfg->num_dsi; i++) { 2026 if (cfg->io_start[i] == res->start) 2027 return i; 2028 } 2029 2030 return -EINVAL; 2031 } 2032 2033 int msm_dsi_host_init(struct msm_dsi *msm_dsi) 2034 { 2035 struct msm_dsi_host *msm_host = NULL; 2036 struct platform_device *pdev = msm_dsi->pdev; 2037 int ret; 2038 2039 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 2040 if (!msm_host) { 2041 ret = -ENOMEM; 2042 goto fail; 2043 } 2044 2045 msm_host->pdev = pdev; 2046 msm_dsi->host = &msm_host->base; 2047 2048 ret = dsi_host_parse_dt(msm_host); 2049 if (ret) { 2050 pr_err("%s: failed to parse dt\n", __func__); 2051 goto fail; 2052 } 2053 2054 msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size); 2055 if (IS_ERR(msm_host->ctrl_base)) { 2056 pr_err("%s: unable to map Dsi ctrl base\n", __func__); 2057 ret = PTR_ERR(msm_host->ctrl_base); 2058 goto fail; 2059 } 2060 2061 pm_runtime_enable(&pdev->dev); 2062 2063 msm_host->cfg_hnd = dsi_get_config(msm_host); 2064 if (!msm_host->cfg_hnd) { 2065 ret = -EINVAL; 2066 pr_err("%s: get config failed\n", __func__); 2067 goto fail; 2068 } 2069 2070 msm_host->id = dsi_host_get_id(msm_host); 2071 if (msm_host->id < 0) { 2072 ret = msm_host->id; 2073 pr_err("%s: unable to identify DSI host index\n", __func__); 2074 goto fail; 2075 } 2076 2077 /* fixup base address by io offset */ 2078 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset; 2079 2080 ret = dsi_regulator_init(msm_host); 2081 if (ret) { 2082 pr_err("%s: regulator init failed\n", __func__); 2083 goto fail; 2084 } 2085 2086 ret = dsi_clk_init(msm_host); 2087 if (ret) { 2088 pr_err("%s: unable to initialize dsi clks\n", __func__); 2089 goto fail; 2090 } 2091 2092 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 2093 if (!msm_host->rx_buf) { 2094 ret = -ENOMEM; 2095 pr_err("%s: alloc rx temp buf failed\n", __func__); 2096 goto fail; 2097 } 2098 2099 ret = devm_pm_opp_set_clkname(&pdev->dev, "byte"); 2100 if (ret) 2101 return ret; 2102 /* OPP table is optional */ 2103 ret = devm_pm_opp_of_add_table(&pdev->dev); 2104 if (ret && ret != -ENODEV) { 2105 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 2106 return ret; 2107 } 2108 2109 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 2110 if (msm_host->irq < 0) { 2111 ret = msm_host->irq; 2112 dev_err(&pdev->dev, "failed to get irq: %d\n", ret); 2113 return ret; 2114 } 2115 2116 /* do not autoenable, will be enabled later */ 2117 ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq, 2118 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, 2119 "dsi_isr", msm_host); 2120 if (ret < 0) { 2121 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n", 2122 msm_host->irq, ret); 2123 return ret; 2124 } 2125 2126 init_completion(&msm_host->dma_comp); 2127 init_completion(&msm_host->video_comp); 2128 mutex_init(&msm_host->dev_mutex); 2129 mutex_init(&msm_host->cmd_mutex); 2130 spin_lock_init(&msm_host->intr_lock); 2131 2132 /* setup workqueue */ 2133 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 2134 INIT_WORK(&msm_host->err_work, dsi_err_worker); 2135 INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker); 2136 2137 msm_dsi->id = msm_host->id; 2138 2139 DBG("Dsi Host %d initialized", msm_host->id); 2140 return 0; 2141 2142 fail: 2143 return ret; 2144 } 2145 2146 void msm_dsi_host_destroy(struct mipi_dsi_host *host) 2147 { 2148 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2149 2150 DBG(""); 2151 dsi_tx_buf_free(msm_host); 2152 if (msm_host->workqueue) { 2153 destroy_workqueue(msm_host->workqueue); 2154 msm_host->workqueue = NULL; 2155 } 2156 2157 mutex_destroy(&msm_host->cmd_mutex); 2158 mutex_destroy(&msm_host->dev_mutex); 2159 2160 pm_runtime_disable(&msm_host->pdev->dev); 2161 } 2162 2163 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 2164 struct drm_device *dev) 2165 { 2166 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2167 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2168 struct drm_panel *panel; 2169 int ret; 2170 2171 msm_host->dev = dev; 2172 panel = msm_dsi_host_get_panel(&msm_host->base); 2173 2174 if (!IS_ERR(panel) && panel->dsc) { 2175 struct msm_display_dsc_config *dsc = msm_host->dsc; 2176 2177 if (!dsc) { 2178 dsc = devm_kzalloc(&msm_host->pdev->dev, sizeof(*dsc), GFP_KERNEL); 2179 if (!dsc) 2180 return -ENOMEM; 2181 dsc->drm = panel->dsc; 2182 msm_host->dsc = dsc; 2183 } 2184 } 2185 2186 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); 2187 if (ret) { 2188 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 2189 return ret; 2190 } 2191 2192 return 0; 2193 } 2194 2195 int msm_dsi_host_register(struct mipi_dsi_host *host) 2196 { 2197 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2198 int ret; 2199 2200 /* Register mipi dsi host */ 2201 if (!msm_host->registered) { 2202 host->dev = &msm_host->pdev->dev; 2203 host->ops = &dsi_host_ops; 2204 ret = mipi_dsi_host_register(host); 2205 if (ret) 2206 return ret; 2207 2208 msm_host->registered = true; 2209 } 2210 2211 return 0; 2212 } 2213 2214 void msm_dsi_host_unregister(struct mipi_dsi_host *host) 2215 { 2216 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2217 2218 if (msm_host->registered) { 2219 mipi_dsi_host_unregister(host); 2220 host->dev = NULL; 2221 host->ops = NULL; 2222 msm_host->registered = false; 2223 } 2224 } 2225 2226 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 2227 const struct mipi_dsi_msg *msg) 2228 { 2229 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2230 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2231 2232 /* TODO: make sure dsi_cmd_mdp is idle. 2233 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 2234 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 2235 * How to handle the old versions? Wait for mdp cmd done? 2236 */ 2237 2238 /* 2239 * mdss interrupt is generated in mdp core clock domain 2240 * mdp clock need to be enabled to receive dsi interrupt 2241 */ 2242 pm_runtime_get_sync(&msm_host->pdev->dev); 2243 cfg_hnd->ops->link_clk_set_rate(msm_host); 2244 cfg_hnd->ops->link_clk_enable(msm_host); 2245 2246 /* TODO: vote for bus bandwidth */ 2247 2248 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2249 dsi_set_tx_power_mode(0, msm_host); 2250 2251 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 2252 dsi_write(msm_host, REG_DSI_CTRL, 2253 msm_host->dma_cmd_ctrl_restore | 2254 DSI_CTRL_CMD_MODE_EN | 2255 DSI_CTRL_ENABLE); 2256 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 2257 2258 return 0; 2259 } 2260 2261 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 2262 const struct mipi_dsi_msg *msg) 2263 { 2264 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2265 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2266 2267 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 2268 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 2269 2270 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2271 dsi_set_tx_power_mode(1, msm_host); 2272 2273 /* TODO: unvote for bus bandwidth */ 2274 2275 cfg_hnd->ops->link_clk_disable(msm_host); 2276 pm_runtime_put(&msm_host->pdev->dev); 2277 } 2278 2279 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 2280 const struct mipi_dsi_msg *msg) 2281 { 2282 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2283 2284 return dsi_cmds2buf_tx(msm_host, msg); 2285 } 2286 2287 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 2288 const struct mipi_dsi_msg *msg) 2289 { 2290 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2291 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2292 int data_byte, rx_byte, dlen, end; 2293 int short_response, diff, pkt_size, ret = 0; 2294 char cmd; 2295 int rlen = msg->rx_len; 2296 u8 *buf; 2297 2298 if (rlen <= 2) { 2299 short_response = 1; 2300 pkt_size = rlen; 2301 rx_byte = 4; 2302 } else { 2303 short_response = 0; 2304 data_byte = 10; /* first read */ 2305 if (rlen < data_byte) 2306 pkt_size = rlen; 2307 else 2308 pkt_size = data_byte; 2309 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 2310 } 2311 2312 buf = msm_host->rx_buf; 2313 end = 0; 2314 while (!end) { 2315 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 2316 struct mipi_dsi_msg max_pkt_size_msg = { 2317 .channel = msg->channel, 2318 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 2319 .tx_len = 2, 2320 .tx_buf = tx, 2321 }; 2322 2323 DBG("rlen=%d pkt_size=%d rx_byte=%d", 2324 rlen, pkt_size, rx_byte); 2325 2326 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 2327 if (ret < 2) { 2328 pr_err("%s: Set max pkt size failed, %d\n", 2329 __func__, ret); 2330 return -EINVAL; 2331 } 2332 2333 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 2334 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 2335 /* Clear the RDBK_DATA registers */ 2336 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 2337 DSI_RDBK_DATA_CTRL_CLR); 2338 wmb(); /* make sure the RDBK registers are cleared */ 2339 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 2340 wmb(); /* release cleared status before transfer */ 2341 } 2342 2343 ret = dsi_cmds2buf_tx(msm_host, msg); 2344 if (ret < 0) { 2345 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 2346 return ret; 2347 } else if (ret < msg->tx_len) { 2348 pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret); 2349 return -ECOMM; 2350 } 2351 2352 /* 2353 * once cmd_dma_done interrupt received, 2354 * return data from client is ready and stored 2355 * at RDBK_DATA register already 2356 * since rx fifo is 16 bytes, dcs header is kept at first loop, 2357 * after that dcs header lost during shift into registers 2358 */ 2359 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 2360 2361 if (dlen <= 0) 2362 return 0; 2363 2364 if (short_response) 2365 break; 2366 2367 if (rlen <= data_byte) { 2368 diff = data_byte - rlen; 2369 end = 1; 2370 } else { 2371 diff = 0; 2372 rlen -= data_byte; 2373 } 2374 2375 if (!end) { 2376 dlen -= 2; /* 2 crc */ 2377 dlen -= diff; 2378 buf += dlen; /* next start position */ 2379 data_byte = 14; /* NOT first read */ 2380 if (rlen < data_byte) 2381 pkt_size += rlen; 2382 else 2383 pkt_size += data_byte; 2384 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 2385 } 2386 } 2387 2388 /* 2389 * For single Long read, if the requested rlen < 10, 2390 * we need to shift the start position of rx 2391 * data buffer to skip the bytes which are not 2392 * updated. 2393 */ 2394 if (pkt_size < 10 && !short_response) 2395 buf = msm_host->rx_buf + (10 - rlen); 2396 else 2397 buf = msm_host->rx_buf; 2398 2399 cmd = buf[0]; 2400 switch (cmd) { 2401 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 2402 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 2403 ret = 0; 2404 break; 2405 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 2406 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 2407 ret = dsi_short_read1_resp(buf, msg); 2408 break; 2409 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 2410 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 2411 ret = dsi_short_read2_resp(buf, msg); 2412 break; 2413 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 2414 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 2415 ret = dsi_long_read_resp(buf, msg); 2416 break; 2417 default: 2418 pr_warn("%s:Invalid response cmd\n", __func__); 2419 ret = 0; 2420 } 2421 2422 return ret; 2423 } 2424 2425 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, 2426 u32 len) 2427 { 2428 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2429 2430 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); 2431 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 2432 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 2433 2434 /* Make sure trigger happens */ 2435 wmb(); 2436 } 2437 2438 void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host, 2439 struct msm_dsi_phy *src_phy) 2440 { 2441 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2442 2443 msm_host->cphy_mode = src_phy->cphy_mode; 2444 } 2445 2446 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) 2447 { 2448 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2449 2450 DBG(""); 2451 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 2452 /* Make sure fully reset */ 2453 wmb(); 2454 udelay(1000); 2455 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 2456 udelay(100); 2457 } 2458 2459 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, 2460 struct msm_dsi_phy_clk_request *clk_req, 2461 bool is_bonded_dsi) 2462 { 2463 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2464 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2465 int ret; 2466 2467 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi); 2468 if (ret) { 2469 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 2470 return; 2471 } 2472 2473 /* CPHY transmits 16 bits over 7 clock cycles 2474 * "byte_clk" is in units of 16-bits (see dsi_calc_pclk), 2475 * so multiply by 7 to get the "bitclk rate" 2476 */ 2477 if (msm_host->cphy_mode) 2478 clk_req->bitclk_rate = msm_host->byte_clk_rate * 7; 2479 else 2480 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; 2481 clk_req->escclk_rate = msm_host->esc_clk_rate; 2482 } 2483 2484 void msm_dsi_host_enable_irq(struct mipi_dsi_host *host) 2485 { 2486 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2487 2488 enable_irq(msm_host->irq); 2489 } 2490 2491 void msm_dsi_host_disable_irq(struct mipi_dsi_host *host) 2492 { 2493 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2494 2495 disable_irq(msm_host->irq); 2496 } 2497 2498 int msm_dsi_host_enable(struct mipi_dsi_host *host) 2499 { 2500 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2501 2502 dsi_op_mode_config(msm_host, 2503 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 2504 2505 /* TODO: clock should be turned off for command mode, 2506 * and only turned on before MDP START. 2507 * This part of code should be enabled once mdp driver support it. 2508 */ 2509 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { 2510 * dsi_link_clk_disable(msm_host); 2511 * pm_runtime_put(&msm_host->pdev->dev); 2512 * } 2513 */ 2514 msm_host->enabled = true; 2515 return 0; 2516 } 2517 2518 int msm_dsi_host_disable(struct mipi_dsi_host *host) 2519 { 2520 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2521 2522 msm_host->enabled = false; 2523 dsi_op_mode_config(msm_host, 2524 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 2525 2526 /* Since we have disabled INTF, the video engine won't stop so that 2527 * the cmd engine will be blocked. 2528 * Reset to disable video engine so that we can send off cmd. 2529 */ 2530 dsi_sw_reset(msm_host); 2531 2532 return 0; 2533 } 2534 2535 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) 2536 { 2537 enum sfpb_ahb_arb_master_port_en en; 2538 2539 if (!msm_host->sfpb) 2540 return; 2541 2542 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; 2543 2544 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, 2545 SFPB_GPREG_MASTER_PORT_EN__MASK, 2546 SFPB_GPREG_MASTER_PORT_EN(en)); 2547 } 2548 2549 int msm_dsi_host_power_on(struct mipi_dsi_host *host, 2550 struct msm_dsi_phy_shared_timings *phy_shared_timings, 2551 bool is_bonded_dsi, struct msm_dsi_phy *phy) 2552 { 2553 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2554 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2555 int ret = 0; 2556 2557 mutex_lock(&msm_host->dev_mutex); 2558 if (msm_host->power_on) { 2559 DBG("dsi host already on"); 2560 goto unlock_ret; 2561 } 2562 2563 msm_dsi_sfpb_config(msm_host, true); 2564 2565 ret = dsi_host_regulator_enable(msm_host); 2566 if (ret) { 2567 pr_err("%s:Failed to enable vregs.ret=%d\n", 2568 __func__, ret); 2569 goto unlock_ret; 2570 } 2571 2572 pm_runtime_get_sync(&msm_host->pdev->dev); 2573 ret = cfg_hnd->ops->link_clk_set_rate(msm_host); 2574 if (!ret) 2575 ret = cfg_hnd->ops->link_clk_enable(msm_host); 2576 if (ret) { 2577 pr_err("%s: failed to enable link clocks. ret=%d\n", 2578 __func__, ret); 2579 goto fail_disable_reg; 2580 } 2581 2582 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); 2583 if (ret) { 2584 pr_err("%s: failed to set pinctrl default state, %d\n", 2585 __func__, ret); 2586 goto fail_disable_clk; 2587 } 2588 2589 dsi_timing_setup(msm_host, is_bonded_dsi); 2590 dsi_sw_reset(msm_host); 2591 dsi_ctrl_config(msm_host, true, phy_shared_timings, phy); 2592 2593 if (msm_host->disp_en_gpio) 2594 gpiod_set_value(msm_host->disp_en_gpio, 1); 2595 2596 msm_host->power_on = true; 2597 mutex_unlock(&msm_host->dev_mutex); 2598 2599 return 0; 2600 2601 fail_disable_clk: 2602 cfg_hnd->ops->link_clk_disable(msm_host); 2603 pm_runtime_put(&msm_host->pdev->dev); 2604 fail_disable_reg: 2605 dsi_host_regulator_disable(msm_host); 2606 unlock_ret: 2607 mutex_unlock(&msm_host->dev_mutex); 2608 return ret; 2609 } 2610 2611 int msm_dsi_host_power_off(struct mipi_dsi_host *host) 2612 { 2613 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2614 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2615 2616 mutex_lock(&msm_host->dev_mutex); 2617 if (!msm_host->power_on) { 2618 DBG("dsi host already off"); 2619 goto unlock_ret; 2620 } 2621 2622 dsi_ctrl_config(msm_host, false, NULL, NULL); 2623 2624 if (msm_host->disp_en_gpio) 2625 gpiod_set_value(msm_host->disp_en_gpio, 0); 2626 2627 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); 2628 2629 cfg_hnd->ops->link_clk_disable(msm_host); 2630 pm_runtime_put(&msm_host->pdev->dev); 2631 2632 dsi_host_regulator_disable(msm_host); 2633 2634 msm_dsi_sfpb_config(msm_host, false); 2635 2636 DBG("-"); 2637 2638 msm_host->power_on = false; 2639 2640 unlock_ret: 2641 mutex_unlock(&msm_host->dev_mutex); 2642 return 0; 2643 } 2644 2645 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 2646 const struct drm_display_mode *mode) 2647 { 2648 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2649 2650 if (msm_host->mode) { 2651 drm_mode_destroy(msm_host->dev, msm_host->mode); 2652 msm_host->mode = NULL; 2653 } 2654 2655 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 2656 if (!msm_host->mode) { 2657 pr_err("%s: cannot duplicate mode\n", __func__); 2658 return -ENOMEM; 2659 } 2660 2661 return 0; 2662 } 2663 2664 enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, 2665 const struct drm_display_mode *mode) 2666 { 2667 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2668 struct msm_display_dsc_config *dsc = msm_host->dsc; 2669 int pic_width = mode->hdisplay; 2670 int pic_height = mode->vdisplay; 2671 2672 if (!msm_host->dsc) 2673 return MODE_OK; 2674 2675 if (pic_width % dsc->drm->slice_width) { 2676 pr_err("DSI: pic_width %d has to be multiple of slice %d\n", 2677 pic_width, dsc->drm->slice_width); 2678 return MODE_H_ILLEGAL; 2679 } 2680 2681 if (pic_height % dsc->drm->slice_height) { 2682 pr_err("DSI: pic_height %d has to be multiple of slice %d\n", 2683 pic_height, dsc->drm->slice_height); 2684 return MODE_V_ILLEGAL; 2685 } 2686 2687 return MODE_OK; 2688 } 2689 2690 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host) 2691 { 2692 return of_drm_find_panel(to_msm_dsi_host(host)->device_node); 2693 } 2694 2695 unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) 2696 { 2697 return to_msm_dsi_host(host)->mode_flags; 2698 } 2699 2700 struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host) 2701 { 2702 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2703 2704 return of_drm_find_bridge(msm_host->device_node); 2705 } 2706 2707 void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host) 2708 { 2709 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2710 2711 pm_runtime_get_sync(&msm_host->pdev->dev); 2712 2713 msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size, 2714 msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id); 2715 2716 pm_runtime_put_sync(&msm_host->pdev->dev); 2717 } 2718 2719 static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host) 2720 { 2721 u32 reg; 2722 2723 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2724 2725 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff); 2726 /* draw checkered rectangle pattern */ 2727 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL, 2728 DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN); 2729 /* use 24-bit RGB test pttern */ 2730 dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG, 2731 DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) | 2732 DSI_TPG_VIDEO_CONFIG_RGB); 2733 2734 reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN); 2735 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2736 2737 DBG("Video test pattern setup done\n"); 2738 } 2739 2740 static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) 2741 { 2742 u32 reg; 2743 2744 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2745 2746 /* initial value for test pattern */ 2747 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff); 2748 2749 reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN); 2750 2751 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2752 /* draw checkered rectangle pattern */ 2753 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, 2754 DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN); 2755 2756 DBG("Cmd test pattern setup done\n"); 2757 } 2758 2759 void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host) 2760 { 2761 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2762 bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO); 2763 u32 reg; 2764 2765 if (is_video_mode) 2766 msm_dsi_host_video_test_pattern_setup(msm_host); 2767 else 2768 msm_dsi_host_cmd_test_pattern_setup(msm_host); 2769 2770 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2771 /* enable the test pattern generator */ 2772 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN)); 2773 2774 /* for command mode need to trigger one frame from tpg */ 2775 if (!is_video_mode) 2776 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, 2777 DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER); 2778 } 2779 2780 struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host) 2781 { 2782 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2783 2784 return msm_host->dsc; 2785 } 2786