1 /* 2 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/gpio.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/interrupt.h> 20 #include <linux/of_device.h> 21 #include <linux/of_gpio.h> 22 #include <linux/of_irq.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/of_graph.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/spinlock.h> 27 #include <linux/mfd/syscon.h> 28 #include <linux/regmap.h> 29 #include <video/mipi_display.h> 30 31 #include "dsi.h" 32 #include "dsi.xml.h" 33 #include "sfpb.xml.h" 34 #include "dsi_cfg.h" 35 #include "msm_kms.h" 36 37 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 38 { 39 u32 ver; 40 41 if (!major || !minor) 42 return -EINVAL; 43 44 /* 45 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 46 * makes all other registers 4-byte shifted down. 47 * 48 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and 49 * older, we read the DSI_VERSION register without any shift(offset 50 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In 51 * the case of DSI6G, this has to be zero (the offset points to a 52 * scratch register which we never touch) 53 */ 54 55 ver = msm_readl(base + REG_DSI_VERSION); 56 if (ver) { 57 /* older dsi host, there is no register shift */ 58 ver = FIELD(ver, DSI_VERSION_MAJOR); 59 if (ver <= MSM_DSI_VER_MAJOR_V2) { 60 /* old versions */ 61 *major = ver; 62 *minor = 0; 63 return 0; 64 } else { 65 return -EINVAL; 66 } 67 } else { 68 /* 69 * newer host, offset 0 has 6G_HW_VERSION, the rest of the 70 * registers are shifted down, read DSI_VERSION again with 71 * the shifted offset 72 */ 73 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 74 ver = FIELD(ver, DSI_VERSION_MAJOR); 75 if (ver == MSM_DSI_VER_MAJOR_6G) { 76 /* 6G version */ 77 *major = ver; 78 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION); 79 return 0; 80 } else { 81 return -EINVAL; 82 } 83 } 84 } 85 86 #define DSI_ERR_STATE_ACK 0x0000 87 #define DSI_ERR_STATE_TIMEOUT 0x0001 88 #define DSI_ERR_STATE_DLN0_PHY 0x0002 89 #define DSI_ERR_STATE_FIFO 0x0004 90 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 91 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 92 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 93 94 #define DSI_CLK_CTRL_ENABLE_CLKS \ 95 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 96 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 97 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 98 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 99 100 struct msm_dsi_host { 101 struct mipi_dsi_host base; 102 103 struct platform_device *pdev; 104 struct drm_device *dev; 105 106 int id; 107 108 void __iomem *ctrl_base; 109 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; 110 111 struct clk *bus_clks[DSI_BUS_CLK_MAX]; 112 113 struct clk *byte_clk; 114 struct clk *esc_clk; 115 struct clk *pixel_clk; 116 struct clk *byte_clk_src; 117 struct clk *pixel_clk_src; 118 struct clk *byte_intf_clk; 119 120 u32 byte_clk_rate; 121 u32 pixel_clk_rate; 122 u32 esc_clk_rate; 123 124 /* DSI v2 specific clocks */ 125 struct clk *src_clk; 126 struct clk *esc_clk_src; 127 struct clk *dsi_clk_src; 128 129 u32 src_clk_rate; 130 131 struct gpio_desc *disp_en_gpio; 132 struct gpio_desc *te_gpio; 133 134 const struct msm_dsi_cfg_handler *cfg_hnd; 135 136 struct completion dma_comp; 137 struct completion video_comp; 138 struct mutex dev_mutex; 139 struct mutex cmd_mutex; 140 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 141 142 u32 err_work_state; 143 struct work_struct err_work; 144 struct work_struct hpd_work; 145 struct workqueue_struct *workqueue; 146 147 /* DSI 6G TX buffer*/ 148 struct drm_gem_object *tx_gem_obj; 149 150 /* DSI v2 TX buffer */ 151 void *tx_buf; 152 dma_addr_t tx_buf_paddr; 153 154 int tx_size; 155 156 u8 *rx_buf; 157 158 struct regmap *sfpb; 159 160 struct drm_display_mode *mode; 161 162 /* connected device info */ 163 struct device_node *device_node; 164 unsigned int channel; 165 unsigned int lanes; 166 enum mipi_dsi_pixel_format format; 167 unsigned long mode_flags; 168 169 /* lane data parsed via DT */ 170 int dlane_swap; 171 int num_data_lanes; 172 173 u32 dma_cmd_ctrl_restore; 174 175 bool registered; 176 bool power_on; 177 bool enabled; 178 int irq; 179 }; 180 181 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt) 182 { 183 switch (fmt) { 184 case MIPI_DSI_FMT_RGB565: return 16; 185 case MIPI_DSI_FMT_RGB666_PACKED: return 18; 186 case MIPI_DSI_FMT_RGB666: 187 case MIPI_DSI_FMT_RGB888: 188 default: return 24; 189 } 190 } 191 192 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 193 { 194 return msm_readl(msm_host->ctrl_base + reg); 195 } 196 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 197 { 198 msm_writel(data, msm_host->ctrl_base + reg); 199 } 200 201 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host); 202 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host); 203 204 static const struct msm_dsi_cfg_handler *dsi_get_config( 205 struct msm_dsi_host *msm_host) 206 { 207 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 208 struct device *dev = &msm_host->pdev->dev; 209 struct regulator *gdsc_reg; 210 struct clk *ahb_clk; 211 int ret; 212 u32 major = 0, minor = 0; 213 214 gdsc_reg = regulator_get(dev, "gdsc"); 215 if (IS_ERR(gdsc_reg)) { 216 pr_err("%s: cannot get gdsc\n", __func__); 217 goto exit; 218 } 219 220 ahb_clk = msm_clk_get(msm_host->pdev, "iface"); 221 if (IS_ERR(ahb_clk)) { 222 pr_err("%s: cannot get interface clock\n", __func__); 223 goto put_gdsc; 224 } 225 226 pm_runtime_get_sync(dev); 227 228 ret = regulator_enable(gdsc_reg); 229 if (ret) { 230 pr_err("%s: unable to enable gdsc\n", __func__); 231 goto put_gdsc; 232 } 233 234 ret = clk_prepare_enable(ahb_clk); 235 if (ret) { 236 pr_err("%s: unable to enable ahb_clk\n", __func__); 237 goto disable_gdsc; 238 } 239 240 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 241 if (ret) { 242 pr_err("%s: Invalid version\n", __func__); 243 goto disable_clks; 244 } 245 246 cfg_hnd = msm_dsi_cfg_get(major, minor); 247 248 DBG("%s: Version %x:%x\n", __func__, major, minor); 249 250 disable_clks: 251 clk_disable_unprepare(ahb_clk); 252 disable_gdsc: 253 regulator_disable(gdsc_reg); 254 pm_runtime_put_sync(dev); 255 put_gdsc: 256 regulator_put(gdsc_reg); 257 exit: 258 return cfg_hnd; 259 } 260 261 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 262 { 263 return container_of(host, struct msm_dsi_host, base); 264 } 265 266 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host) 267 { 268 struct regulator_bulk_data *s = msm_host->supplies; 269 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 270 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 271 int i; 272 273 DBG(""); 274 for (i = num - 1; i >= 0; i--) 275 if (regs[i].disable_load >= 0) 276 regulator_set_load(s[i].consumer, 277 regs[i].disable_load); 278 279 regulator_bulk_disable(num, s); 280 } 281 282 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host) 283 { 284 struct regulator_bulk_data *s = msm_host->supplies; 285 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 286 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 287 int ret, i; 288 289 DBG(""); 290 for (i = 0; i < num; i++) { 291 if (regs[i].enable_load >= 0) { 292 ret = regulator_set_load(s[i].consumer, 293 regs[i].enable_load); 294 if (ret < 0) { 295 pr_err("regulator %d set op mode failed, %d\n", 296 i, ret); 297 goto fail; 298 } 299 } 300 } 301 302 ret = regulator_bulk_enable(num, s); 303 if (ret < 0) { 304 pr_err("regulator enable failed, %d\n", ret); 305 goto fail; 306 } 307 308 return 0; 309 310 fail: 311 for (i--; i >= 0; i--) 312 regulator_set_load(s[i].consumer, regs[i].disable_load); 313 return ret; 314 } 315 316 static int dsi_regulator_init(struct msm_dsi_host *msm_host) 317 { 318 struct regulator_bulk_data *s = msm_host->supplies; 319 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 320 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 321 int i, ret; 322 323 for (i = 0; i < num; i++) 324 s[i].supply = regs[i].name; 325 326 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s); 327 if (ret < 0) { 328 pr_err("%s: failed to init regulator, ret=%d\n", 329 __func__, ret); 330 return ret; 331 } 332 333 return 0; 334 } 335 336 int dsi_clk_init_v2(struct msm_dsi_host *msm_host) 337 { 338 struct platform_device *pdev = msm_host->pdev; 339 int ret = 0; 340 341 msm_host->src_clk = msm_clk_get(pdev, "src"); 342 343 if (IS_ERR(msm_host->src_clk)) { 344 ret = PTR_ERR(msm_host->src_clk); 345 pr_err("%s: can't find src clock. ret=%d\n", 346 __func__, ret); 347 msm_host->src_clk = NULL; 348 return ret; 349 } 350 351 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk); 352 if (!msm_host->esc_clk_src) { 353 ret = -ENODEV; 354 pr_err("%s: can't get esc clock parent. ret=%d\n", 355 __func__, ret); 356 return ret; 357 } 358 359 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk); 360 if (!msm_host->dsi_clk_src) { 361 ret = -ENODEV; 362 pr_err("%s: can't get src clock parent. ret=%d\n", 363 __func__, ret); 364 } 365 366 return ret; 367 } 368 369 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) 370 { 371 struct platform_device *pdev = msm_host->pdev; 372 int ret = 0; 373 374 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); 375 if (IS_ERR(msm_host->byte_intf_clk)) { 376 ret = PTR_ERR(msm_host->byte_intf_clk); 377 pr_err("%s: can't find byte_intf clock. ret=%d\n", 378 __func__, ret); 379 } 380 381 return ret; 382 } 383 384 static int dsi_clk_init(struct msm_dsi_host *msm_host) 385 { 386 struct platform_device *pdev = msm_host->pdev; 387 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 388 const struct msm_dsi_config *cfg = cfg_hnd->cfg; 389 int i, ret = 0; 390 391 /* get bus clocks */ 392 for (i = 0; i < cfg->num_bus_clks; i++) { 393 msm_host->bus_clks[i] = msm_clk_get(pdev, 394 cfg->bus_clk_names[i]); 395 if (IS_ERR(msm_host->bus_clks[i])) { 396 ret = PTR_ERR(msm_host->bus_clks[i]); 397 pr_err("%s: Unable to get %s clock, ret = %d\n", 398 __func__, cfg->bus_clk_names[i], ret); 399 goto exit; 400 } 401 } 402 403 /* get link and source clocks */ 404 msm_host->byte_clk = msm_clk_get(pdev, "byte"); 405 if (IS_ERR(msm_host->byte_clk)) { 406 ret = PTR_ERR(msm_host->byte_clk); 407 pr_err("%s: can't find dsi_byte clock. ret=%d\n", 408 __func__, ret); 409 msm_host->byte_clk = NULL; 410 goto exit; 411 } 412 413 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); 414 if (IS_ERR(msm_host->pixel_clk)) { 415 ret = PTR_ERR(msm_host->pixel_clk); 416 pr_err("%s: can't find dsi_pixel clock. ret=%d\n", 417 __func__, ret); 418 msm_host->pixel_clk = NULL; 419 goto exit; 420 } 421 422 msm_host->esc_clk = msm_clk_get(pdev, "core"); 423 if (IS_ERR(msm_host->esc_clk)) { 424 ret = PTR_ERR(msm_host->esc_clk); 425 pr_err("%s: can't find dsi_esc clock. ret=%d\n", 426 __func__, ret); 427 msm_host->esc_clk = NULL; 428 goto exit; 429 } 430 431 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk); 432 if (!msm_host->byte_clk_src) { 433 ret = -ENODEV; 434 pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret); 435 goto exit; 436 } 437 438 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk); 439 if (!msm_host->pixel_clk_src) { 440 ret = -ENODEV; 441 pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret); 442 goto exit; 443 } 444 445 if (cfg_hnd->ops->clk_init_ver) 446 ret = cfg_hnd->ops->clk_init_ver(msm_host); 447 exit: 448 return ret; 449 } 450 451 static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host) 452 { 453 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 454 int i, ret; 455 456 DBG("id=%d", msm_host->id); 457 458 for (i = 0; i < cfg->num_bus_clks; i++) { 459 ret = clk_prepare_enable(msm_host->bus_clks[i]); 460 if (ret) { 461 pr_err("%s: failed to enable bus clock %d ret %d\n", 462 __func__, i, ret); 463 goto err; 464 } 465 } 466 467 return 0; 468 err: 469 for (; i > 0; i--) 470 clk_disable_unprepare(msm_host->bus_clks[i]); 471 472 return ret; 473 } 474 475 static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host) 476 { 477 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 478 int i; 479 480 DBG(""); 481 482 for (i = cfg->num_bus_clks - 1; i >= 0; i--) 483 clk_disable_unprepare(msm_host->bus_clks[i]); 484 } 485 486 int msm_dsi_runtime_suspend(struct device *dev) 487 { 488 struct platform_device *pdev = to_platform_device(dev); 489 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 490 struct mipi_dsi_host *host = msm_dsi->host; 491 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 492 493 if (!msm_host->cfg_hnd) 494 return 0; 495 496 dsi_bus_clk_disable(msm_host); 497 498 return 0; 499 } 500 501 int msm_dsi_runtime_resume(struct device *dev) 502 { 503 struct platform_device *pdev = to_platform_device(dev); 504 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 505 struct mipi_dsi_host *host = msm_dsi->host; 506 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 507 508 if (!msm_host->cfg_hnd) 509 return 0; 510 511 return dsi_bus_clk_enable(msm_host); 512 } 513 514 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) 515 { 516 int ret; 517 518 DBG("Set clk rates: pclk=%d, byteclk=%d", 519 msm_host->mode->clock, msm_host->byte_clk_rate); 520 521 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 522 if (ret) { 523 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 524 goto error; 525 } 526 527 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 528 if (ret) { 529 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 530 goto error; 531 } 532 533 if (msm_host->byte_intf_clk) { 534 ret = clk_set_rate(msm_host->byte_intf_clk, 535 msm_host->byte_clk_rate / 2); 536 if (ret) { 537 pr_err("%s: Failed to set rate byte intf clk, %d\n", 538 __func__, ret); 539 goto error; 540 } 541 } 542 543 ret = clk_prepare_enable(msm_host->esc_clk); 544 if (ret) { 545 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 546 goto error; 547 } 548 549 ret = clk_prepare_enable(msm_host->byte_clk); 550 if (ret) { 551 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 552 goto byte_clk_err; 553 } 554 555 ret = clk_prepare_enable(msm_host->pixel_clk); 556 if (ret) { 557 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 558 goto pixel_clk_err; 559 } 560 561 if (msm_host->byte_intf_clk) { 562 ret = clk_prepare_enable(msm_host->byte_intf_clk); 563 if (ret) { 564 pr_err("%s: Failed to enable byte intf clk\n", 565 __func__); 566 goto byte_intf_clk_err; 567 } 568 } 569 570 return 0; 571 572 byte_intf_clk_err: 573 clk_disable_unprepare(msm_host->pixel_clk); 574 pixel_clk_err: 575 clk_disable_unprepare(msm_host->byte_clk); 576 byte_clk_err: 577 clk_disable_unprepare(msm_host->esc_clk); 578 error: 579 return ret; 580 } 581 582 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) 583 { 584 int ret; 585 586 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d", 587 msm_host->mode->clock, msm_host->byte_clk_rate, 588 msm_host->esc_clk_rate, msm_host->src_clk_rate); 589 590 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 591 if (ret) { 592 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 593 goto error; 594 } 595 596 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); 597 if (ret) { 598 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); 599 goto error; 600 } 601 602 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); 603 if (ret) { 604 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); 605 goto error; 606 } 607 608 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 609 if (ret) { 610 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 611 goto error; 612 } 613 614 ret = clk_prepare_enable(msm_host->byte_clk); 615 if (ret) { 616 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 617 goto error; 618 } 619 620 ret = clk_prepare_enable(msm_host->esc_clk); 621 if (ret) { 622 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 623 goto esc_clk_err; 624 } 625 626 ret = clk_prepare_enable(msm_host->src_clk); 627 if (ret) { 628 pr_err("%s: Failed to enable dsi src clk\n", __func__); 629 goto src_clk_err; 630 } 631 632 ret = clk_prepare_enable(msm_host->pixel_clk); 633 if (ret) { 634 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 635 goto pixel_clk_err; 636 } 637 638 return 0; 639 640 pixel_clk_err: 641 clk_disable_unprepare(msm_host->src_clk); 642 src_clk_err: 643 clk_disable_unprepare(msm_host->esc_clk); 644 esc_clk_err: 645 clk_disable_unprepare(msm_host->byte_clk); 646 error: 647 return ret; 648 } 649 650 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) 651 { 652 clk_disable_unprepare(msm_host->esc_clk); 653 clk_disable_unprepare(msm_host->pixel_clk); 654 if (msm_host->byte_intf_clk) 655 clk_disable_unprepare(msm_host->byte_intf_clk); 656 clk_disable_unprepare(msm_host->byte_clk); 657 } 658 659 void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) 660 { 661 clk_disable_unprepare(msm_host->pixel_clk); 662 clk_disable_unprepare(msm_host->src_clk); 663 clk_disable_unprepare(msm_host->esc_clk); 664 clk_disable_unprepare(msm_host->byte_clk); 665 } 666 667 static u32 dsi_get_pclk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi) 668 { 669 struct drm_display_mode *mode = msm_host->mode; 670 u32 pclk_rate; 671 672 pclk_rate = mode->clock * 1000; 673 674 /* 675 * For dual DSI mode, the current DRM mode has the complete width of the 676 * panel. Since, the complete panel is driven by two DSI controllers, 677 * the clock rates have to be split between the two dsi controllers. 678 * Adjust the byte and pixel clock rates for each dsi host accordingly. 679 */ 680 if (is_dual_dsi) 681 pclk_rate /= 2; 682 683 return pclk_rate; 684 } 685 686 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_dual_dsi) 687 { 688 u8 lanes = msm_host->lanes; 689 u32 bpp = dsi_get_bpp(msm_host->format); 690 u32 pclk_rate = dsi_get_pclk_rate(msm_host, is_dual_dsi); 691 u64 pclk_bpp = (u64)pclk_rate * bpp; 692 693 if (lanes == 0) { 694 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 695 lanes = 1; 696 } 697 698 do_div(pclk_bpp, (8 * lanes)); 699 700 msm_host->pixel_clk_rate = pclk_rate; 701 msm_host->byte_clk_rate = pclk_bpp; 702 703 DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate, 704 msm_host->byte_clk_rate); 705 706 } 707 708 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi) 709 { 710 if (!msm_host->mode) { 711 pr_err("%s: mode not set\n", __func__); 712 return -EINVAL; 713 } 714 715 dsi_calc_pclk(msm_host, is_dual_dsi); 716 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); 717 return 0; 718 } 719 720 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi) 721 { 722 u32 bpp = dsi_get_bpp(msm_host->format); 723 u64 pclk_bpp; 724 unsigned int esc_mhz, esc_div; 725 unsigned long byte_mhz; 726 727 dsi_calc_pclk(msm_host, is_dual_dsi); 728 729 pclk_bpp = (u64)dsi_get_pclk_rate(msm_host, is_dual_dsi) * bpp; 730 do_div(pclk_bpp, 8); 731 msm_host->src_clk_rate = pclk_bpp; 732 733 /* 734 * esc clock is byte clock followed by a 4 bit divider, 735 * we need to find an escape clock frequency within the 736 * mipi DSI spec range within the maximum divider limit 737 * We iterate here between an escape clock frequencey 738 * between 20 Mhz to 5 Mhz and pick up the first one 739 * that can be supported by our divider 740 */ 741 742 byte_mhz = msm_host->byte_clk_rate / 1000000; 743 744 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { 745 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); 746 747 /* 748 * TODO: Ideally, we shouldn't know what sort of divider 749 * is available in mmss_cc, we're just assuming that 750 * it'll always be a 4 bit divider. Need to come up with 751 * a better way here. 752 */ 753 if (esc_div >= 1 && esc_div <= 16) 754 break; 755 } 756 757 if (esc_mhz < 5) 758 return -EINVAL; 759 760 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; 761 762 DBG("esc=%d, src=%d", msm_host->esc_clk_rate, 763 msm_host->src_clk_rate); 764 765 return 0; 766 } 767 768 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 769 { 770 u32 intr; 771 unsigned long flags; 772 773 spin_lock_irqsave(&msm_host->intr_lock, flags); 774 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 775 776 if (enable) 777 intr |= mask; 778 else 779 intr &= ~mask; 780 781 DBG("intr=%x enable=%d", intr, enable); 782 783 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 784 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 785 } 786 787 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 788 { 789 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 790 return BURST_MODE; 791 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 792 return NON_BURST_SYNCH_PULSE; 793 794 return NON_BURST_SYNCH_EVENT; 795 } 796 797 static inline enum dsi_vid_dst_format dsi_get_vid_fmt( 798 const enum mipi_dsi_pixel_format mipi_fmt) 799 { 800 switch (mipi_fmt) { 801 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 802 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 803 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 804 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 805 default: return VID_DST_FORMAT_RGB888; 806 } 807 } 808 809 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( 810 const enum mipi_dsi_pixel_format mipi_fmt) 811 { 812 switch (mipi_fmt) { 813 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 814 case MIPI_DSI_FMT_RGB666_PACKED: 815 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; 816 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 817 default: return CMD_DST_FORMAT_RGB888; 818 } 819 } 820 821 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, 822 struct msm_dsi_phy_shared_timings *phy_shared_timings) 823 { 824 u32 flags = msm_host->mode_flags; 825 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 826 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 827 u32 data = 0; 828 829 if (!enable) { 830 dsi_write(msm_host, REG_DSI_CTRL, 0); 831 return; 832 } 833 834 if (flags & MIPI_DSI_MODE_VIDEO) { 835 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 836 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 837 if (flags & MIPI_DSI_MODE_VIDEO_HFP) 838 data |= DSI_VID_CFG0_HFP_POWER_STOP; 839 if (flags & MIPI_DSI_MODE_VIDEO_HBP) 840 data |= DSI_VID_CFG0_HBP_POWER_STOP; 841 if (flags & MIPI_DSI_MODE_VIDEO_HSA) 842 data |= DSI_VID_CFG0_HSA_POWER_STOP; 843 /* Always set low power stop mode for BLLP 844 * to let command engine send packets 845 */ 846 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 847 DSI_VID_CFG0_BLLP_POWER_STOP; 848 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 849 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 850 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 851 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 852 853 /* Do not swap RGB colors */ 854 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 855 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 856 } else { 857 /* Do not swap RGB colors */ 858 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 859 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 860 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 861 862 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 863 DSI_CMD_CFG1_WR_MEM_CONTINUE( 864 MIPI_DCS_WRITE_MEMORY_CONTINUE); 865 /* Always insert DCS command */ 866 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 867 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 868 } 869 870 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 871 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 872 DSI_CMD_DMA_CTRL_LOW_POWER); 873 874 data = 0; 875 /* Always assume dedicated TE pin */ 876 data |= DSI_TRIG_CTRL_TE; 877 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 878 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 879 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 880 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 881 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 882 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 883 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 884 885 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | 886 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); 887 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 888 889 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 890 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && 891 phy_shared_timings->clk_pre_inc_by_2) 892 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND, 893 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); 894 895 data = 0; 896 if (!(flags & MIPI_DSI_MODE_EOT_PACKET)) 897 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 898 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 899 900 /* allow only ack-err-status to generate interrupt */ 901 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 902 903 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 904 905 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 906 907 data = DSI_CTRL_CLK_EN; 908 909 DBG("lane number=%d", msm_host->lanes); 910 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); 911 912 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 913 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); 914 915 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 916 dsi_write(msm_host, REG_DSI_LANE_CTRL, 917 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); 918 919 data |= DSI_CTRL_ENABLE; 920 921 dsi_write(msm_host, REG_DSI_CTRL, data); 922 } 923 924 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi) 925 { 926 struct drm_display_mode *mode = msm_host->mode; 927 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 928 u32 h_total = mode->htotal; 929 u32 v_total = mode->vtotal; 930 u32 hs_end = mode->hsync_end - mode->hsync_start; 931 u32 vs_end = mode->vsync_end - mode->vsync_start; 932 u32 ha_start = h_total - mode->hsync_start; 933 u32 ha_end = ha_start + mode->hdisplay; 934 u32 va_start = v_total - mode->vsync_start; 935 u32 va_end = va_start + mode->vdisplay; 936 u32 hdisplay = mode->hdisplay; 937 u32 wc; 938 939 DBG(""); 940 941 /* 942 * For dual DSI mode, the current DRM mode has 943 * the complete width of the panel. Since, the complete 944 * panel is driven by two DSI controllers, the horizontal 945 * timings have to be split between the two dsi controllers. 946 * Adjust the DSI host timing values accordingly. 947 */ 948 if (is_dual_dsi) { 949 h_total /= 2; 950 hs_end /= 2; 951 ha_start /= 2; 952 ha_end /= 2; 953 hdisplay /= 2; 954 } 955 956 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 957 dsi_write(msm_host, REG_DSI_ACTIVE_H, 958 DSI_ACTIVE_H_START(ha_start) | 959 DSI_ACTIVE_H_END(ha_end)); 960 dsi_write(msm_host, REG_DSI_ACTIVE_V, 961 DSI_ACTIVE_V_START(va_start) | 962 DSI_ACTIVE_V_END(va_end)); 963 dsi_write(msm_host, REG_DSI_TOTAL, 964 DSI_TOTAL_H_TOTAL(h_total - 1) | 965 DSI_TOTAL_V_TOTAL(v_total - 1)); 966 967 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 968 DSI_ACTIVE_HSYNC_START(hs_start) | 969 DSI_ACTIVE_HSYNC_END(hs_end)); 970 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 971 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 972 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 973 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 974 } else { /* command mode */ 975 /* image data and 1 byte write_memory_start cmd */ 976 wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; 977 978 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL, 979 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) | 980 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL( 981 msm_host->channel) | 982 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE( 983 MIPI_DSI_DCS_LONG_WRITE)); 984 985 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL, 986 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(hdisplay) | 987 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay)); 988 } 989 } 990 991 static void dsi_sw_reset(struct msm_dsi_host *msm_host) 992 { 993 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 994 wmb(); /* clocks need to be enabled before reset */ 995 996 dsi_write(msm_host, REG_DSI_RESET, 1); 997 wmb(); /* make sure reset happen */ 998 dsi_write(msm_host, REG_DSI_RESET, 0); 999 } 1000 1001 static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 1002 bool video_mode, bool enable) 1003 { 1004 u32 dsi_ctrl; 1005 1006 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1007 1008 if (!enable) { 1009 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 1010 DSI_CTRL_CMD_MODE_EN); 1011 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 1012 DSI_IRQ_MASK_VIDEO_DONE, 0); 1013 } else { 1014 if (video_mode) { 1015 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 1016 } else { /* command mode */ 1017 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 1018 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 1019 } 1020 dsi_ctrl |= DSI_CTRL_ENABLE; 1021 } 1022 1023 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 1024 } 1025 1026 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 1027 { 1028 u32 data; 1029 1030 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 1031 1032 if (mode == 0) 1033 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 1034 else 1035 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 1036 1037 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 1038 } 1039 1040 static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 1041 { 1042 u32 ret = 0; 1043 struct device *dev = &msm_host->pdev->dev; 1044 1045 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 1046 1047 reinit_completion(&msm_host->video_comp); 1048 1049 ret = wait_for_completion_timeout(&msm_host->video_comp, 1050 msecs_to_jiffies(70)); 1051 1052 if (ret <= 0) 1053 dev_err(dev, "wait for video done timed out\n"); 1054 1055 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 1056 } 1057 1058 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 1059 { 1060 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 1061 return; 1062 1063 if (msm_host->power_on && msm_host->enabled) { 1064 dsi_wait4video_done(msm_host); 1065 /* delay 4 ms to skip BLLP */ 1066 usleep_range(2000, 4000); 1067 } 1068 } 1069 1070 int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) 1071 { 1072 struct drm_device *dev = msm_host->dev; 1073 struct msm_drm_private *priv = dev->dev_private; 1074 uint64_t iova; 1075 u8 *data; 1076 1077 data = msm_gem_kernel_new(dev, size, MSM_BO_UNCACHED, 1078 priv->kms->aspace, 1079 &msm_host->tx_gem_obj, &iova); 1080 1081 if (IS_ERR(data)) { 1082 msm_host->tx_gem_obj = NULL; 1083 return PTR_ERR(data); 1084 } 1085 1086 msm_host->tx_size = msm_host->tx_gem_obj->size; 1087 1088 return 0; 1089 } 1090 1091 int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) 1092 { 1093 struct drm_device *dev = msm_host->dev; 1094 1095 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, 1096 &msm_host->tx_buf_paddr, GFP_KERNEL); 1097 if (!msm_host->tx_buf) 1098 return -ENOMEM; 1099 1100 msm_host->tx_size = size; 1101 1102 return 0; 1103 } 1104 1105 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host) 1106 { 1107 struct drm_device *dev = msm_host->dev; 1108 struct msm_drm_private *priv; 1109 1110 /* 1111 * This is possible if we're tearing down before we've had a chance to 1112 * fully initialize. A very real possibility if our probe is deferred, 1113 * in which case we'll hit msm_dsi_host_destroy() without having run 1114 * through the dsi_tx_buf_alloc(). 1115 */ 1116 if (!dev) 1117 return; 1118 1119 priv = dev->dev_private; 1120 if (msm_host->tx_gem_obj) { 1121 msm_gem_put_iova(msm_host->tx_gem_obj, priv->kms->aspace); 1122 drm_gem_object_put_unlocked(msm_host->tx_gem_obj); 1123 msm_host->tx_gem_obj = NULL; 1124 } 1125 1126 if (msm_host->tx_buf) 1127 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, 1128 msm_host->tx_buf_paddr); 1129 } 1130 1131 void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host) 1132 { 1133 return msm_gem_get_vaddr(msm_host->tx_gem_obj); 1134 } 1135 1136 void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host) 1137 { 1138 return msm_host->tx_buf; 1139 } 1140 1141 void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host) 1142 { 1143 msm_gem_put_vaddr(msm_host->tx_gem_obj); 1144 } 1145 1146 /* 1147 * prepare cmd buffer to be txed 1148 */ 1149 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, 1150 const struct mipi_dsi_msg *msg) 1151 { 1152 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1153 struct mipi_dsi_packet packet; 1154 int len; 1155 int ret; 1156 u8 *data; 1157 1158 ret = mipi_dsi_create_packet(&packet, msg); 1159 if (ret) { 1160 pr_err("%s: create packet failed, %d\n", __func__, ret); 1161 return ret; 1162 } 1163 len = (packet.size + 3) & (~0x3); 1164 1165 if (len > msm_host->tx_size) { 1166 pr_err("%s: packet size is too big\n", __func__); 1167 return -EINVAL; 1168 } 1169 1170 data = cfg_hnd->ops->tx_buf_get(msm_host); 1171 if (IS_ERR(data)) { 1172 ret = PTR_ERR(data); 1173 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 1174 return ret; 1175 } 1176 1177 /* MSM specific command format in memory */ 1178 data[0] = packet.header[1]; 1179 data[1] = packet.header[2]; 1180 data[2] = packet.header[0]; 1181 data[3] = BIT(7); /* Last packet */ 1182 if (mipi_dsi_packet_format_is_long(msg->type)) 1183 data[3] |= BIT(6); 1184 if (msg->rx_buf && msg->rx_len) 1185 data[3] |= BIT(5); 1186 1187 /* Long packet */ 1188 if (packet.payload && packet.payload_length) 1189 memcpy(data + 4, packet.payload, packet.payload_length); 1190 1191 /* Append 0xff to the end */ 1192 if (packet.size < len) 1193 memset(data + packet.size, 0xff, len - packet.size); 1194 1195 if (cfg_hnd->ops->tx_buf_put) 1196 cfg_hnd->ops->tx_buf_put(msm_host); 1197 1198 return len; 1199 } 1200 1201 /* 1202 * dsi_short_read1_resp: 1 parameter 1203 */ 1204 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1205 { 1206 u8 *data = msg->rx_buf; 1207 if (data && (msg->rx_len >= 1)) { 1208 *data = buf[1]; /* strip out dcs type */ 1209 return 1; 1210 } else { 1211 pr_err("%s: read data does not match with rx_buf len %zu\n", 1212 __func__, msg->rx_len); 1213 return -EINVAL; 1214 } 1215 } 1216 1217 /* 1218 * dsi_short_read2_resp: 2 parameter 1219 */ 1220 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1221 { 1222 u8 *data = msg->rx_buf; 1223 if (data && (msg->rx_len >= 2)) { 1224 data[0] = buf[1]; /* strip out dcs type */ 1225 data[1] = buf[2]; 1226 return 2; 1227 } else { 1228 pr_err("%s: read data does not match with rx_buf len %zu\n", 1229 __func__, msg->rx_len); 1230 return -EINVAL; 1231 } 1232 } 1233 1234 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1235 { 1236 /* strip out 4 byte dcs header */ 1237 if (msg->rx_buf && msg->rx_len) 1238 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 1239 1240 return msg->rx_len; 1241 } 1242 1243 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1244 { 1245 struct drm_device *dev = msm_host->dev; 1246 struct msm_drm_private *priv = dev->dev_private; 1247 1248 if (!dma_base) 1249 return -EINVAL; 1250 1251 return msm_gem_get_iova(msm_host->tx_gem_obj, 1252 priv->kms->aspace, dma_base); 1253 } 1254 1255 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1256 { 1257 if (!dma_base) 1258 return -EINVAL; 1259 1260 *dma_base = msm_host->tx_buf_paddr; 1261 return 0; 1262 } 1263 1264 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 1265 { 1266 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1267 int ret; 1268 uint64_t dma_base; 1269 bool triggered; 1270 1271 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); 1272 if (ret) { 1273 pr_err("%s: failed to get iova: %d\n", __func__, ret); 1274 return ret; 1275 } 1276 1277 reinit_completion(&msm_host->dma_comp); 1278 1279 dsi_wait4video_eng_busy(msm_host); 1280 1281 triggered = msm_dsi_manager_cmd_xfer_trigger( 1282 msm_host->id, dma_base, len); 1283 if (triggered) { 1284 ret = wait_for_completion_timeout(&msm_host->dma_comp, 1285 msecs_to_jiffies(200)); 1286 DBG("ret=%d", ret); 1287 if (ret == 0) 1288 ret = -ETIMEDOUT; 1289 else 1290 ret = len; 1291 } else 1292 ret = len; 1293 1294 return ret; 1295 } 1296 1297 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1298 u8 *buf, int rx_byte, int pkt_size) 1299 { 1300 u32 *lp, *temp, data; 1301 int i, j = 0, cnt; 1302 u32 read_cnt; 1303 u8 reg[16]; 1304 int repeated_bytes = 0; 1305 int buf_offset = buf - msm_host->rx_buf; 1306 1307 lp = (u32 *)buf; 1308 temp = (u32 *)reg; 1309 cnt = (rx_byte + 3) >> 2; 1310 if (cnt > 4) 1311 cnt = 4; /* 4 x 32 bits registers only */ 1312 1313 if (rx_byte == 4) 1314 read_cnt = 4; 1315 else 1316 read_cnt = pkt_size + 6; 1317 1318 /* 1319 * In case of multiple reads from the panel, after the first read, there 1320 * is possibility that there are some bytes in the payload repeating in 1321 * the RDBK_DATA registers. Since we read all the parameters from the 1322 * panel right from the first byte for every pass. We need to skip the 1323 * repeating bytes and then append the new parameters to the rx buffer. 1324 */ 1325 if (read_cnt > 16) { 1326 int bytes_shifted; 1327 /* Any data more than 16 bytes will be shifted out. 1328 * The temp read buffer should already contain these bytes. 1329 * The remaining bytes in read buffer are the repeated bytes. 1330 */ 1331 bytes_shifted = read_cnt - 16; 1332 repeated_bytes = buf_offset - bytes_shifted; 1333 } 1334 1335 for (i = cnt - 1; i >= 0; i--) { 1336 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1337 *temp++ = ntohl(data); /* to host byte order */ 1338 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1339 } 1340 1341 for (i = repeated_bytes; i < 16; i++) 1342 buf[j++] = reg[i]; 1343 1344 return j; 1345 } 1346 1347 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1348 const struct mipi_dsi_msg *msg) 1349 { 1350 int len, ret; 1351 int bllp_len = msm_host->mode->hdisplay * 1352 dsi_get_bpp(msm_host->format) / 8; 1353 1354 len = dsi_cmd_dma_add(msm_host, msg); 1355 if (!len) { 1356 pr_err("%s: failed to add cmd type = 0x%x\n", 1357 __func__, msg->type); 1358 return -EINVAL; 1359 } 1360 1361 /* for video mode, do not send cmds more than 1362 * one pixel line, since it only transmit it 1363 * during BLLP. 1364 */ 1365 /* TODO: if the command is sent in LP mode, the bit rate is only 1366 * half of esc clk rate. In this case, if the video is already 1367 * actively streaming, we need to check more carefully if the 1368 * command can be fit into one BLLP. 1369 */ 1370 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1371 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1372 __func__, len); 1373 return -EINVAL; 1374 } 1375 1376 ret = dsi_cmd_dma_tx(msm_host, len); 1377 if (ret < len) { 1378 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n", 1379 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len); 1380 return -ECOMM; 1381 } 1382 1383 return len; 1384 } 1385 1386 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host) 1387 { 1388 u32 data0, data1; 1389 1390 data0 = dsi_read(msm_host, REG_DSI_CTRL); 1391 data1 = data0; 1392 data1 &= ~DSI_CTRL_ENABLE; 1393 dsi_write(msm_host, REG_DSI_CTRL, data1); 1394 /* 1395 * dsi controller need to be disabled before 1396 * clocks turned on 1397 */ 1398 wmb(); 1399 1400 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1401 wmb(); /* make sure clocks enabled */ 1402 1403 /* dsi controller can only be reset while clocks are running */ 1404 dsi_write(msm_host, REG_DSI_RESET, 1); 1405 wmb(); /* make sure reset happen */ 1406 dsi_write(msm_host, REG_DSI_RESET, 0); 1407 wmb(); /* controller out of reset */ 1408 dsi_write(msm_host, REG_DSI_CTRL, data0); 1409 wmb(); /* make sure dsi controller enabled again */ 1410 } 1411 1412 static void dsi_hpd_worker(struct work_struct *work) 1413 { 1414 struct msm_dsi_host *msm_host = 1415 container_of(work, struct msm_dsi_host, hpd_work); 1416 1417 drm_helper_hpd_irq_event(msm_host->dev); 1418 } 1419 1420 static void dsi_err_worker(struct work_struct *work) 1421 { 1422 struct msm_dsi_host *msm_host = 1423 container_of(work, struct msm_dsi_host, err_work); 1424 u32 status = msm_host->err_work_state; 1425 1426 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1427 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1428 dsi_sw_reset_restore(msm_host); 1429 1430 /* It is safe to clear here because error irq is disabled. */ 1431 msm_host->err_work_state = 0; 1432 1433 /* enable dsi error interrupt */ 1434 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1435 } 1436 1437 static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1438 { 1439 u32 status; 1440 1441 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1442 1443 if (status) { 1444 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1445 /* Writing of an extra 0 needed to clear error bits */ 1446 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1447 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1448 } 1449 } 1450 1451 static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1452 { 1453 u32 status; 1454 1455 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1456 1457 if (status) { 1458 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1459 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1460 } 1461 } 1462 1463 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1464 { 1465 u32 status; 1466 1467 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1468 1469 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | 1470 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | 1471 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | 1472 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | 1473 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { 1474 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1475 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1476 } 1477 } 1478 1479 static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1480 { 1481 u32 status; 1482 1483 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1484 1485 /* fifo underflow, overflow */ 1486 if (status) { 1487 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1488 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1489 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1490 msm_host->err_work_state |= 1491 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1492 } 1493 } 1494 1495 static void dsi_status(struct msm_dsi_host *msm_host) 1496 { 1497 u32 status; 1498 1499 status = dsi_read(msm_host, REG_DSI_STATUS0); 1500 1501 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1502 dsi_write(msm_host, REG_DSI_STATUS0, status); 1503 msm_host->err_work_state |= 1504 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1505 } 1506 } 1507 1508 static void dsi_clk_status(struct msm_dsi_host *msm_host) 1509 { 1510 u32 status; 1511 1512 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1513 1514 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1515 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1516 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1517 } 1518 } 1519 1520 static void dsi_error(struct msm_dsi_host *msm_host) 1521 { 1522 /* disable dsi error interrupt */ 1523 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1524 1525 dsi_clk_status(msm_host); 1526 dsi_fifo_status(msm_host); 1527 dsi_ack_err_status(msm_host); 1528 dsi_timeout_status(msm_host); 1529 dsi_status(msm_host); 1530 dsi_dln0_phy_err(msm_host); 1531 1532 queue_work(msm_host->workqueue, &msm_host->err_work); 1533 } 1534 1535 static irqreturn_t dsi_host_irq(int irq, void *ptr) 1536 { 1537 struct msm_dsi_host *msm_host = ptr; 1538 u32 isr; 1539 unsigned long flags; 1540 1541 if (!msm_host->ctrl_base) 1542 return IRQ_HANDLED; 1543 1544 spin_lock_irqsave(&msm_host->intr_lock, flags); 1545 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1546 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1547 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1548 1549 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1550 1551 if (isr & DSI_IRQ_ERROR) 1552 dsi_error(msm_host); 1553 1554 if (isr & DSI_IRQ_VIDEO_DONE) 1555 complete(&msm_host->video_comp); 1556 1557 if (isr & DSI_IRQ_CMD_DMA_DONE) 1558 complete(&msm_host->dma_comp); 1559 1560 return IRQ_HANDLED; 1561 } 1562 1563 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, 1564 struct device *panel_device) 1565 { 1566 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device, 1567 "disp-enable", 1568 GPIOD_OUT_LOW); 1569 if (IS_ERR(msm_host->disp_en_gpio)) { 1570 DBG("cannot get disp-enable-gpios %ld", 1571 PTR_ERR(msm_host->disp_en_gpio)); 1572 return PTR_ERR(msm_host->disp_en_gpio); 1573 } 1574 1575 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te", 1576 GPIOD_IN); 1577 if (IS_ERR(msm_host->te_gpio)) { 1578 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); 1579 return PTR_ERR(msm_host->te_gpio); 1580 } 1581 1582 return 0; 1583 } 1584 1585 static int dsi_host_attach(struct mipi_dsi_host *host, 1586 struct mipi_dsi_device *dsi) 1587 { 1588 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1589 int ret; 1590 1591 if (dsi->lanes > msm_host->num_data_lanes) 1592 return -EINVAL; 1593 1594 msm_host->channel = dsi->channel; 1595 msm_host->lanes = dsi->lanes; 1596 msm_host->format = dsi->format; 1597 msm_host->mode_flags = dsi->mode_flags; 1598 1599 msm_dsi_manager_attach_dsi_device(msm_host->id, dsi->mode_flags); 1600 1601 /* Some gpios defined in panel DT need to be controlled by host */ 1602 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); 1603 if (ret) 1604 return ret; 1605 1606 DBG("id=%d", msm_host->id); 1607 if (msm_host->dev) 1608 queue_work(msm_host->workqueue, &msm_host->hpd_work); 1609 1610 return 0; 1611 } 1612 1613 static int dsi_host_detach(struct mipi_dsi_host *host, 1614 struct mipi_dsi_device *dsi) 1615 { 1616 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1617 1618 msm_host->device_node = NULL; 1619 1620 DBG("id=%d", msm_host->id); 1621 if (msm_host->dev) 1622 queue_work(msm_host->workqueue, &msm_host->hpd_work); 1623 1624 return 0; 1625 } 1626 1627 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1628 const struct mipi_dsi_msg *msg) 1629 { 1630 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1631 int ret; 1632 1633 if (!msg || !msm_host->power_on) 1634 return -EINVAL; 1635 1636 mutex_lock(&msm_host->cmd_mutex); 1637 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1638 mutex_unlock(&msm_host->cmd_mutex); 1639 1640 return ret; 1641 } 1642 1643 static struct mipi_dsi_host_ops dsi_host_ops = { 1644 .attach = dsi_host_attach, 1645 .detach = dsi_host_detach, 1646 .transfer = dsi_host_transfer, 1647 }; 1648 1649 /* 1650 * List of supported physical to logical lane mappings. 1651 * For example, the 2nd entry represents the following mapping: 1652 * 1653 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; 1654 */ 1655 static const int supported_data_lane_swaps[][4] = { 1656 { 0, 1, 2, 3 }, 1657 { 3, 0, 1, 2 }, 1658 { 2, 3, 0, 1 }, 1659 { 1, 2, 3, 0 }, 1660 { 0, 3, 2, 1 }, 1661 { 1, 0, 3, 2 }, 1662 { 2, 1, 0, 3 }, 1663 { 3, 2, 1, 0 }, 1664 }; 1665 1666 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, 1667 struct device_node *ep) 1668 { 1669 struct device *dev = &msm_host->pdev->dev; 1670 struct property *prop; 1671 u32 lane_map[4]; 1672 int ret, i, len, num_lanes; 1673 1674 prop = of_find_property(ep, "data-lanes", &len); 1675 if (!prop) { 1676 dev_dbg(dev, 1677 "failed to find data lane mapping, using default\n"); 1678 return 0; 1679 } 1680 1681 num_lanes = len / sizeof(u32); 1682 1683 if (num_lanes < 1 || num_lanes > 4) { 1684 dev_err(dev, "bad number of data lanes\n"); 1685 return -EINVAL; 1686 } 1687 1688 msm_host->num_data_lanes = num_lanes; 1689 1690 ret = of_property_read_u32_array(ep, "data-lanes", lane_map, 1691 num_lanes); 1692 if (ret) { 1693 dev_err(dev, "failed to read lane data\n"); 1694 return ret; 1695 } 1696 1697 /* 1698 * compare DT specified physical-logical lane mappings with the ones 1699 * supported by hardware 1700 */ 1701 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { 1702 const int *swap = supported_data_lane_swaps[i]; 1703 int j; 1704 1705 /* 1706 * the data-lanes array we get from DT has a logical->physical 1707 * mapping. The "data lane swap" register field represents 1708 * supported configurations in a physical->logical mapping. 1709 * Translate the DT mapping to what we understand and find a 1710 * configuration that works. 1711 */ 1712 for (j = 0; j < num_lanes; j++) { 1713 if (lane_map[j] < 0 || lane_map[j] > 3) 1714 dev_err(dev, "bad physical lane entry %u\n", 1715 lane_map[j]); 1716 1717 if (swap[lane_map[j]] != j) 1718 break; 1719 } 1720 1721 if (j == num_lanes) { 1722 msm_host->dlane_swap = i; 1723 return 0; 1724 } 1725 } 1726 1727 return -EINVAL; 1728 } 1729 1730 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) 1731 { 1732 struct device *dev = &msm_host->pdev->dev; 1733 struct device_node *np = dev->of_node; 1734 struct device_node *endpoint, *device_node; 1735 int ret = 0; 1736 1737 /* 1738 * Get the endpoint of the output port of the DSI host. In our case, 1739 * this is mapped to port number with reg = 1. Don't return an error if 1740 * the remote endpoint isn't defined. It's possible that there is 1741 * nothing connected to the dsi output. 1742 */ 1743 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1744 if (!endpoint) { 1745 dev_dbg(dev, "%s: no endpoint\n", __func__); 1746 return 0; 1747 } 1748 1749 ret = dsi_host_parse_lane_data(msm_host, endpoint); 1750 if (ret) { 1751 dev_err(dev, "%s: invalid lane configuration %d\n", 1752 __func__, ret); 1753 goto err; 1754 } 1755 1756 /* Get panel node from the output port's endpoint data */ 1757 device_node = of_graph_get_remote_node(np, 1, 0); 1758 if (!device_node) { 1759 dev_dbg(dev, "%s: no valid device\n", __func__); 1760 goto err; 1761 } 1762 1763 msm_host->device_node = device_node; 1764 1765 if (of_property_read_bool(np, "syscon-sfpb")) { 1766 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, 1767 "syscon-sfpb"); 1768 if (IS_ERR(msm_host->sfpb)) { 1769 dev_err(dev, "%s: failed to get sfpb regmap\n", 1770 __func__); 1771 ret = PTR_ERR(msm_host->sfpb); 1772 } 1773 } 1774 1775 of_node_put(device_node); 1776 1777 err: 1778 of_node_put(endpoint); 1779 1780 return ret; 1781 } 1782 1783 static int dsi_host_get_id(struct msm_dsi_host *msm_host) 1784 { 1785 struct platform_device *pdev = msm_host->pdev; 1786 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 1787 struct resource *res; 1788 int i; 1789 1790 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); 1791 if (!res) 1792 return -EINVAL; 1793 1794 for (i = 0; i < cfg->num_dsi; i++) { 1795 if (cfg->io_start[i] == res->start) 1796 return i; 1797 } 1798 1799 return -EINVAL; 1800 } 1801 1802 int msm_dsi_host_init(struct msm_dsi *msm_dsi) 1803 { 1804 struct msm_dsi_host *msm_host = NULL; 1805 struct platform_device *pdev = msm_dsi->pdev; 1806 int ret; 1807 1808 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 1809 if (!msm_host) { 1810 pr_err("%s: FAILED: cannot alloc dsi host\n", 1811 __func__); 1812 ret = -ENOMEM; 1813 goto fail; 1814 } 1815 1816 msm_host->pdev = pdev; 1817 msm_dsi->host = &msm_host->base; 1818 1819 ret = dsi_host_parse_dt(msm_host); 1820 if (ret) { 1821 pr_err("%s: failed to parse dt\n", __func__); 1822 goto fail; 1823 } 1824 1825 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL"); 1826 if (IS_ERR(msm_host->ctrl_base)) { 1827 pr_err("%s: unable to map Dsi ctrl base\n", __func__); 1828 ret = PTR_ERR(msm_host->ctrl_base); 1829 goto fail; 1830 } 1831 1832 pm_runtime_enable(&pdev->dev); 1833 1834 msm_host->cfg_hnd = dsi_get_config(msm_host); 1835 if (!msm_host->cfg_hnd) { 1836 ret = -EINVAL; 1837 pr_err("%s: get config failed\n", __func__); 1838 goto fail; 1839 } 1840 1841 msm_host->id = dsi_host_get_id(msm_host); 1842 if (msm_host->id < 0) { 1843 ret = msm_host->id; 1844 pr_err("%s: unable to identify DSI host index\n", __func__); 1845 goto fail; 1846 } 1847 1848 /* fixup base address by io offset */ 1849 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset; 1850 1851 ret = dsi_regulator_init(msm_host); 1852 if (ret) { 1853 pr_err("%s: regulator init failed\n", __func__); 1854 goto fail; 1855 } 1856 1857 ret = dsi_clk_init(msm_host); 1858 if (ret) { 1859 pr_err("%s: unable to initialize dsi clks\n", __func__); 1860 goto fail; 1861 } 1862 1863 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 1864 if (!msm_host->rx_buf) { 1865 ret = -ENOMEM; 1866 pr_err("%s: alloc rx temp buf failed\n", __func__); 1867 goto fail; 1868 } 1869 1870 init_completion(&msm_host->dma_comp); 1871 init_completion(&msm_host->video_comp); 1872 mutex_init(&msm_host->dev_mutex); 1873 mutex_init(&msm_host->cmd_mutex); 1874 spin_lock_init(&msm_host->intr_lock); 1875 1876 /* setup workqueue */ 1877 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 1878 INIT_WORK(&msm_host->err_work, dsi_err_worker); 1879 INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker); 1880 1881 msm_dsi->id = msm_host->id; 1882 1883 DBG("Dsi Host %d initialized", msm_host->id); 1884 return 0; 1885 1886 fail: 1887 return ret; 1888 } 1889 1890 void msm_dsi_host_destroy(struct mipi_dsi_host *host) 1891 { 1892 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1893 1894 DBG(""); 1895 dsi_tx_buf_free(msm_host); 1896 if (msm_host->workqueue) { 1897 flush_workqueue(msm_host->workqueue); 1898 destroy_workqueue(msm_host->workqueue); 1899 msm_host->workqueue = NULL; 1900 } 1901 1902 mutex_destroy(&msm_host->cmd_mutex); 1903 mutex_destroy(&msm_host->dev_mutex); 1904 1905 pm_runtime_disable(&msm_host->pdev->dev); 1906 } 1907 1908 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 1909 struct drm_device *dev) 1910 { 1911 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1912 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1913 struct platform_device *pdev = msm_host->pdev; 1914 int ret; 1915 1916 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1917 if (msm_host->irq < 0) { 1918 ret = msm_host->irq; 1919 dev_err(dev->dev, "failed to get irq: %d\n", ret); 1920 return ret; 1921 } 1922 1923 ret = devm_request_irq(&pdev->dev, msm_host->irq, 1924 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1925 "dsi_isr", msm_host); 1926 if (ret < 0) { 1927 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n", 1928 msm_host->irq, ret); 1929 return ret; 1930 } 1931 1932 msm_host->dev = dev; 1933 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); 1934 if (ret) { 1935 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 1936 return ret; 1937 } 1938 1939 return 0; 1940 } 1941 1942 int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer) 1943 { 1944 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1945 int ret; 1946 1947 /* Register mipi dsi host */ 1948 if (!msm_host->registered) { 1949 host->dev = &msm_host->pdev->dev; 1950 host->ops = &dsi_host_ops; 1951 ret = mipi_dsi_host_register(host); 1952 if (ret) 1953 return ret; 1954 1955 msm_host->registered = true; 1956 1957 /* If the panel driver has not been probed after host register, 1958 * we should defer the host's probe. 1959 * It makes sure panel is connected when fbcon detects 1960 * connector status and gets the proper display mode to 1961 * create framebuffer. 1962 * Don't try to defer if there is nothing connected to the dsi 1963 * output 1964 */ 1965 if (check_defer && msm_host->device_node) { 1966 if (IS_ERR(of_drm_find_panel(msm_host->device_node))) 1967 if (!of_drm_find_bridge(msm_host->device_node)) 1968 return -EPROBE_DEFER; 1969 } 1970 } 1971 1972 return 0; 1973 } 1974 1975 void msm_dsi_host_unregister(struct mipi_dsi_host *host) 1976 { 1977 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1978 1979 if (msm_host->registered) { 1980 mipi_dsi_host_unregister(host); 1981 host->dev = NULL; 1982 host->ops = NULL; 1983 msm_host->registered = false; 1984 } 1985 } 1986 1987 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 1988 const struct mipi_dsi_msg *msg) 1989 { 1990 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1991 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1992 1993 /* TODO: make sure dsi_cmd_mdp is idle. 1994 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 1995 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 1996 * How to handle the old versions? Wait for mdp cmd done? 1997 */ 1998 1999 /* 2000 * mdss interrupt is generated in mdp core clock domain 2001 * mdp clock need to be enabled to receive dsi interrupt 2002 */ 2003 pm_runtime_get_sync(&msm_host->pdev->dev); 2004 cfg_hnd->ops->link_clk_enable(msm_host); 2005 2006 /* TODO: vote for bus bandwidth */ 2007 2008 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2009 dsi_set_tx_power_mode(0, msm_host); 2010 2011 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 2012 dsi_write(msm_host, REG_DSI_CTRL, 2013 msm_host->dma_cmd_ctrl_restore | 2014 DSI_CTRL_CMD_MODE_EN | 2015 DSI_CTRL_ENABLE); 2016 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 2017 2018 return 0; 2019 } 2020 2021 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 2022 const struct mipi_dsi_msg *msg) 2023 { 2024 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2025 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2026 2027 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 2028 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 2029 2030 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2031 dsi_set_tx_power_mode(1, msm_host); 2032 2033 /* TODO: unvote for bus bandwidth */ 2034 2035 cfg_hnd->ops->link_clk_disable(msm_host); 2036 pm_runtime_put_autosuspend(&msm_host->pdev->dev); 2037 } 2038 2039 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 2040 const struct mipi_dsi_msg *msg) 2041 { 2042 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2043 2044 return dsi_cmds2buf_tx(msm_host, msg); 2045 } 2046 2047 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 2048 const struct mipi_dsi_msg *msg) 2049 { 2050 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2051 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2052 int data_byte, rx_byte, dlen, end; 2053 int short_response, diff, pkt_size, ret = 0; 2054 char cmd; 2055 int rlen = msg->rx_len; 2056 u8 *buf; 2057 2058 if (rlen <= 2) { 2059 short_response = 1; 2060 pkt_size = rlen; 2061 rx_byte = 4; 2062 } else { 2063 short_response = 0; 2064 data_byte = 10; /* first read */ 2065 if (rlen < data_byte) 2066 pkt_size = rlen; 2067 else 2068 pkt_size = data_byte; 2069 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 2070 } 2071 2072 buf = msm_host->rx_buf; 2073 end = 0; 2074 while (!end) { 2075 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 2076 struct mipi_dsi_msg max_pkt_size_msg = { 2077 .channel = msg->channel, 2078 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 2079 .tx_len = 2, 2080 .tx_buf = tx, 2081 }; 2082 2083 DBG("rlen=%d pkt_size=%d rx_byte=%d", 2084 rlen, pkt_size, rx_byte); 2085 2086 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 2087 if (ret < 2) { 2088 pr_err("%s: Set max pkt size failed, %d\n", 2089 __func__, ret); 2090 return -EINVAL; 2091 } 2092 2093 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 2094 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 2095 /* Clear the RDBK_DATA registers */ 2096 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 2097 DSI_RDBK_DATA_CTRL_CLR); 2098 wmb(); /* make sure the RDBK registers are cleared */ 2099 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 2100 wmb(); /* release cleared status before transfer */ 2101 } 2102 2103 ret = dsi_cmds2buf_tx(msm_host, msg); 2104 if (ret < msg->tx_len) { 2105 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 2106 return ret; 2107 } 2108 2109 /* 2110 * once cmd_dma_done interrupt received, 2111 * return data from client is ready and stored 2112 * at RDBK_DATA register already 2113 * since rx fifo is 16 bytes, dcs header is kept at first loop, 2114 * after that dcs header lost during shift into registers 2115 */ 2116 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 2117 2118 if (dlen <= 0) 2119 return 0; 2120 2121 if (short_response) 2122 break; 2123 2124 if (rlen <= data_byte) { 2125 diff = data_byte - rlen; 2126 end = 1; 2127 } else { 2128 diff = 0; 2129 rlen -= data_byte; 2130 } 2131 2132 if (!end) { 2133 dlen -= 2; /* 2 crc */ 2134 dlen -= diff; 2135 buf += dlen; /* next start position */ 2136 data_byte = 14; /* NOT first read */ 2137 if (rlen < data_byte) 2138 pkt_size += rlen; 2139 else 2140 pkt_size += data_byte; 2141 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 2142 } 2143 } 2144 2145 /* 2146 * For single Long read, if the requested rlen < 10, 2147 * we need to shift the start position of rx 2148 * data buffer to skip the bytes which are not 2149 * updated. 2150 */ 2151 if (pkt_size < 10 && !short_response) 2152 buf = msm_host->rx_buf + (10 - rlen); 2153 else 2154 buf = msm_host->rx_buf; 2155 2156 cmd = buf[0]; 2157 switch (cmd) { 2158 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 2159 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 2160 ret = 0; 2161 break; 2162 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 2163 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 2164 ret = dsi_short_read1_resp(buf, msg); 2165 break; 2166 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 2167 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 2168 ret = dsi_short_read2_resp(buf, msg); 2169 break; 2170 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 2171 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 2172 ret = dsi_long_read_resp(buf, msg); 2173 break; 2174 default: 2175 pr_warn("%s:Invalid response cmd\n", __func__); 2176 ret = 0; 2177 } 2178 2179 return ret; 2180 } 2181 2182 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, 2183 u32 len) 2184 { 2185 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2186 2187 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); 2188 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 2189 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 2190 2191 /* Make sure trigger happens */ 2192 wmb(); 2193 } 2194 2195 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, 2196 struct msm_dsi_pll *src_pll) 2197 { 2198 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2199 struct clk *byte_clk_provider, *pixel_clk_provider; 2200 int ret; 2201 2202 ret = msm_dsi_pll_get_clk_provider(src_pll, 2203 &byte_clk_provider, &pixel_clk_provider); 2204 if (ret) { 2205 pr_info("%s: can't get provider from pll, don't set parent\n", 2206 __func__); 2207 return 0; 2208 } 2209 2210 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider); 2211 if (ret) { 2212 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n", 2213 __func__, ret); 2214 goto exit; 2215 } 2216 2217 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider); 2218 if (ret) { 2219 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n", 2220 __func__, ret); 2221 goto exit; 2222 } 2223 2224 if (msm_host->dsi_clk_src) { 2225 ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider); 2226 if (ret) { 2227 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n", 2228 __func__, ret); 2229 goto exit; 2230 } 2231 } 2232 2233 if (msm_host->esc_clk_src) { 2234 ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider); 2235 if (ret) { 2236 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n", 2237 __func__, ret); 2238 goto exit; 2239 } 2240 } 2241 2242 exit: 2243 return ret; 2244 } 2245 2246 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) 2247 { 2248 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2249 2250 DBG(""); 2251 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 2252 /* Make sure fully reset */ 2253 wmb(); 2254 udelay(1000); 2255 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 2256 udelay(100); 2257 } 2258 2259 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, 2260 struct msm_dsi_phy_clk_request *clk_req, 2261 bool is_dual_dsi) 2262 { 2263 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2264 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2265 int ret; 2266 2267 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_dual_dsi); 2268 if (ret) { 2269 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 2270 return; 2271 } 2272 2273 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; 2274 clk_req->escclk_rate = msm_host->esc_clk_rate; 2275 } 2276 2277 int msm_dsi_host_enable(struct mipi_dsi_host *host) 2278 { 2279 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2280 2281 dsi_op_mode_config(msm_host, 2282 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 2283 2284 /* TODO: clock should be turned off for command mode, 2285 * and only turned on before MDP START. 2286 * This part of code should be enabled once mdp driver support it. 2287 */ 2288 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { 2289 * dsi_link_clk_disable(msm_host); 2290 * pm_runtime_put_autosuspend(&msm_host->pdev->dev); 2291 * } 2292 */ 2293 msm_host->enabled = true; 2294 return 0; 2295 } 2296 2297 int msm_dsi_host_disable(struct mipi_dsi_host *host) 2298 { 2299 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2300 2301 msm_host->enabled = false; 2302 dsi_op_mode_config(msm_host, 2303 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 2304 2305 /* Since we have disabled INTF, the video engine won't stop so that 2306 * the cmd engine will be blocked. 2307 * Reset to disable video engine so that we can send off cmd. 2308 */ 2309 dsi_sw_reset(msm_host); 2310 2311 return 0; 2312 } 2313 2314 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) 2315 { 2316 enum sfpb_ahb_arb_master_port_en en; 2317 2318 if (!msm_host->sfpb) 2319 return; 2320 2321 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; 2322 2323 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, 2324 SFPB_GPREG_MASTER_PORT_EN__MASK, 2325 SFPB_GPREG_MASTER_PORT_EN(en)); 2326 } 2327 2328 int msm_dsi_host_power_on(struct mipi_dsi_host *host, 2329 struct msm_dsi_phy_shared_timings *phy_shared_timings, 2330 bool is_dual_dsi) 2331 { 2332 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2333 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2334 int ret = 0; 2335 2336 mutex_lock(&msm_host->dev_mutex); 2337 if (msm_host->power_on) { 2338 DBG("dsi host already on"); 2339 goto unlock_ret; 2340 } 2341 2342 msm_dsi_sfpb_config(msm_host, true); 2343 2344 ret = dsi_host_regulator_enable(msm_host); 2345 if (ret) { 2346 pr_err("%s:Failed to enable vregs.ret=%d\n", 2347 __func__, ret); 2348 goto unlock_ret; 2349 } 2350 2351 pm_runtime_get_sync(&msm_host->pdev->dev); 2352 ret = cfg_hnd->ops->link_clk_enable(msm_host); 2353 if (ret) { 2354 pr_err("%s: failed to enable link clocks. ret=%d\n", 2355 __func__, ret); 2356 goto fail_disable_reg; 2357 } 2358 2359 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); 2360 if (ret) { 2361 pr_err("%s: failed to set pinctrl default state, %d\n", 2362 __func__, ret); 2363 goto fail_disable_clk; 2364 } 2365 2366 dsi_timing_setup(msm_host, is_dual_dsi); 2367 dsi_sw_reset(msm_host); 2368 dsi_ctrl_config(msm_host, true, phy_shared_timings); 2369 2370 if (msm_host->disp_en_gpio) 2371 gpiod_set_value(msm_host->disp_en_gpio, 1); 2372 2373 msm_host->power_on = true; 2374 mutex_unlock(&msm_host->dev_mutex); 2375 2376 return 0; 2377 2378 fail_disable_clk: 2379 cfg_hnd->ops->link_clk_disable(msm_host); 2380 pm_runtime_put_autosuspend(&msm_host->pdev->dev); 2381 fail_disable_reg: 2382 dsi_host_regulator_disable(msm_host); 2383 unlock_ret: 2384 mutex_unlock(&msm_host->dev_mutex); 2385 return ret; 2386 } 2387 2388 int msm_dsi_host_power_off(struct mipi_dsi_host *host) 2389 { 2390 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2391 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2392 2393 mutex_lock(&msm_host->dev_mutex); 2394 if (!msm_host->power_on) { 2395 DBG("dsi host already off"); 2396 goto unlock_ret; 2397 } 2398 2399 dsi_ctrl_config(msm_host, false, NULL); 2400 2401 if (msm_host->disp_en_gpio) 2402 gpiod_set_value(msm_host->disp_en_gpio, 0); 2403 2404 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); 2405 2406 cfg_hnd->ops->link_clk_disable(msm_host); 2407 pm_runtime_put_autosuspend(&msm_host->pdev->dev); 2408 2409 dsi_host_regulator_disable(msm_host); 2410 2411 msm_dsi_sfpb_config(msm_host, false); 2412 2413 DBG("-"); 2414 2415 msm_host->power_on = false; 2416 2417 unlock_ret: 2418 mutex_unlock(&msm_host->dev_mutex); 2419 return 0; 2420 } 2421 2422 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 2423 struct drm_display_mode *mode) 2424 { 2425 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2426 2427 if (msm_host->mode) { 2428 drm_mode_destroy(msm_host->dev, msm_host->mode); 2429 msm_host->mode = NULL; 2430 } 2431 2432 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 2433 if (!msm_host->mode) { 2434 pr_err("%s: cannot duplicate mode\n", __func__); 2435 return -ENOMEM; 2436 } 2437 2438 return 0; 2439 } 2440 2441 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host, 2442 unsigned long *panel_flags) 2443 { 2444 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2445 struct drm_panel *panel; 2446 2447 panel = of_drm_find_panel(msm_host->device_node); 2448 if (panel_flags) 2449 *panel_flags = msm_host->mode_flags; 2450 2451 return panel; 2452 } 2453 2454 struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host) 2455 { 2456 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2457 2458 return of_drm_find_bridge(msm_host->device_node); 2459 } 2460