1 /* 2 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/gpio.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/interrupt.h> 20 #include <linux/of_device.h> 21 #include <linux/of_gpio.h> 22 #include <linux/of_irq.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/of_graph.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/spinlock.h> 27 #include <linux/mfd/syscon.h> 28 #include <linux/regmap.h> 29 #include <video/mipi_display.h> 30 31 #include "dsi.h" 32 #include "dsi.xml.h" 33 #include "sfpb.xml.h" 34 #include "dsi_cfg.h" 35 36 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 37 { 38 u32 ver; 39 40 if (!major || !minor) 41 return -EINVAL; 42 43 /* 44 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 45 * makes all other registers 4-byte shifted down. 46 * 47 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and 48 * older, we read the DSI_VERSION register without any shift(offset 49 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In 50 * the case of DSI6G, this has to be zero (the offset points to a 51 * scratch register which we never touch) 52 */ 53 54 ver = msm_readl(base + REG_DSI_VERSION); 55 if (ver) { 56 /* older dsi host, there is no register shift */ 57 ver = FIELD(ver, DSI_VERSION_MAJOR); 58 if (ver <= MSM_DSI_VER_MAJOR_V2) { 59 /* old versions */ 60 *major = ver; 61 *minor = 0; 62 return 0; 63 } else { 64 return -EINVAL; 65 } 66 } else { 67 /* 68 * newer host, offset 0 has 6G_HW_VERSION, the rest of the 69 * registers are shifted down, read DSI_VERSION again with 70 * the shifted offset 71 */ 72 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 73 ver = FIELD(ver, DSI_VERSION_MAJOR); 74 if (ver == MSM_DSI_VER_MAJOR_6G) { 75 /* 6G version */ 76 *major = ver; 77 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION); 78 return 0; 79 } else { 80 return -EINVAL; 81 } 82 } 83 } 84 85 #define DSI_ERR_STATE_ACK 0x0000 86 #define DSI_ERR_STATE_TIMEOUT 0x0001 87 #define DSI_ERR_STATE_DLN0_PHY 0x0002 88 #define DSI_ERR_STATE_FIFO 0x0004 89 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 90 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 91 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 92 93 #define DSI_CLK_CTRL_ENABLE_CLKS \ 94 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 95 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 96 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 97 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 98 99 struct msm_dsi_host { 100 struct mipi_dsi_host base; 101 102 struct platform_device *pdev; 103 struct drm_device *dev; 104 105 int id; 106 107 void __iomem *ctrl_base; 108 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; 109 110 struct clk *bus_clks[DSI_BUS_CLK_MAX]; 111 112 struct clk *byte_clk; 113 struct clk *esc_clk; 114 struct clk *pixel_clk; 115 struct clk *byte_clk_src; 116 struct clk *pixel_clk_src; 117 118 u32 byte_clk_rate; 119 u32 esc_clk_rate; 120 121 /* DSI v2 specific clocks */ 122 struct clk *src_clk; 123 struct clk *esc_clk_src; 124 struct clk *dsi_clk_src; 125 126 u32 src_clk_rate; 127 128 struct gpio_desc *disp_en_gpio; 129 struct gpio_desc *te_gpio; 130 131 const struct msm_dsi_cfg_handler *cfg_hnd; 132 133 struct completion dma_comp; 134 struct completion video_comp; 135 struct mutex dev_mutex; 136 struct mutex cmd_mutex; 137 struct mutex clk_mutex; 138 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 139 140 u32 err_work_state; 141 struct work_struct err_work; 142 struct workqueue_struct *workqueue; 143 144 /* DSI 6G TX buffer*/ 145 struct drm_gem_object *tx_gem_obj; 146 147 /* DSI v2 TX buffer */ 148 void *tx_buf; 149 dma_addr_t tx_buf_paddr; 150 151 int tx_size; 152 153 u8 *rx_buf; 154 155 struct regmap *sfpb; 156 157 struct drm_display_mode *mode; 158 159 /* connected device info */ 160 struct device_node *device_node; 161 unsigned int channel; 162 unsigned int lanes; 163 enum mipi_dsi_pixel_format format; 164 unsigned long mode_flags; 165 166 u32 dma_cmd_ctrl_restore; 167 168 bool registered; 169 bool power_on; 170 int irq; 171 }; 172 173 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt) 174 { 175 switch (fmt) { 176 case MIPI_DSI_FMT_RGB565: return 16; 177 case MIPI_DSI_FMT_RGB666_PACKED: return 18; 178 case MIPI_DSI_FMT_RGB666: 179 case MIPI_DSI_FMT_RGB888: 180 default: return 24; 181 } 182 } 183 184 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 185 { 186 return msm_readl(msm_host->ctrl_base + reg); 187 } 188 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 189 { 190 msm_writel(data, msm_host->ctrl_base + reg); 191 } 192 193 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host); 194 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host); 195 196 static const struct msm_dsi_cfg_handler *dsi_get_config( 197 struct msm_dsi_host *msm_host) 198 { 199 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 200 struct device *dev = &msm_host->pdev->dev; 201 struct regulator *gdsc_reg; 202 struct clk *ahb_clk; 203 int ret; 204 u32 major = 0, minor = 0; 205 206 gdsc_reg = regulator_get(dev, "gdsc"); 207 if (IS_ERR(gdsc_reg)) { 208 pr_err("%s: cannot get gdsc\n", __func__); 209 goto exit; 210 } 211 212 ahb_clk = clk_get(dev, "iface_clk"); 213 if (IS_ERR(ahb_clk)) { 214 pr_err("%s: cannot get interface clock\n", __func__); 215 goto put_gdsc; 216 } 217 218 ret = regulator_enable(gdsc_reg); 219 if (ret) { 220 pr_err("%s: unable to enable gdsc\n", __func__); 221 goto put_clk; 222 } 223 224 ret = clk_prepare_enable(ahb_clk); 225 if (ret) { 226 pr_err("%s: unable to enable ahb_clk\n", __func__); 227 goto disable_gdsc; 228 } 229 230 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 231 if (ret) { 232 pr_err("%s: Invalid version\n", __func__); 233 goto disable_clks; 234 } 235 236 cfg_hnd = msm_dsi_cfg_get(major, minor); 237 238 DBG("%s: Version %x:%x\n", __func__, major, minor); 239 240 disable_clks: 241 clk_disable_unprepare(ahb_clk); 242 disable_gdsc: 243 regulator_disable(gdsc_reg); 244 put_clk: 245 clk_put(ahb_clk); 246 put_gdsc: 247 regulator_put(gdsc_reg); 248 exit: 249 return cfg_hnd; 250 } 251 252 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 253 { 254 return container_of(host, struct msm_dsi_host, base); 255 } 256 257 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host) 258 { 259 struct regulator_bulk_data *s = msm_host->supplies; 260 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 261 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 262 int i; 263 264 DBG(""); 265 for (i = num - 1; i >= 0; i--) 266 if (regs[i].disable_load >= 0) 267 regulator_set_load(s[i].consumer, 268 regs[i].disable_load); 269 270 regulator_bulk_disable(num, s); 271 } 272 273 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host) 274 { 275 struct regulator_bulk_data *s = msm_host->supplies; 276 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 277 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 278 int ret, i; 279 280 DBG(""); 281 for (i = 0; i < num; i++) { 282 if (regs[i].enable_load >= 0) { 283 ret = regulator_set_load(s[i].consumer, 284 regs[i].enable_load); 285 if (ret < 0) { 286 pr_err("regulator %d set op mode failed, %d\n", 287 i, ret); 288 goto fail; 289 } 290 } 291 } 292 293 ret = regulator_bulk_enable(num, s); 294 if (ret < 0) { 295 pr_err("regulator enable failed, %d\n", ret); 296 goto fail; 297 } 298 299 return 0; 300 301 fail: 302 for (i--; i >= 0; i--) 303 regulator_set_load(s[i].consumer, regs[i].disable_load); 304 return ret; 305 } 306 307 static int dsi_regulator_init(struct msm_dsi_host *msm_host) 308 { 309 struct regulator_bulk_data *s = msm_host->supplies; 310 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 311 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 312 int i, ret; 313 314 for (i = 0; i < num; i++) 315 s[i].supply = regs[i].name; 316 317 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s); 318 if (ret < 0) { 319 pr_err("%s: failed to init regulator, ret=%d\n", 320 __func__, ret); 321 return ret; 322 } 323 324 for (i = 0; i < num; i++) { 325 if (regulator_can_change_voltage(s[i].consumer)) { 326 ret = regulator_set_voltage(s[i].consumer, 327 regs[i].min_voltage, regs[i].max_voltage); 328 if (ret < 0) { 329 pr_err("regulator %d set voltage failed, %d\n", 330 i, ret); 331 return ret; 332 } 333 } 334 } 335 336 return 0; 337 } 338 339 static int dsi_clk_init(struct msm_dsi_host *msm_host) 340 { 341 struct device *dev = &msm_host->pdev->dev; 342 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 343 const struct msm_dsi_config *cfg = cfg_hnd->cfg; 344 int i, ret = 0; 345 346 /* get bus clocks */ 347 for (i = 0; i < cfg->num_bus_clks; i++) { 348 msm_host->bus_clks[i] = devm_clk_get(dev, 349 cfg->bus_clk_names[i]); 350 if (IS_ERR(msm_host->bus_clks[i])) { 351 ret = PTR_ERR(msm_host->bus_clks[i]); 352 pr_err("%s: Unable to get %s, ret = %d\n", 353 __func__, cfg->bus_clk_names[i], ret); 354 goto exit; 355 } 356 } 357 358 /* get link and source clocks */ 359 msm_host->byte_clk = devm_clk_get(dev, "byte_clk"); 360 if (IS_ERR(msm_host->byte_clk)) { 361 ret = PTR_ERR(msm_host->byte_clk); 362 pr_err("%s: can't find dsi_byte_clk. ret=%d\n", 363 __func__, ret); 364 msm_host->byte_clk = NULL; 365 goto exit; 366 } 367 368 msm_host->pixel_clk = devm_clk_get(dev, "pixel_clk"); 369 if (IS_ERR(msm_host->pixel_clk)) { 370 ret = PTR_ERR(msm_host->pixel_clk); 371 pr_err("%s: can't find dsi_pixel_clk. ret=%d\n", 372 __func__, ret); 373 msm_host->pixel_clk = NULL; 374 goto exit; 375 } 376 377 msm_host->esc_clk = devm_clk_get(dev, "core_clk"); 378 if (IS_ERR(msm_host->esc_clk)) { 379 ret = PTR_ERR(msm_host->esc_clk); 380 pr_err("%s: can't find dsi_esc_clk. ret=%d\n", 381 __func__, ret); 382 msm_host->esc_clk = NULL; 383 goto exit; 384 } 385 386 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk); 387 if (!msm_host->byte_clk_src) { 388 ret = -ENODEV; 389 pr_err("%s: can't find byte_clk_src. ret=%d\n", __func__, ret); 390 goto exit; 391 } 392 393 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk); 394 if (!msm_host->pixel_clk_src) { 395 ret = -ENODEV; 396 pr_err("%s: can't find pixel_clk_src. ret=%d\n", __func__, ret); 397 goto exit; 398 } 399 400 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) { 401 msm_host->src_clk = devm_clk_get(dev, "src_clk"); 402 if (IS_ERR(msm_host->src_clk)) { 403 ret = PTR_ERR(msm_host->src_clk); 404 pr_err("%s: can't find dsi_src_clk. ret=%d\n", 405 __func__, ret); 406 msm_host->src_clk = NULL; 407 goto exit; 408 } 409 410 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk); 411 if (!msm_host->esc_clk_src) { 412 ret = -ENODEV; 413 pr_err("%s: can't get esc_clk_src. ret=%d\n", 414 __func__, ret); 415 goto exit; 416 } 417 418 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk); 419 if (!msm_host->dsi_clk_src) { 420 ret = -ENODEV; 421 pr_err("%s: can't get dsi_clk_src. ret=%d\n", 422 __func__, ret); 423 } 424 } 425 exit: 426 return ret; 427 } 428 429 static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host) 430 { 431 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 432 int i, ret; 433 434 DBG("id=%d", msm_host->id); 435 436 for (i = 0; i < cfg->num_bus_clks; i++) { 437 ret = clk_prepare_enable(msm_host->bus_clks[i]); 438 if (ret) { 439 pr_err("%s: failed to enable bus clock %d ret %d\n", 440 __func__, i, ret); 441 goto err; 442 } 443 } 444 445 return 0; 446 err: 447 for (; i > 0; i--) 448 clk_disable_unprepare(msm_host->bus_clks[i]); 449 450 return ret; 451 } 452 453 static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host) 454 { 455 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 456 int i; 457 458 DBG(""); 459 460 for (i = cfg->num_bus_clks - 1; i >= 0; i--) 461 clk_disable_unprepare(msm_host->bus_clks[i]); 462 } 463 464 static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) 465 { 466 int ret; 467 468 DBG("Set clk rates: pclk=%d, byteclk=%d", 469 msm_host->mode->clock, msm_host->byte_clk_rate); 470 471 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 472 if (ret) { 473 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 474 goto error; 475 } 476 477 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000); 478 if (ret) { 479 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 480 goto error; 481 } 482 483 ret = clk_prepare_enable(msm_host->esc_clk); 484 if (ret) { 485 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 486 goto error; 487 } 488 489 ret = clk_prepare_enable(msm_host->byte_clk); 490 if (ret) { 491 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 492 goto byte_clk_err; 493 } 494 495 ret = clk_prepare_enable(msm_host->pixel_clk); 496 if (ret) { 497 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 498 goto pixel_clk_err; 499 } 500 501 return 0; 502 503 pixel_clk_err: 504 clk_disable_unprepare(msm_host->byte_clk); 505 byte_clk_err: 506 clk_disable_unprepare(msm_host->esc_clk); 507 error: 508 return ret; 509 } 510 511 static int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) 512 { 513 int ret; 514 515 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d", 516 msm_host->mode->clock, msm_host->byte_clk_rate, 517 msm_host->esc_clk_rate, msm_host->src_clk_rate); 518 519 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 520 if (ret) { 521 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 522 goto error; 523 } 524 525 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); 526 if (ret) { 527 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); 528 goto error; 529 } 530 531 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); 532 if (ret) { 533 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); 534 goto error; 535 } 536 537 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000); 538 if (ret) { 539 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 540 goto error; 541 } 542 543 ret = clk_prepare_enable(msm_host->byte_clk); 544 if (ret) { 545 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 546 goto error; 547 } 548 549 ret = clk_prepare_enable(msm_host->esc_clk); 550 if (ret) { 551 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 552 goto esc_clk_err; 553 } 554 555 ret = clk_prepare_enable(msm_host->src_clk); 556 if (ret) { 557 pr_err("%s: Failed to enable dsi src clk\n", __func__); 558 goto src_clk_err; 559 } 560 561 ret = clk_prepare_enable(msm_host->pixel_clk); 562 if (ret) { 563 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 564 goto pixel_clk_err; 565 } 566 567 return 0; 568 569 pixel_clk_err: 570 clk_disable_unprepare(msm_host->src_clk); 571 src_clk_err: 572 clk_disable_unprepare(msm_host->esc_clk); 573 esc_clk_err: 574 clk_disable_unprepare(msm_host->byte_clk); 575 error: 576 return ret; 577 } 578 579 static int dsi_link_clk_enable(struct msm_dsi_host *msm_host) 580 { 581 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 582 583 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) 584 return dsi_link_clk_enable_6g(msm_host); 585 else 586 return dsi_link_clk_enable_v2(msm_host); 587 } 588 589 static void dsi_link_clk_disable(struct msm_dsi_host *msm_host) 590 { 591 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 592 593 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { 594 clk_disable_unprepare(msm_host->esc_clk); 595 clk_disable_unprepare(msm_host->pixel_clk); 596 clk_disable_unprepare(msm_host->byte_clk); 597 } else { 598 clk_disable_unprepare(msm_host->pixel_clk); 599 clk_disable_unprepare(msm_host->src_clk); 600 clk_disable_unprepare(msm_host->esc_clk); 601 clk_disable_unprepare(msm_host->byte_clk); 602 } 603 } 604 605 static int dsi_clk_ctrl(struct msm_dsi_host *msm_host, bool enable) 606 { 607 int ret = 0; 608 609 mutex_lock(&msm_host->clk_mutex); 610 if (enable) { 611 ret = dsi_bus_clk_enable(msm_host); 612 if (ret) { 613 pr_err("%s: Can not enable bus clk, %d\n", 614 __func__, ret); 615 goto unlock_ret; 616 } 617 ret = dsi_link_clk_enable(msm_host); 618 if (ret) { 619 pr_err("%s: Can not enable link clk, %d\n", 620 __func__, ret); 621 dsi_bus_clk_disable(msm_host); 622 goto unlock_ret; 623 } 624 } else { 625 dsi_link_clk_disable(msm_host); 626 dsi_bus_clk_disable(msm_host); 627 } 628 629 unlock_ret: 630 mutex_unlock(&msm_host->clk_mutex); 631 return ret; 632 } 633 634 static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host) 635 { 636 struct drm_display_mode *mode = msm_host->mode; 637 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 638 u8 lanes = msm_host->lanes; 639 u32 bpp = dsi_get_bpp(msm_host->format); 640 u32 pclk_rate; 641 642 if (!mode) { 643 pr_err("%s: mode not set\n", __func__); 644 return -EINVAL; 645 } 646 647 pclk_rate = mode->clock * 1000; 648 if (lanes > 0) { 649 msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes); 650 } else { 651 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 652 msm_host->byte_clk_rate = (pclk_rate * bpp) / 8; 653 } 654 655 DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate); 656 657 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); 658 659 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) { 660 unsigned int esc_mhz, esc_div; 661 unsigned long byte_mhz; 662 663 msm_host->src_clk_rate = (pclk_rate * bpp) / 8; 664 665 /* 666 * esc clock is byte clock followed by a 4 bit divider, 667 * we need to find an escape clock frequency within the 668 * mipi DSI spec range within the maximum divider limit 669 * We iterate here between an escape clock frequencey 670 * between 20 Mhz to 5 Mhz and pick up the first one 671 * that can be supported by our divider 672 */ 673 674 byte_mhz = msm_host->byte_clk_rate / 1000000; 675 676 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { 677 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); 678 679 /* 680 * TODO: Ideally, we shouldn't know what sort of divider 681 * is available in mmss_cc, we're just assuming that 682 * it'll always be a 4 bit divider. Need to come up with 683 * a better way here. 684 */ 685 if (esc_div >= 1 && esc_div <= 16) 686 break; 687 } 688 689 if (esc_mhz < 5) 690 return -EINVAL; 691 692 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; 693 694 DBG("esc=%d, src=%d", msm_host->esc_clk_rate, 695 msm_host->src_clk_rate); 696 } 697 698 return 0; 699 } 700 701 static void dsi_phy_sw_reset(struct msm_dsi_host *msm_host) 702 { 703 DBG(""); 704 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 705 /* Make sure fully reset */ 706 wmb(); 707 udelay(1000); 708 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 709 udelay(100); 710 } 711 712 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 713 { 714 u32 intr; 715 unsigned long flags; 716 717 spin_lock_irqsave(&msm_host->intr_lock, flags); 718 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 719 720 if (enable) 721 intr |= mask; 722 else 723 intr &= ~mask; 724 725 DBG("intr=%x enable=%d", intr, enable); 726 727 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 728 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 729 } 730 731 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 732 { 733 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 734 return BURST_MODE; 735 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 736 return NON_BURST_SYNCH_PULSE; 737 738 return NON_BURST_SYNCH_EVENT; 739 } 740 741 static inline enum dsi_vid_dst_format dsi_get_vid_fmt( 742 const enum mipi_dsi_pixel_format mipi_fmt) 743 { 744 switch (mipi_fmt) { 745 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 746 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 747 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 748 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 749 default: return VID_DST_FORMAT_RGB888; 750 } 751 } 752 753 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( 754 const enum mipi_dsi_pixel_format mipi_fmt) 755 { 756 switch (mipi_fmt) { 757 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 758 case MIPI_DSI_FMT_RGB666_PACKED: 759 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666; 760 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 761 default: return CMD_DST_FORMAT_RGB888; 762 } 763 } 764 765 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, 766 u32 clk_pre, u32 clk_post) 767 { 768 u32 flags = msm_host->mode_flags; 769 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 770 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 771 u32 data = 0; 772 773 if (!enable) { 774 dsi_write(msm_host, REG_DSI_CTRL, 0); 775 return; 776 } 777 778 if (flags & MIPI_DSI_MODE_VIDEO) { 779 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 780 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 781 if (flags & MIPI_DSI_MODE_VIDEO_HFP) 782 data |= DSI_VID_CFG0_HFP_POWER_STOP; 783 if (flags & MIPI_DSI_MODE_VIDEO_HBP) 784 data |= DSI_VID_CFG0_HBP_POWER_STOP; 785 if (flags & MIPI_DSI_MODE_VIDEO_HSA) 786 data |= DSI_VID_CFG0_HSA_POWER_STOP; 787 /* Always set low power stop mode for BLLP 788 * to let command engine send packets 789 */ 790 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 791 DSI_VID_CFG0_BLLP_POWER_STOP; 792 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 793 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 794 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 795 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 796 797 /* Do not swap RGB colors */ 798 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 799 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 800 } else { 801 /* Do not swap RGB colors */ 802 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 803 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 804 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 805 806 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 807 DSI_CMD_CFG1_WR_MEM_CONTINUE( 808 MIPI_DCS_WRITE_MEMORY_CONTINUE); 809 /* Always insert DCS command */ 810 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 811 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 812 } 813 814 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 815 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 816 DSI_CMD_DMA_CTRL_LOW_POWER); 817 818 data = 0; 819 /* Always assume dedicated TE pin */ 820 data |= DSI_TRIG_CTRL_TE; 821 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 822 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 823 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 824 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 825 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 826 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 827 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 828 829 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(clk_post) | 830 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(clk_pre); 831 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 832 833 data = 0; 834 if (!(flags & MIPI_DSI_MODE_EOT_PACKET)) 835 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 836 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 837 838 /* allow only ack-err-status to generate interrupt */ 839 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 840 841 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 842 843 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 844 845 data = DSI_CTRL_CLK_EN; 846 847 DBG("lane number=%d", msm_host->lanes); 848 if (msm_host->lanes == 2) { 849 data |= DSI_CTRL_LANE1 | DSI_CTRL_LANE2; 850 /* swap lanes for 2-lane panel for better performance */ 851 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 852 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_1230)); 853 } else { 854 /* Take 4 lanes as default */ 855 data |= DSI_CTRL_LANE0 | DSI_CTRL_LANE1 | DSI_CTRL_LANE2 | 856 DSI_CTRL_LANE3; 857 /* Do not swap lanes for 4-lane panel */ 858 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 859 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_0123)); 860 } 861 862 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 863 dsi_write(msm_host, REG_DSI_LANE_CTRL, 864 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); 865 866 data |= DSI_CTRL_ENABLE; 867 868 dsi_write(msm_host, REG_DSI_CTRL, data); 869 } 870 871 static void dsi_timing_setup(struct msm_dsi_host *msm_host) 872 { 873 struct drm_display_mode *mode = msm_host->mode; 874 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 875 u32 h_total = mode->htotal; 876 u32 v_total = mode->vtotal; 877 u32 hs_end = mode->hsync_end - mode->hsync_start; 878 u32 vs_end = mode->vsync_end - mode->vsync_start; 879 u32 ha_start = h_total - mode->hsync_start; 880 u32 ha_end = ha_start + mode->hdisplay; 881 u32 va_start = v_total - mode->vsync_start; 882 u32 va_end = va_start + mode->vdisplay; 883 u32 wc; 884 885 DBG(""); 886 887 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 888 dsi_write(msm_host, REG_DSI_ACTIVE_H, 889 DSI_ACTIVE_H_START(ha_start) | 890 DSI_ACTIVE_H_END(ha_end)); 891 dsi_write(msm_host, REG_DSI_ACTIVE_V, 892 DSI_ACTIVE_V_START(va_start) | 893 DSI_ACTIVE_V_END(va_end)); 894 dsi_write(msm_host, REG_DSI_TOTAL, 895 DSI_TOTAL_H_TOTAL(h_total - 1) | 896 DSI_TOTAL_V_TOTAL(v_total - 1)); 897 898 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 899 DSI_ACTIVE_HSYNC_START(hs_start) | 900 DSI_ACTIVE_HSYNC_END(hs_end)); 901 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 902 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 903 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 904 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 905 } else { /* command mode */ 906 /* image data and 1 byte write_memory_start cmd */ 907 wc = mode->hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; 908 909 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL, 910 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) | 911 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL( 912 msm_host->channel) | 913 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE( 914 MIPI_DSI_DCS_LONG_WRITE)); 915 916 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL, 917 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(mode->hdisplay) | 918 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay)); 919 } 920 } 921 922 static void dsi_sw_reset(struct msm_dsi_host *msm_host) 923 { 924 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 925 wmb(); /* clocks need to be enabled before reset */ 926 927 dsi_write(msm_host, REG_DSI_RESET, 1); 928 wmb(); /* make sure reset happen */ 929 dsi_write(msm_host, REG_DSI_RESET, 0); 930 } 931 932 static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 933 bool video_mode, bool enable) 934 { 935 u32 dsi_ctrl; 936 937 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 938 939 if (!enable) { 940 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 941 DSI_CTRL_CMD_MODE_EN); 942 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 943 DSI_IRQ_MASK_VIDEO_DONE, 0); 944 } else { 945 if (video_mode) { 946 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 947 } else { /* command mode */ 948 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 949 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 950 } 951 dsi_ctrl |= DSI_CTRL_ENABLE; 952 } 953 954 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 955 } 956 957 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 958 { 959 u32 data; 960 961 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 962 963 if (mode == 0) 964 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 965 else 966 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 967 968 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 969 } 970 971 static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 972 { 973 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 974 975 reinit_completion(&msm_host->video_comp); 976 977 wait_for_completion_timeout(&msm_host->video_comp, 978 msecs_to_jiffies(70)); 979 980 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 981 } 982 983 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 984 { 985 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 986 return; 987 988 if (msm_host->power_on) { 989 dsi_wait4video_done(msm_host); 990 /* delay 4 ms to skip BLLP */ 991 usleep_range(2000, 4000); 992 } 993 } 994 995 /* dsi_cmd */ 996 static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size) 997 { 998 struct drm_device *dev = msm_host->dev; 999 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1000 int ret; 1001 u32 iova; 1002 1003 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { 1004 mutex_lock(&dev->struct_mutex); 1005 msm_host->tx_gem_obj = msm_gem_new(dev, size, MSM_BO_UNCACHED); 1006 if (IS_ERR(msm_host->tx_gem_obj)) { 1007 ret = PTR_ERR(msm_host->tx_gem_obj); 1008 pr_err("%s: failed to allocate gem, %d\n", 1009 __func__, ret); 1010 msm_host->tx_gem_obj = NULL; 1011 mutex_unlock(&dev->struct_mutex); 1012 return ret; 1013 } 1014 1015 ret = msm_gem_get_iova_locked(msm_host->tx_gem_obj, 0, &iova); 1016 mutex_unlock(&dev->struct_mutex); 1017 if (ret) { 1018 pr_err("%s: failed to get iova, %d\n", __func__, ret); 1019 return ret; 1020 } 1021 1022 if (iova & 0x07) { 1023 pr_err("%s: buf NOT 8 bytes aligned\n", __func__); 1024 return -EINVAL; 1025 } 1026 1027 msm_host->tx_size = msm_host->tx_gem_obj->size; 1028 } else { 1029 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, 1030 &msm_host->tx_buf_paddr, GFP_KERNEL); 1031 if (!msm_host->tx_buf) { 1032 ret = -ENOMEM; 1033 pr_err("%s: failed to allocate tx buf, %d\n", 1034 __func__, ret); 1035 return ret; 1036 } 1037 1038 msm_host->tx_size = size; 1039 } 1040 1041 return 0; 1042 } 1043 1044 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host) 1045 { 1046 struct drm_device *dev = msm_host->dev; 1047 1048 if (msm_host->tx_gem_obj) { 1049 msm_gem_put_iova(msm_host->tx_gem_obj, 0); 1050 mutex_lock(&dev->struct_mutex); 1051 msm_gem_free_object(msm_host->tx_gem_obj); 1052 msm_host->tx_gem_obj = NULL; 1053 mutex_unlock(&dev->struct_mutex); 1054 } 1055 1056 if (msm_host->tx_buf) 1057 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, 1058 msm_host->tx_buf_paddr); 1059 } 1060 1061 /* 1062 * prepare cmd buffer to be txed 1063 */ 1064 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, 1065 const struct mipi_dsi_msg *msg) 1066 { 1067 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1068 struct mipi_dsi_packet packet; 1069 int len; 1070 int ret; 1071 u8 *data; 1072 1073 ret = mipi_dsi_create_packet(&packet, msg); 1074 if (ret) { 1075 pr_err("%s: create packet failed, %d\n", __func__, ret); 1076 return ret; 1077 } 1078 len = (packet.size + 3) & (~0x3); 1079 1080 if (len > msm_host->tx_size) { 1081 pr_err("%s: packet size is too big\n", __func__); 1082 return -EINVAL; 1083 } 1084 1085 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { 1086 data = msm_gem_vaddr(msm_host->tx_gem_obj); 1087 if (IS_ERR(data)) { 1088 ret = PTR_ERR(data); 1089 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 1090 return ret; 1091 } 1092 } else { 1093 data = msm_host->tx_buf; 1094 } 1095 1096 /* MSM specific command format in memory */ 1097 data[0] = packet.header[1]; 1098 data[1] = packet.header[2]; 1099 data[2] = packet.header[0]; 1100 data[3] = BIT(7); /* Last packet */ 1101 if (mipi_dsi_packet_format_is_long(msg->type)) 1102 data[3] |= BIT(6); 1103 if (msg->rx_buf && msg->rx_len) 1104 data[3] |= BIT(5); 1105 1106 /* Long packet */ 1107 if (packet.payload && packet.payload_length) 1108 memcpy(data + 4, packet.payload, packet.payload_length); 1109 1110 /* Append 0xff to the end */ 1111 if (packet.size < len) 1112 memset(data + packet.size, 0xff, len - packet.size); 1113 1114 return len; 1115 } 1116 1117 /* 1118 * dsi_short_read1_resp: 1 parameter 1119 */ 1120 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1121 { 1122 u8 *data = msg->rx_buf; 1123 if (data && (msg->rx_len >= 1)) { 1124 *data = buf[1]; /* strip out dcs type */ 1125 return 1; 1126 } else { 1127 pr_err("%s: read data does not match with rx_buf len %zu\n", 1128 __func__, msg->rx_len); 1129 return -EINVAL; 1130 } 1131 } 1132 1133 /* 1134 * dsi_short_read2_resp: 2 parameter 1135 */ 1136 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1137 { 1138 u8 *data = msg->rx_buf; 1139 if (data && (msg->rx_len >= 2)) { 1140 data[0] = buf[1]; /* strip out dcs type */ 1141 data[1] = buf[2]; 1142 return 2; 1143 } else { 1144 pr_err("%s: read data does not match with rx_buf len %zu\n", 1145 __func__, msg->rx_len); 1146 return -EINVAL; 1147 } 1148 } 1149 1150 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1151 { 1152 /* strip out 4 byte dcs header */ 1153 if (msg->rx_buf && msg->rx_len) 1154 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 1155 1156 return msg->rx_len; 1157 } 1158 1159 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 1160 { 1161 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1162 int ret; 1163 u32 dma_base; 1164 bool triggered; 1165 1166 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { 1167 ret = msm_gem_get_iova(msm_host->tx_gem_obj, 0, &dma_base); 1168 if (ret) { 1169 pr_err("%s: failed to get iova: %d\n", __func__, ret); 1170 return ret; 1171 } 1172 } else { 1173 dma_base = msm_host->tx_buf_paddr; 1174 } 1175 1176 reinit_completion(&msm_host->dma_comp); 1177 1178 dsi_wait4video_eng_busy(msm_host); 1179 1180 triggered = msm_dsi_manager_cmd_xfer_trigger( 1181 msm_host->id, dma_base, len); 1182 if (triggered) { 1183 ret = wait_for_completion_timeout(&msm_host->dma_comp, 1184 msecs_to_jiffies(200)); 1185 DBG("ret=%d", ret); 1186 if (ret == 0) 1187 ret = -ETIMEDOUT; 1188 else 1189 ret = len; 1190 } else 1191 ret = len; 1192 1193 return ret; 1194 } 1195 1196 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1197 u8 *buf, int rx_byte, int pkt_size) 1198 { 1199 u32 *lp, *temp, data; 1200 int i, j = 0, cnt; 1201 u32 read_cnt; 1202 u8 reg[16]; 1203 int repeated_bytes = 0; 1204 int buf_offset = buf - msm_host->rx_buf; 1205 1206 lp = (u32 *)buf; 1207 temp = (u32 *)reg; 1208 cnt = (rx_byte + 3) >> 2; 1209 if (cnt > 4) 1210 cnt = 4; /* 4 x 32 bits registers only */ 1211 1212 if (rx_byte == 4) 1213 read_cnt = 4; 1214 else 1215 read_cnt = pkt_size + 6; 1216 1217 /* 1218 * In case of multiple reads from the panel, after the first read, there 1219 * is possibility that there are some bytes in the payload repeating in 1220 * the RDBK_DATA registers. Since we read all the parameters from the 1221 * panel right from the first byte for every pass. We need to skip the 1222 * repeating bytes and then append the new parameters to the rx buffer. 1223 */ 1224 if (read_cnt > 16) { 1225 int bytes_shifted; 1226 /* Any data more than 16 bytes will be shifted out. 1227 * The temp read buffer should already contain these bytes. 1228 * The remaining bytes in read buffer are the repeated bytes. 1229 */ 1230 bytes_shifted = read_cnt - 16; 1231 repeated_bytes = buf_offset - bytes_shifted; 1232 } 1233 1234 for (i = cnt - 1; i >= 0; i--) { 1235 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1236 *temp++ = ntohl(data); /* to host byte order */ 1237 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1238 } 1239 1240 for (i = repeated_bytes; i < 16; i++) 1241 buf[j++] = reg[i]; 1242 1243 return j; 1244 } 1245 1246 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1247 const struct mipi_dsi_msg *msg) 1248 { 1249 int len, ret; 1250 int bllp_len = msm_host->mode->hdisplay * 1251 dsi_get_bpp(msm_host->format) / 8; 1252 1253 len = dsi_cmd_dma_add(msm_host, msg); 1254 if (!len) { 1255 pr_err("%s: failed to add cmd type = 0x%x\n", 1256 __func__, msg->type); 1257 return -EINVAL; 1258 } 1259 1260 /* for video mode, do not send cmds more than 1261 * one pixel line, since it only transmit it 1262 * during BLLP. 1263 */ 1264 /* TODO: if the command is sent in LP mode, the bit rate is only 1265 * half of esc clk rate. In this case, if the video is already 1266 * actively streaming, we need to check more carefully if the 1267 * command can be fit into one BLLP. 1268 */ 1269 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1270 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1271 __func__, len); 1272 return -EINVAL; 1273 } 1274 1275 ret = dsi_cmd_dma_tx(msm_host, len); 1276 if (ret < len) { 1277 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n", 1278 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len); 1279 return -ECOMM; 1280 } 1281 1282 return len; 1283 } 1284 1285 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host) 1286 { 1287 u32 data0, data1; 1288 1289 data0 = dsi_read(msm_host, REG_DSI_CTRL); 1290 data1 = data0; 1291 data1 &= ~DSI_CTRL_ENABLE; 1292 dsi_write(msm_host, REG_DSI_CTRL, data1); 1293 /* 1294 * dsi controller need to be disabled before 1295 * clocks turned on 1296 */ 1297 wmb(); 1298 1299 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1300 wmb(); /* make sure clocks enabled */ 1301 1302 /* dsi controller can only be reset while clocks are running */ 1303 dsi_write(msm_host, REG_DSI_RESET, 1); 1304 wmb(); /* make sure reset happen */ 1305 dsi_write(msm_host, REG_DSI_RESET, 0); 1306 wmb(); /* controller out of reset */ 1307 dsi_write(msm_host, REG_DSI_CTRL, data0); 1308 wmb(); /* make sure dsi controller enabled again */ 1309 } 1310 1311 static void dsi_err_worker(struct work_struct *work) 1312 { 1313 struct msm_dsi_host *msm_host = 1314 container_of(work, struct msm_dsi_host, err_work); 1315 u32 status = msm_host->err_work_state; 1316 1317 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1318 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1319 dsi_sw_reset_restore(msm_host); 1320 1321 /* It is safe to clear here because error irq is disabled. */ 1322 msm_host->err_work_state = 0; 1323 1324 /* enable dsi error interrupt */ 1325 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1326 } 1327 1328 static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1329 { 1330 u32 status; 1331 1332 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1333 1334 if (status) { 1335 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1336 /* Writing of an extra 0 needed to clear error bits */ 1337 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1338 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1339 } 1340 } 1341 1342 static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1343 { 1344 u32 status; 1345 1346 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1347 1348 if (status) { 1349 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1350 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1351 } 1352 } 1353 1354 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1355 { 1356 u32 status; 1357 1358 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1359 1360 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | 1361 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | 1362 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | 1363 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | 1364 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { 1365 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1366 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1367 } 1368 } 1369 1370 static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1371 { 1372 u32 status; 1373 1374 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1375 1376 /* fifo underflow, overflow */ 1377 if (status) { 1378 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1379 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1380 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1381 msm_host->err_work_state |= 1382 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1383 } 1384 } 1385 1386 static void dsi_status(struct msm_dsi_host *msm_host) 1387 { 1388 u32 status; 1389 1390 status = dsi_read(msm_host, REG_DSI_STATUS0); 1391 1392 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1393 dsi_write(msm_host, REG_DSI_STATUS0, status); 1394 msm_host->err_work_state |= 1395 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1396 } 1397 } 1398 1399 static void dsi_clk_status(struct msm_dsi_host *msm_host) 1400 { 1401 u32 status; 1402 1403 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1404 1405 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1406 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1407 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1408 } 1409 } 1410 1411 static void dsi_error(struct msm_dsi_host *msm_host) 1412 { 1413 /* disable dsi error interrupt */ 1414 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1415 1416 dsi_clk_status(msm_host); 1417 dsi_fifo_status(msm_host); 1418 dsi_ack_err_status(msm_host); 1419 dsi_timeout_status(msm_host); 1420 dsi_status(msm_host); 1421 dsi_dln0_phy_err(msm_host); 1422 1423 queue_work(msm_host->workqueue, &msm_host->err_work); 1424 } 1425 1426 static irqreturn_t dsi_host_irq(int irq, void *ptr) 1427 { 1428 struct msm_dsi_host *msm_host = ptr; 1429 u32 isr; 1430 unsigned long flags; 1431 1432 if (!msm_host->ctrl_base) 1433 return IRQ_HANDLED; 1434 1435 spin_lock_irqsave(&msm_host->intr_lock, flags); 1436 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1437 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1438 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1439 1440 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1441 1442 if (isr & DSI_IRQ_ERROR) 1443 dsi_error(msm_host); 1444 1445 if (isr & DSI_IRQ_VIDEO_DONE) 1446 complete(&msm_host->video_comp); 1447 1448 if (isr & DSI_IRQ_CMD_DMA_DONE) 1449 complete(&msm_host->dma_comp); 1450 1451 return IRQ_HANDLED; 1452 } 1453 1454 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, 1455 struct device *panel_device) 1456 { 1457 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device, 1458 "disp-enable", 1459 GPIOD_OUT_LOW); 1460 if (IS_ERR(msm_host->disp_en_gpio)) { 1461 DBG("cannot get disp-enable-gpios %ld", 1462 PTR_ERR(msm_host->disp_en_gpio)); 1463 return PTR_ERR(msm_host->disp_en_gpio); 1464 } 1465 1466 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te", 1467 GPIOD_IN); 1468 if (IS_ERR(msm_host->te_gpio)) { 1469 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); 1470 return PTR_ERR(msm_host->te_gpio); 1471 } 1472 1473 return 0; 1474 } 1475 1476 static int dsi_host_attach(struct mipi_dsi_host *host, 1477 struct mipi_dsi_device *dsi) 1478 { 1479 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1480 int ret; 1481 1482 msm_host->channel = dsi->channel; 1483 msm_host->lanes = dsi->lanes; 1484 msm_host->format = dsi->format; 1485 msm_host->mode_flags = dsi->mode_flags; 1486 1487 WARN_ON(dsi->dev.of_node != msm_host->device_node); 1488 1489 /* Some gpios defined in panel DT need to be controlled by host */ 1490 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); 1491 if (ret) 1492 return ret; 1493 1494 DBG("id=%d", msm_host->id); 1495 if (msm_host->dev) 1496 drm_helper_hpd_irq_event(msm_host->dev); 1497 1498 return 0; 1499 } 1500 1501 static int dsi_host_detach(struct mipi_dsi_host *host, 1502 struct mipi_dsi_device *dsi) 1503 { 1504 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1505 1506 msm_host->device_node = NULL; 1507 1508 DBG("id=%d", msm_host->id); 1509 if (msm_host->dev) 1510 drm_helper_hpd_irq_event(msm_host->dev); 1511 1512 return 0; 1513 } 1514 1515 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1516 const struct mipi_dsi_msg *msg) 1517 { 1518 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1519 int ret; 1520 1521 if (!msg || !msm_host->power_on) 1522 return -EINVAL; 1523 1524 mutex_lock(&msm_host->cmd_mutex); 1525 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1526 mutex_unlock(&msm_host->cmd_mutex); 1527 1528 return ret; 1529 } 1530 1531 static struct mipi_dsi_host_ops dsi_host_ops = { 1532 .attach = dsi_host_attach, 1533 .detach = dsi_host_detach, 1534 .transfer = dsi_host_transfer, 1535 }; 1536 1537 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) 1538 { 1539 struct device *dev = &msm_host->pdev->dev; 1540 struct device_node *np = dev->of_node; 1541 struct device_node *endpoint, *device_node; 1542 int ret; 1543 1544 ret = of_property_read_u32(np, "qcom,dsi-host-index", &msm_host->id); 1545 if (ret) { 1546 dev_err(dev, "%s: host index not specified, ret=%d\n", 1547 __func__, ret); 1548 return ret; 1549 } 1550 1551 /* 1552 * Get the first endpoint node. In our case, dsi has one output port 1553 * to which the panel is connected. Don't return an error if a port 1554 * isn't defined. It's possible that there is nothing connected to 1555 * the dsi output. 1556 */ 1557 endpoint = of_graph_get_next_endpoint(np, NULL); 1558 if (!endpoint) { 1559 dev_dbg(dev, "%s: no endpoint\n", __func__); 1560 return 0; 1561 } 1562 1563 /* Get panel node from the output port's endpoint data */ 1564 device_node = of_graph_get_remote_port_parent(endpoint); 1565 if (!device_node) { 1566 dev_err(dev, "%s: no valid device\n", __func__); 1567 of_node_put(endpoint); 1568 return -ENODEV; 1569 } 1570 1571 of_node_put(endpoint); 1572 of_node_put(device_node); 1573 1574 msm_host->device_node = device_node; 1575 1576 if (of_property_read_bool(np, "syscon-sfpb")) { 1577 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, 1578 "syscon-sfpb"); 1579 if (IS_ERR(msm_host->sfpb)) { 1580 dev_err(dev, "%s: failed to get sfpb regmap\n", 1581 __func__); 1582 return PTR_ERR(msm_host->sfpb); 1583 } 1584 } 1585 1586 return 0; 1587 } 1588 1589 int msm_dsi_host_init(struct msm_dsi *msm_dsi) 1590 { 1591 struct msm_dsi_host *msm_host = NULL; 1592 struct platform_device *pdev = msm_dsi->pdev; 1593 int ret; 1594 1595 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 1596 if (!msm_host) { 1597 pr_err("%s: FAILED: cannot alloc dsi host\n", 1598 __func__); 1599 ret = -ENOMEM; 1600 goto fail; 1601 } 1602 1603 msm_host->pdev = pdev; 1604 1605 ret = dsi_host_parse_dt(msm_host); 1606 if (ret) { 1607 pr_err("%s: failed to parse dt\n", __func__); 1608 goto fail; 1609 } 1610 1611 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL"); 1612 if (IS_ERR(msm_host->ctrl_base)) { 1613 pr_err("%s: unable to map Dsi ctrl base\n", __func__); 1614 ret = PTR_ERR(msm_host->ctrl_base); 1615 goto fail; 1616 } 1617 1618 msm_host->cfg_hnd = dsi_get_config(msm_host); 1619 if (!msm_host->cfg_hnd) { 1620 ret = -EINVAL; 1621 pr_err("%s: get config failed\n", __func__); 1622 goto fail; 1623 } 1624 1625 /* fixup base address by io offset */ 1626 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset; 1627 1628 ret = dsi_regulator_init(msm_host); 1629 if (ret) { 1630 pr_err("%s: regulator init failed\n", __func__); 1631 goto fail; 1632 } 1633 1634 ret = dsi_clk_init(msm_host); 1635 if (ret) { 1636 pr_err("%s: unable to initialize dsi clks\n", __func__); 1637 goto fail; 1638 } 1639 1640 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 1641 if (!msm_host->rx_buf) { 1642 pr_err("%s: alloc rx temp buf failed\n", __func__); 1643 goto fail; 1644 } 1645 1646 init_completion(&msm_host->dma_comp); 1647 init_completion(&msm_host->video_comp); 1648 mutex_init(&msm_host->dev_mutex); 1649 mutex_init(&msm_host->cmd_mutex); 1650 mutex_init(&msm_host->clk_mutex); 1651 spin_lock_init(&msm_host->intr_lock); 1652 1653 /* setup workqueue */ 1654 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 1655 INIT_WORK(&msm_host->err_work, dsi_err_worker); 1656 1657 msm_dsi->host = &msm_host->base; 1658 msm_dsi->id = msm_host->id; 1659 1660 DBG("Dsi Host %d initialized", msm_host->id); 1661 return 0; 1662 1663 fail: 1664 return ret; 1665 } 1666 1667 void msm_dsi_host_destroy(struct mipi_dsi_host *host) 1668 { 1669 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1670 1671 DBG(""); 1672 dsi_tx_buf_free(msm_host); 1673 if (msm_host->workqueue) { 1674 flush_workqueue(msm_host->workqueue); 1675 destroy_workqueue(msm_host->workqueue); 1676 msm_host->workqueue = NULL; 1677 } 1678 1679 mutex_destroy(&msm_host->clk_mutex); 1680 mutex_destroy(&msm_host->cmd_mutex); 1681 mutex_destroy(&msm_host->dev_mutex); 1682 } 1683 1684 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 1685 struct drm_device *dev) 1686 { 1687 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1688 struct platform_device *pdev = msm_host->pdev; 1689 int ret; 1690 1691 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1692 if (msm_host->irq < 0) { 1693 ret = msm_host->irq; 1694 dev_err(dev->dev, "failed to get irq: %d\n", ret); 1695 return ret; 1696 } 1697 1698 ret = devm_request_irq(&pdev->dev, msm_host->irq, 1699 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1700 "dsi_isr", msm_host); 1701 if (ret < 0) { 1702 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n", 1703 msm_host->irq, ret); 1704 return ret; 1705 } 1706 1707 msm_host->dev = dev; 1708 ret = dsi_tx_buf_alloc(msm_host, SZ_4K); 1709 if (ret) { 1710 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 1711 return ret; 1712 } 1713 1714 return 0; 1715 } 1716 1717 int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer) 1718 { 1719 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1720 int ret; 1721 1722 /* Register mipi dsi host */ 1723 if (!msm_host->registered) { 1724 host->dev = &msm_host->pdev->dev; 1725 host->ops = &dsi_host_ops; 1726 ret = mipi_dsi_host_register(host); 1727 if (ret) 1728 return ret; 1729 1730 msm_host->registered = true; 1731 1732 /* If the panel driver has not been probed after host register, 1733 * we should defer the host's probe. 1734 * It makes sure panel is connected when fbcon detects 1735 * connector status and gets the proper display mode to 1736 * create framebuffer. 1737 * Don't try to defer if there is nothing connected to the dsi 1738 * output 1739 */ 1740 if (check_defer && msm_host->device_node) { 1741 if (!of_drm_find_panel(msm_host->device_node)) 1742 if (!of_drm_find_bridge(msm_host->device_node)) 1743 return -EPROBE_DEFER; 1744 } 1745 } 1746 1747 return 0; 1748 } 1749 1750 void msm_dsi_host_unregister(struct mipi_dsi_host *host) 1751 { 1752 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1753 1754 if (msm_host->registered) { 1755 mipi_dsi_host_unregister(host); 1756 host->dev = NULL; 1757 host->ops = NULL; 1758 msm_host->registered = false; 1759 } 1760 } 1761 1762 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 1763 const struct mipi_dsi_msg *msg) 1764 { 1765 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1766 1767 /* TODO: make sure dsi_cmd_mdp is idle. 1768 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 1769 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 1770 * How to handle the old versions? Wait for mdp cmd done? 1771 */ 1772 1773 /* 1774 * mdss interrupt is generated in mdp core clock domain 1775 * mdp clock need to be enabled to receive dsi interrupt 1776 */ 1777 dsi_clk_ctrl(msm_host, 1); 1778 1779 /* TODO: vote for bus bandwidth */ 1780 1781 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 1782 dsi_set_tx_power_mode(0, msm_host); 1783 1784 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 1785 dsi_write(msm_host, REG_DSI_CTRL, 1786 msm_host->dma_cmd_ctrl_restore | 1787 DSI_CTRL_CMD_MODE_EN | 1788 DSI_CTRL_ENABLE); 1789 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 1790 1791 return 0; 1792 } 1793 1794 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 1795 const struct mipi_dsi_msg *msg) 1796 { 1797 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1798 1799 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 1800 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 1801 1802 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 1803 dsi_set_tx_power_mode(1, msm_host); 1804 1805 /* TODO: unvote for bus bandwidth */ 1806 1807 dsi_clk_ctrl(msm_host, 0); 1808 } 1809 1810 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 1811 const struct mipi_dsi_msg *msg) 1812 { 1813 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1814 1815 return dsi_cmds2buf_tx(msm_host, msg); 1816 } 1817 1818 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 1819 const struct mipi_dsi_msg *msg) 1820 { 1821 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1822 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1823 int data_byte, rx_byte, dlen, end; 1824 int short_response, diff, pkt_size, ret = 0; 1825 char cmd; 1826 int rlen = msg->rx_len; 1827 u8 *buf; 1828 1829 if (rlen <= 2) { 1830 short_response = 1; 1831 pkt_size = rlen; 1832 rx_byte = 4; 1833 } else { 1834 short_response = 0; 1835 data_byte = 10; /* first read */ 1836 if (rlen < data_byte) 1837 pkt_size = rlen; 1838 else 1839 pkt_size = data_byte; 1840 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 1841 } 1842 1843 buf = msm_host->rx_buf; 1844 end = 0; 1845 while (!end) { 1846 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 1847 struct mipi_dsi_msg max_pkt_size_msg = { 1848 .channel = msg->channel, 1849 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 1850 .tx_len = 2, 1851 .tx_buf = tx, 1852 }; 1853 1854 DBG("rlen=%d pkt_size=%d rx_byte=%d", 1855 rlen, pkt_size, rx_byte); 1856 1857 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 1858 if (ret < 2) { 1859 pr_err("%s: Set max pkt size failed, %d\n", 1860 __func__, ret); 1861 return -EINVAL; 1862 } 1863 1864 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 1865 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 1866 /* Clear the RDBK_DATA registers */ 1867 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 1868 DSI_RDBK_DATA_CTRL_CLR); 1869 wmb(); /* make sure the RDBK registers are cleared */ 1870 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 1871 wmb(); /* release cleared status before transfer */ 1872 } 1873 1874 ret = dsi_cmds2buf_tx(msm_host, msg); 1875 if (ret < msg->tx_len) { 1876 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 1877 return ret; 1878 } 1879 1880 /* 1881 * once cmd_dma_done interrupt received, 1882 * return data from client is ready and stored 1883 * at RDBK_DATA register already 1884 * since rx fifo is 16 bytes, dcs header is kept at first loop, 1885 * after that dcs header lost during shift into registers 1886 */ 1887 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 1888 1889 if (dlen <= 0) 1890 return 0; 1891 1892 if (short_response) 1893 break; 1894 1895 if (rlen <= data_byte) { 1896 diff = data_byte - rlen; 1897 end = 1; 1898 } else { 1899 diff = 0; 1900 rlen -= data_byte; 1901 } 1902 1903 if (!end) { 1904 dlen -= 2; /* 2 crc */ 1905 dlen -= diff; 1906 buf += dlen; /* next start position */ 1907 data_byte = 14; /* NOT first read */ 1908 if (rlen < data_byte) 1909 pkt_size += rlen; 1910 else 1911 pkt_size += data_byte; 1912 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 1913 } 1914 } 1915 1916 /* 1917 * For single Long read, if the requested rlen < 10, 1918 * we need to shift the start position of rx 1919 * data buffer to skip the bytes which are not 1920 * updated. 1921 */ 1922 if (pkt_size < 10 && !short_response) 1923 buf = msm_host->rx_buf + (10 - rlen); 1924 else 1925 buf = msm_host->rx_buf; 1926 1927 cmd = buf[0]; 1928 switch (cmd) { 1929 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1930 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 1931 ret = 0; 1932 break; 1933 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 1934 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1935 ret = dsi_short_read1_resp(buf, msg); 1936 break; 1937 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 1938 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1939 ret = dsi_short_read2_resp(buf, msg); 1940 break; 1941 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 1942 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 1943 ret = dsi_long_read_resp(buf, msg); 1944 break; 1945 default: 1946 pr_warn("%s:Invalid response cmd\n", __func__); 1947 ret = 0; 1948 } 1949 1950 return ret; 1951 } 1952 1953 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, 1954 u32 len) 1955 { 1956 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1957 1958 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); 1959 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 1960 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 1961 1962 /* Make sure trigger happens */ 1963 wmb(); 1964 } 1965 1966 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, 1967 struct msm_dsi_pll *src_pll) 1968 { 1969 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1970 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1971 struct clk *byte_clk_provider, *pixel_clk_provider; 1972 int ret; 1973 1974 ret = msm_dsi_pll_get_clk_provider(src_pll, 1975 &byte_clk_provider, &pixel_clk_provider); 1976 if (ret) { 1977 pr_info("%s: can't get provider from pll, don't set parent\n", 1978 __func__); 1979 return 0; 1980 } 1981 1982 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider); 1983 if (ret) { 1984 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n", 1985 __func__, ret); 1986 goto exit; 1987 } 1988 1989 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider); 1990 if (ret) { 1991 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n", 1992 __func__, ret); 1993 goto exit; 1994 } 1995 1996 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) { 1997 ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider); 1998 if (ret) { 1999 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n", 2000 __func__, ret); 2001 goto exit; 2002 } 2003 2004 ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider); 2005 if (ret) { 2006 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n", 2007 __func__, ret); 2008 goto exit; 2009 } 2010 } 2011 2012 exit: 2013 return ret; 2014 } 2015 2016 int msm_dsi_host_enable(struct mipi_dsi_host *host) 2017 { 2018 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2019 2020 dsi_op_mode_config(msm_host, 2021 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 2022 2023 /* TODO: clock should be turned off for command mode, 2024 * and only turned on before MDP START. 2025 * This part of code should be enabled once mdp driver support it. 2026 */ 2027 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) 2028 dsi_clk_ctrl(msm_host, 0); */ 2029 2030 return 0; 2031 } 2032 2033 int msm_dsi_host_disable(struct mipi_dsi_host *host) 2034 { 2035 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2036 2037 dsi_op_mode_config(msm_host, 2038 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 2039 2040 /* Since we have disabled INTF, the video engine won't stop so that 2041 * the cmd engine will be blocked. 2042 * Reset to disable video engine so that we can send off cmd. 2043 */ 2044 dsi_sw_reset(msm_host); 2045 2046 return 0; 2047 } 2048 2049 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) 2050 { 2051 enum sfpb_ahb_arb_master_port_en en; 2052 2053 if (!msm_host->sfpb) 2054 return; 2055 2056 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; 2057 2058 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, 2059 SFPB_GPREG_MASTER_PORT_EN__MASK, 2060 SFPB_GPREG_MASTER_PORT_EN(en)); 2061 } 2062 2063 int msm_dsi_host_power_on(struct mipi_dsi_host *host) 2064 { 2065 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2066 u32 clk_pre = 0, clk_post = 0; 2067 int ret = 0; 2068 2069 mutex_lock(&msm_host->dev_mutex); 2070 if (msm_host->power_on) { 2071 DBG("dsi host already on"); 2072 goto unlock_ret; 2073 } 2074 2075 msm_dsi_sfpb_config(msm_host, true); 2076 2077 ret = dsi_calc_clk_rate(msm_host); 2078 if (ret) { 2079 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 2080 goto unlock_ret; 2081 } 2082 2083 ret = dsi_host_regulator_enable(msm_host); 2084 if (ret) { 2085 pr_err("%s:Failed to enable vregs.ret=%d\n", 2086 __func__, ret); 2087 goto unlock_ret; 2088 } 2089 2090 ret = dsi_bus_clk_enable(msm_host); 2091 if (ret) { 2092 pr_err("%s: failed to enable bus clocks, %d\n", __func__, ret); 2093 goto fail_disable_reg; 2094 } 2095 2096 dsi_phy_sw_reset(msm_host); 2097 ret = msm_dsi_manager_phy_enable(msm_host->id, 2098 msm_host->byte_clk_rate * 8, 2099 msm_host->esc_clk_rate, 2100 &clk_pre, &clk_post); 2101 dsi_bus_clk_disable(msm_host); 2102 if (ret) { 2103 pr_err("%s: failed to enable phy, %d\n", __func__, ret); 2104 goto fail_disable_reg; 2105 } 2106 2107 ret = dsi_clk_ctrl(msm_host, 1); 2108 if (ret) { 2109 pr_err("%s: failed to enable clocks. ret=%d\n", __func__, ret); 2110 goto fail_disable_reg; 2111 } 2112 2113 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); 2114 if (ret) { 2115 pr_err("%s: failed to set pinctrl default state, %d\n", 2116 __func__, ret); 2117 goto fail_disable_clk; 2118 } 2119 2120 dsi_timing_setup(msm_host); 2121 dsi_sw_reset(msm_host); 2122 dsi_ctrl_config(msm_host, true, clk_pre, clk_post); 2123 2124 if (msm_host->disp_en_gpio) 2125 gpiod_set_value(msm_host->disp_en_gpio, 1); 2126 2127 msm_host->power_on = true; 2128 mutex_unlock(&msm_host->dev_mutex); 2129 2130 return 0; 2131 2132 fail_disable_clk: 2133 dsi_clk_ctrl(msm_host, 0); 2134 fail_disable_reg: 2135 dsi_host_regulator_disable(msm_host); 2136 unlock_ret: 2137 mutex_unlock(&msm_host->dev_mutex); 2138 return ret; 2139 } 2140 2141 int msm_dsi_host_power_off(struct mipi_dsi_host *host) 2142 { 2143 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2144 2145 mutex_lock(&msm_host->dev_mutex); 2146 if (!msm_host->power_on) { 2147 DBG("dsi host already off"); 2148 goto unlock_ret; 2149 } 2150 2151 dsi_ctrl_config(msm_host, false, 0, 0); 2152 2153 if (msm_host->disp_en_gpio) 2154 gpiod_set_value(msm_host->disp_en_gpio, 0); 2155 2156 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); 2157 2158 msm_dsi_manager_phy_disable(msm_host->id); 2159 2160 dsi_clk_ctrl(msm_host, 0); 2161 2162 dsi_host_regulator_disable(msm_host); 2163 2164 msm_dsi_sfpb_config(msm_host, false); 2165 2166 DBG("-"); 2167 2168 msm_host->power_on = false; 2169 2170 unlock_ret: 2171 mutex_unlock(&msm_host->dev_mutex); 2172 return 0; 2173 } 2174 2175 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 2176 struct drm_display_mode *mode) 2177 { 2178 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2179 2180 if (msm_host->mode) { 2181 drm_mode_destroy(msm_host->dev, msm_host->mode); 2182 msm_host->mode = NULL; 2183 } 2184 2185 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 2186 if (IS_ERR(msm_host->mode)) { 2187 pr_err("%s: cannot duplicate mode\n", __func__); 2188 return PTR_ERR(msm_host->mode); 2189 } 2190 2191 return 0; 2192 } 2193 2194 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host, 2195 unsigned long *panel_flags) 2196 { 2197 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2198 struct drm_panel *panel; 2199 2200 panel = of_drm_find_panel(msm_host->device_node); 2201 if (panel_flags) 2202 *panel_flags = msm_host->mode_flags; 2203 2204 return panel; 2205 } 2206 2207 struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host) 2208 { 2209 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2210 2211 return of_drm_find_bridge(msm_host->device_node); 2212 } 2213