1 /* 2 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/gpio.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/interrupt.h> 20 #include <linux/of_device.h> 21 #include <linux/of_gpio.h> 22 #include <linux/of_irq.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/of_graph.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/spinlock.h> 27 #include <video/mipi_display.h> 28 29 #include "dsi.h" 30 #include "dsi.xml.h" 31 #include "dsi_cfg.h" 32 33 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 34 { 35 u32 ver; 36 u32 ver_6g; 37 38 if (!major || !minor) 39 return -EINVAL; 40 41 /* From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 42 * makes all other registers 4-byte shifted down. 43 */ 44 ver_6g = msm_readl(base + REG_DSI_6G_HW_VERSION); 45 if (ver_6g == 0) { 46 ver = msm_readl(base + REG_DSI_VERSION); 47 ver = FIELD(ver, DSI_VERSION_MAJOR); 48 if (ver <= MSM_DSI_VER_MAJOR_V2) { 49 /* old versions */ 50 *major = ver; 51 *minor = 0; 52 return 0; 53 } else { 54 return -EINVAL; 55 } 56 } else { 57 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 58 ver = FIELD(ver, DSI_VERSION_MAJOR); 59 if (ver == MSM_DSI_VER_MAJOR_6G) { 60 /* 6G version */ 61 *major = ver; 62 *minor = ver_6g; 63 return 0; 64 } else { 65 return -EINVAL; 66 } 67 } 68 } 69 70 #define DSI_ERR_STATE_ACK 0x0000 71 #define DSI_ERR_STATE_TIMEOUT 0x0001 72 #define DSI_ERR_STATE_DLN0_PHY 0x0002 73 #define DSI_ERR_STATE_FIFO 0x0004 74 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 75 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 76 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 77 78 #define DSI_CLK_CTRL_ENABLE_CLKS \ 79 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 80 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 81 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 82 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 83 84 struct msm_dsi_host { 85 struct mipi_dsi_host base; 86 87 struct platform_device *pdev; 88 struct drm_device *dev; 89 90 int id; 91 92 void __iomem *ctrl_base; 93 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; 94 struct clk *mdp_core_clk; 95 struct clk *ahb_clk; 96 struct clk *axi_clk; 97 struct clk *mmss_misc_ahb_clk; 98 struct clk *byte_clk; 99 struct clk *esc_clk; 100 struct clk *pixel_clk; 101 struct clk *byte_clk_src; 102 struct clk *pixel_clk_src; 103 104 u32 byte_clk_rate; 105 106 struct gpio_desc *disp_en_gpio; 107 struct gpio_desc *te_gpio; 108 109 const struct msm_dsi_cfg_handler *cfg_hnd; 110 111 struct completion dma_comp; 112 struct completion video_comp; 113 struct mutex dev_mutex; 114 struct mutex cmd_mutex; 115 struct mutex clk_mutex; 116 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 117 118 u32 err_work_state; 119 struct work_struct err_work; 120 struct workqueue_struct *workqueue; 121 122 struct drm_gem_object *tx_gem_obj; 123 u8 *rx_buf; 124 125 struct drm_display_mode *mode; 126 127 /* connected device info */ 128 struct device_node *device_node; 129 unsigned int channel; 130 unsigned int lanes; 131 enum mipi_dsi_pixel_format format; 132 unsigned long mode_flags; 133 134 u32 dma_cmd_ctrl_restore; 135 136 bool registered; 137 bool power_on; 138 int irq; 139 }; 140 141 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt) 142 { 143 switch (fmt) { 144 case MIPI_DSI_FMT_RGB565: return 16; 145 case MIPI_DSI_FMT_RGB666_PACKED: return 18; 146 case MIPI_DSI_FMT_RGB666: 147 case MIPI_DSI_FMT_RGB888: 148 default: return 24; 149 } 150 } 151 152 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 153 { 154 return msm_readl(msm_host->ctrl_base + reg); 155 } 156 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 157 { 158 msm_writel(data, msm_host->ctrl_base + reg); 159 } 160 161 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host); 162 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host); 163 164 static const struct msm_dsi_cfg_handler *dsi_get_config( 165 struct msm_dsi_host *msm_host) 166 { 167 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 168 struct regulator *gdsc_reg; 169 int ret; 170 u32 major = 0, minor = 0; 171 172 gdsc_reg = regulator_get(&msm_host->pdev->dev, "gdsc"); 173 if (IS_ERR(gdsc_reg)) { 174 pr_err("%s: cannot get gdsc\n", __func__); 175 goto exit; 176 } 177 ret = regulator_enable(gdsc_reg); 178 if (ret) { 179 pr_err("%s: unable to enable gdsc\n", __func__); 180 goto put_gdsc; 181 } 182 ret = clk_prepare_enable(msm_host->ahb_clk); 183 if (ret) { 184 pr_err("%s: unable to enable ahb_clk\n", __func__); 185 goto disable_gdsc; 186 } 187 188 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 189 if (ret) { 190 pr_err("%s: Invalid version\n", __func__); 191 goto disable_clks; 192 } 193 194 cfg_hnd = msm_dsi_cfg_get(major, minor); 195 196 DBG("%s: Version %x:%x\n", __func__, major, minor); 197 198 disable_clks: 199 clk_disable_unprepare(msm_host->ahb_clk); 200 disable_gdsc: 201 regulator_disable(gdsc_reg); 202 put_gdsc: 203 regulator_put(gdsc_reg); 204 exit: 205 return cfg_hnd; 206 } 207 208 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 209 { 210 return container_of(host, struct msm_dsi_host, base); 211 } 212 213 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host) 214 { 215 struct regulator_bulk_data *s = msm_host->supplies; 216 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 217 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 218 int i; 219 220 DBG(""); 221 for (i = num - 1; i >= 0; i--) 222 if (regs[i].disable_load >= 0) 223 regulator_set_load(s[i].consumer, 224 regs[i].disable_load); 225 226 regulator_bulk_disable(num, s); 227 } 228 229 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host) 230 { 231 struct regulator_bulk_data *s = msm_host->supplies; 232 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 233 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 234 int ret, i; 235 236 DBG(""); 237 for (i = 0; i < num; i++) { 238 if (regs[i].enable_load >= 0) { 239 ret = regulator_set_load(s[i].consumer, 240 regs[i].enable_load); 241 if (ret < 0) { 242 pr_err("regulator %d set op mode failed, %d\n", 243 i, ret); 244 goto fail; 245 } 246 } 247 } 248 249 ret = regulator_bulk_enable(num, s); 250 if (ret < 0) { 251 pr_err("regulator enable failed, %d\n", ret); 252 goto fail; 253 } 254 255 return 0; 256 257 fail: 258 for (i--; i >= 0; i--) 259 regulator_set_load(s[i].consumer, regs[i].disable_load); 260 return ret; 261 } 262 263 static int dsi_regulator_init(struct msm_dsi_host *msm_host) 264 { 265 struct regulator_bulk_data *s = msm_host->supplies; 266 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 267 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 268 int i, ret; 269 270 for (i = 0; i < num; i++) 271 s[i].supply = regs[i].name; 272 273 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s); 274 if (ret < 0) { 275 pr_err("%s: failed to init regulator, ret=%d\n", 276 __func__, ret); 277 return ret; 278 } 279 280 for (i = 0; i < num; i++) { 281 if ((regs[i].min_voltage >= 0) && (regs[i].max_voltage >= 0)) { 282 ret = regulator_set_voltage(s[i].consumer, 283 regs[i].min_voltage, regs[i].max_voltage); 284 if (ret < 0) { 285 pr_err("regulator %d set voltage failed, %d\n", 286 i, ret); 287 return ret; 288 } 289 } 290 } 291 292 return 0; 293 } 294 295 static int dsi_clk_init(struct msm_dsi_host *msm_host) 296 { 297 struct device *dev = &msm_host->pdev->dev; 298 int ret = 0; 299 300 msm_host->mdp_core_clk = devm_clk_get(dev, "mdp_core_clk"); 301 if (IS_ERR(msm_host->mdp_core_clk)) { 302 ret = PTR_ERR(msm_host->mdp_core_clk); 303 pr_err("%s: Unable to get mdp core clk. ret=%d\n", 304 __func__, ret); 305 goto exit; 306 } 307 308 msm_host->ahb_clk = devm_clk_get(dev, "iface_clk"); 309 if (IS_ERR(msm_host->ahb_clk)) { 310 ret = PTR_ERR(msm_host->ahb_clk); 311 pr_err("%s: Unable to get mdss ahb clk. ret=%d\n", 312 __func__, ret); 313 goto exit; 314 } 315 316 msm_host->axi_clk = devm_clk_get(dev, "bus_clk"); 317 if (IS_ERR(msm_host->axi_clk)) { 318 ret = PTR_ERR(msm_host->axi_clk); 319 pr_err("%s: Unable to get axi bus clk. ret=%d\n", 320 __func__, ret); 321 goto exit; 322 } 323 324 msm_host->mmss_misc_ahb_clk = devm_clk_get(dev, "core_mmss_clk"); 325 if (IS_ERR(msm_host->mmss_misc_ahb_clk)) { 326 ret = PTR_ERR(msm_host->mmss_misc_ahb_clk); 327 pr_err("%s: Unable to get mmss misc ahb clk. ret=%d\n", 328 __func__, ret); 329 goto exit; 330 } 331 332 msm_host->byte_clk = devm_clk_get(dev, "byte_clk"); 333 if (IS_ERR(msm_host->byte_clk)) { 334 ret = PTR_ERR(msm_host->byte_clk); 335 pr_err("%s: can't find dsi_byte_clk. ret=%d\n", 336 __func__, ret); 337 msm_host->byte_clk = NULL; 338 goto exit; 339 } 340 341 msm_host->pixel_clk = devm_clk_get(dev, "pixel_clk"); 342 if (IS_ERR(msm_host->pixel_clk)) { 343 ret = PTR_ERR(msm_host->pixel_clk); 344 pr_err("%s: can't find dsi_pixel_clk. ret=%d\n", 345 __func__, ret); 346 msm_host->pixel_clk = NULL; 347 goto exit; 348 } 349 350 msm_host->esc_clk = devm_clk_get(dev, "core_clk"); 351 if (IS_ERR(msm_host->esc_clk)) { 352 ret = PTR_ERR(msm_host->esc_clk); 353 pr_err("%s: can't find dsi_esc_clk. ret=%d\n", 354 __func__, ret); 355 msm_host->esc_clk = NULL; 356 goto exit; 357 } 358 359 msm_host->byte_clk_src = devm_clk_get(dev, "byte_clk_src"); 360 if (IS_ERR(msm_host->byte_clk_src)) { 361 ret = PTR_ERR(msm_host->byte_clk_src); 362 pr_err("%s: can't find byte_clk_src. ret=%d\n", __func__, ret); 363 msm_host->byte_clk_src = NULL; 364 goto exit; 365 } 366 367 msm_host->pixel_clk_src = devm_clk_get(dev, "pixel_clk_src"); 368 if (IS_ERR(msm_host->pixel_clk_src)) { 369 ret = PTR_ERR(msm_host->pixel_clk_src); 370 pr_err("%s: can't find pixel_clk_src. ret=%d\n", __func__, ret); 371 msm_host->pixel_clk_src = NULL; 372 goto exit; 373 } 374 375 exit: 376 return ret; 377 } 378 379 static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host) 380 { 381 int ret; 382 383 DBG("id=%d", msm_host->id); 384 385 ret = clk_prepare_enable(msm_host->mdp_core_clk); 386 if (ret) { 387 pr_err("%s: failed to enable mdp_core_clock, %d\n", 388 __func__, ret); 389 goto core_clk_err; 390 } 391 392 ret = clk_prepare_enable(msm_host->ahb_clk); 393 if (ret) { 394 pr_err("%s: failed to enable ahb clock, %d\n", __func__, ret); 395 goto ahb_clk_err; 396 } 397 398 ret = clk_prepare_enable(msm_host->axi_clk); 399 if (ret) { 400 pr_err("%s: failed to enable ahb clock, %d\n", __func__, ret); 401 goto axi_clk_err; 402 } 403 404 ret = clk_prepare_enable(msm_host->mmss_misc_ahb_clk); 405 if (ret) { 406 pr_err("%s: failed to enable mmss misc ahb clk, %d\n", 407 __func__, ret); 408 goto misc_ahb_clk_err; 409 } 410 411 return 0; 412 413 misc_ahb_clk_err: 414 clk_disable_unprepare(msm_host->axi_clk); 415 axi_clk_err: 416 clk_disable_unprepare(msm_host->ahb_clk); 417 ahb_clk_err: 418 clk_disable_unprepare(msm_host->mdp_core_clk); 419 core_clk_err: 420 return ret; 421 } 422 423 static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host) 424 { 425 DBG(""); 426 clk_disable_unprepare(msm_host->mmss_misc_ahb_clk); 427 clk_disable_unprepare(msm_host->axi_clk); 428 clk_disable_unprepare(msm_host->ahb_clk); 429 clk_disable_unprepare(msm_host->mdp_core_clk); 430 } 431 432 static int dsi_link_clk_enable(struct msm_dsi_host *msm_host) 433 { 434 int ret; 435 436 DBG("Set clk rates: pclk=%d, byteclk=%d", 437 msm_host->mode->clock, msm_host->byte_clk_rate); 438 439 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 440 if (ret) { 441 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 442 goto error; 443 } 444 445 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000); 446 if (ret) { 447 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 448 goto error; 449 } 450 451 ret = clk_prepare_enable(msm_host->esc_clk); 452 if (ret) { 453 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 454 goto error; 455 } 456 457 ret = clk_prepare_enable(msm_host->byte_clk); 458 if (ret) { 459 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 460 goto byte_clk_err; 461 } 462 463 ret = clk_prepare_enable(msm_host->pixel_clk); 464 if (ret) { 465 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 466 goto pixel_clk_err; 467 } 468 469 return 0; 470 471 pixel_clk_err: 472 clk_disable_unprepare(msm_host->byte_clk); 473 byte_clk_err: 474 clk_disable_unprepare(msm_host->esc_clk); 475 error: 476 return ret; 477 } 478 479 static void dsi_link_clk_disable(struct msm_dsi_host *msm_host) 480 { 481 clk_disable_unprepare(msm_host->esc_clk); 482 clk_disable_unprepare(msm_host->pixel_clk); 483 clk_disable_unprepare(msm_host->byte_clk); 484 } 485 486 static int dsi_clk_ctrl(struct msm_dsi_host *msm_host, bool enable) 487 { 488 int ret = 0; 489 490 mutex_lock(&msm_host->clk_mutex); 491 if (enable) { 492 ret = dsi_bus_clk_enable(msm_host); 493 if (ret) { 494 pr_err("%s: Can not enable bus clk, %d\n", 495 __func__, ret); 496 goto unlock_ret; 497 } 498 ret = dsi_link_clk_enable(msm_host); 499 if (ret) { 500 pr_err("%s: Can not enable link clk, %d\n", 501 __func__, ret); 502 dsi_bus_clk_disable(msm_host); 503 goto unlock_ret; 504 } 505 } else { 506 dsi_link_clk_disable(msm_host); 507 dsi_bus_clk_disable(msm_host); 508 } 509 510 unlock_ret: 511 mutex_unlock(&msm_host->clk_mutex); 512 return ret; 513 } 514 515 static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host) 516 { 517 struct drm_display_mode *mode = msm_host->mode; 518 u8 lanes = msm_host->lanes; 519 u32 bpp = dsi_get_bpp(msm_host->format); 520 u32 pclk_rate; 521 522 if (!mode) { 523 pr_err("%s: mode not set\n", __func__); 524 return -EINVAL; 525 } 526 527 pclk_rate = mode->clock * 1000; 528 if (lanes > 0) { 529 msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes); 530 } else { 531 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 532 msm_host->byte_clk_rate = (pclk_rate * bpp) / 8; 533 } 534 535 DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate); 536 537 return 0; 538 } 539 540 static void dsi_phy_sw_reset(struct msm_dsi_host *msm_host) 541 { 542 DBG(""); 543 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 544 /* Make sure fully reset */ 545 wmb(); 546 udelay(1000); 547 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 548 udelay(100); 549 } 550 551 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 552 { 553 u32 intr; 554 unsigned long flags; 555 556 spin_lock_irqsave(&msm_host->intr_lock, flags); 557 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 558 559 if (enable) 560 intr |= mask; 561 else 562 intr &= ~mask; 563 564 DBG("intr=%x enable=%d", intr, enable); 565 566 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 567 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 568 } 569 570 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 571 { 572 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 573 return BURST_MODE; 574 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 575 return NON_BURST_SYNCH_PULSE; 576 577 return NON_BURST_SYNCH_EVENT; 578 } 579 580 static inline enum dsi_vid_dst_format dsi_get_vid_fmt( 581 const enum mipi_dsi_pixel_format mipi_fmt) 582 { 583 switch (mipi_fmt) { 584 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 585 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 586 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 587 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 588 default: return VID_DST_FORMAT_RGB888; 589 } 590 } 591 592 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( 593 const enum mipi_dsi_pixel_format mipi_fmt) 594 { 595 switch (mipi_fmt) { 596 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 597 case MIPI_DSI_FMT_RGB666_PACKED: 598 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666; 599 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 600 default: return CMD_DST_FORMAT_RGB888; 601 } 602 } 603 604 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, 605 u32 clk_pre, u32 clk_post) 606 { 607 u32 flags = msm_host->mode_flags; 608 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 609 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 610 u32 data = 0; 611 612 if (!enable) { 613 dsi_write(msm_host, REG_DSI_CTRL, 0); 614 return; 615 } 616 617 if (flags & MIPI_DSI_MODE_VIDEO) { 618 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 619 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 620 if (flags & MIPI_DSI_MODE_VIDEO_HFP) 621 data |= DSI_VID_CFG0_HFP_POWER_STOP; 622 if (flags & MIPI_DSI_MODE_VIDEO_HBP) 623 data |= DSI_VID_CFG0_HBP_POWER_STOP; 624 if (flags & MIPI_DSI_MODE_VIDEO_HSA) 625 data |= DSI_VID_CFG0_HSA_POWER_STOP; 626 /* Always set low power stop mode for BLLP 627 * to let command engine send packets 628 */ 629 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 630 DSI_VID_CFG0_BLLP_POWER_STOP; 631 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 632 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 633 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 634 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 635 636 /* Do not swap RGB colors */ 637 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 638 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 639 } else { 640 /* Do not swap RGB colors */ 641 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 642 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 643 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 644 645 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 646 DSI_CMD_CFG1_WR_MEM_CONTINUE( 647 MIPI_DCS_WRITE_MEMORY_CONTINUE); 648 /* Always insert DCS command */ 649 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 650 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 651 } 652 653 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 654 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 655 DSI_CMD_DMA_CTRL_LOW_POWER); 656 657 data = 0; 658 /* Always assume dedicated TE pin */ 659 data |= DSI_TRIG_CTRL_TE; 660 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 661 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 662 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 663 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 664 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 665 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 666 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 667 668 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(clk_post) | 669 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(clk_pre); 670 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 671 672 data = 0; 673 if (!(flags & MIPI_DSI_MODE_EOT_PACKET)) 674 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 675 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 676 677 /* allow only ack-err-status to generate interrupt */ 678 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 679 680 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 681 682 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 683 684 data = DSI_CTRL_CLK_EN; 685 686 DBG("lane number=%d", msm_host->lanes); 687 if (msm_host->lanes == 2) { 688 data |= DSI_CTRL_LANE1 | DSI_CTRL_LANE2; 689 /* swap lanes for 2-lane panel for better performance */ 690 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 691 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_1230)); 692 } else { 693 /* Take 4 lanes as default */ 694 data |= DSI_CTRL_LANE0 | DSI_CTRL_LANE1 | DSI_CTRL_LANE2 | 695 DSI_CTRL_LANE3; 696 /* Do not swap lanes for 4-lane panel */ 697 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 698 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_0123)); 699 } 700 701 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 702 dsi_write(msm_host, REG_DSI_LANE_CTRL, 703 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); 704 705 data |= DSI_CTRL_ENABLE; 706 707 dsi_write(msm_host, REG_DSI_CTRL, data); 708 } 709 710 static void dsi_timing_setup(struct msm_dsi_host *msm_host) 711 { 712 struct drm_display_mode *mode = msm_host->mode; 713 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 714 u32 h_total = mode->htotal; 715 u32 v_total = mode->vtotal; 716 u32 hs_end = mode->hsync_end - mode->hsync_start; 717 u32 vs_end = mode->vsync_end - mode->vsync_start; 718 u32 ha_start = h_total - mode->hsync_start; 719 u32 ha_end = ha_start + mode->hdisplay; 720 u32 va_start = v_total - mode->vsync_start; 721 u32 va_end = va_start + mode->vdisplay; 722 u32 wc; 723 724 DBG(""); 725 726 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 727 dsi_write(msm_host, REG_DSI_ACTIVE_H, 728 DSI_ACTIVE_H_START(ha_start) | 729 DSI_ACTIVE_H_END(ha_end)); 730 dsi_write(msm_host, REG_DSI_ACTIVE_V, 731 DSI_ACTIVE_V_START(va_start) | 732 DSI_ACTIVE_V_END(va_end)); 733 dsi_write(msm_host, REG_DSI_TOTAL, 734 DSI_TOTAL_H_TOTAL(h_total - 1) | 735 DSI_TOTAL_V_TOTAL(v_total - 1)); 736 737 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 738 DSI_ACTIVE_HSYNC_START(hs_start) | 739 DSI_ACTIVE_HSYNC_END(hs_end)); 740 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 741 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 742 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 743 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 744 } else { /* command mode */ 745 /* image data and 1 byte write_memory_start cmd */ 746 wc = mode->hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; 747 748 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL, 749 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) | 750 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL( 751 msm_host->channel) | 752 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE( 753 MIPI_DSI_DCS_LONG_WRITE)); 754 755 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL, 756 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(mode->hdisplay) | 757 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay)); 758 } 759 } 760 761 static void dsi_sw_reset(struct msm_dsi_host *msm_host) 762 { 763 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 764 wmb(); /* clocks need to be enabled before reset */ 765 766 dsi_write(msm_host, REG_DSI_RESET, 1); 767 wmb(); /* make sure reset happen */ 768 dsi_write(msm_host, REG_DSI_RESET, 0); 769 } 770 771 static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 772 bool video_mode, bool enable) 773 { 774 u32 dsi_ctrl; 775 776 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 777 778 if (!enable) { 779 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 780 DSI_CTRL_CMD_MODE_EN); 781 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 782 DSI_IRQ_MASK_VIDEO_DONE, 0); 783 } else { 784 if (video_mode) { 785 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 786 } else { /* command mode */ 787 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 788 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 789 } 790 dsi_ctrl |= DSI_CTRL_ENABLE; 791 } 792 793 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 794 } 795 796 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 797 { 798 u32 data; 799 800 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 801 802 if (mode == 0) 803 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 804 else 805 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 806 807 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 808 } 809 810 static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 811 { 812 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 813 814 reinit_completion(&msm_host->video_comp); 815 816 wait_for_completion_timeout(&msm_host->video_comp, 817 msecs_to_jiffies(70)); 818 819 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 820 } 821 822 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 823 { 824 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 825 return; 826 827 if (msm_host->power_on) { 828 dsi_wait4video_done(msm_host); 829 /* delay 4 ms to skip BLLP */ 830 usleep_range(2000, 4000); 831 } 832 } 833 834 /* dsi_cmd */ 835 static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size) 836 { 837 struct drm_device *dev = msm_host->dev; 838 int ret; 839 u32 iova; 840 841 mutex_lock(&dev->struct_mutex); 842 msm_host->tx_gem_obj = msm_gem_new(dev, size, MSM_BO_UNCACHED); 843 if (IS_ERR(msm_host->tx_gem_obj)) { 844 ret = PTR_ERR(msm_host->tx_gem_obj); 845 pr_err("%s: failed to allocate gem, %d\n", __func__, ret); 846 msm_host->tx_gem_obj = NULL; 847 mutex_unlock(&dev->struct_mutex); 848 return ret; 849 } 850 851 ret = msm_gem_get_iova_locked(msm_host->tx_gem_obj, 0, &iova); 852 if (ret) { 853 pr_err("%s: failed to get iova, %d\n", __func__, ret); 854 return ret; 855 } 856 mutex_unlock(&dev->struct_mutex); 857 858 if (iova & 0x07) { 859 pr_err("%s: buf NOT 8 bytes aligned\n", __func__); 860 return -EINVAL; 861 } 862 863 return 0; 864 } 865 866 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host) 867 { 868 struct drm_device *dev = msm_host->dev; 869 870 if (msm_host->tx_gem_obj) { 871 msm_gem_put_iova(msm_host->tx_gem_obj, 0); 872 mutex_lock(&dev->struct_mutex); 873 msm_gem_free_object(msm_host->tx_gem_obj); 874 msm_host->tx_gem_obj = NULL; 875 mutex_unlock(&dev->struct_mutex); 876 } 877 } 878 879 /* 880 * prepare cmd buffer to be txed 881 */ 882 static int dsi_cmd_dma_add(struct drm_gem_object *tx_gem, 883 const struct mipi_dsi_msg *msg) 884 { 885 struct mipi_dsi_packet packet; 886 int len; 887 int ret; 888 u8 *data; 889 890 ret = mipi_dsi_create_packet(&packet, msg); 891 if (ret) { 892 pr_err("%s: create packet failed, %d\n", __func__, ret); 893 return ret; 894 } 895 len = (packet.size + 3) & (~0x3); 896 897 if (len > tx_gem->size) { 898 pr_err("%s: packet size is too big\n", __func__); 899 return -EINVAL; 900 } 901 902 data = msm_gem_vaddr(tx_gem); 903 904 if (IS_ERR(data)) { 905 ret = PTR_ERR(data); 906 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 907 return ret; 908 } 909 910 /* MSM specific command format in memory */ 911 data[0] = packet.header[1]; 912 data[1] = packet.header[2]; 913 data[2] = packet.header[0]; 914 data[3] = BIT(7); /* Last packet */ 915 if (mipi_dsi_packet_format_is_long(msg->type)) 916 data[3] |= BIT(6); 917 if (msg->rx_buf && msg->rx_len) 918 data[3] |= BIT(5); 919 920 /* Long packet */ 921 if (packet.payload && packet.payload_length) 922 memcpy(data + 4, packet.payload, packet.payload_length); 923 924 /* Append 0xff to the end */ 925 if (packet.size < len) 926 memset(data + packet.size, 0xff, len - packet.size); 927 928 return len; 929 } 930 931 /* 932 * dsi_short_read1_resp: 1 parameter 933 */ 934 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 935 { 936 u8 *data = msg->rx_buf; 937 if (data && (msg->rx_len >= 1)) { 938 *data = buf[1]; /* strip out dcs type */ 939 return 1; 940 } else { 941 pr_err("%s: read data does not match with rx_buf len %zu\n", 942 __func__, msg->rx_len); 943 return -EINVAL; 944 } 945 } 946 947 /* 948 * dsi_short_read2_resp: 2 parameter 949 */ 950 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 951 { 952 u8 *data = msg->rx_buf; 953 if (data && (msg->rx_len >= 2)) { 954 data[0] = buf[1]; /* strip out dcs type */ 955 data[1] = buf[2]; 956 return 2; 957 } else { 958 pr_err("%s: read data does not match with rx_buf len %zu\n", 959 __func__, msg->rx_len); 960 return -EINVAL; 961 } 962 } 963 964 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 965 { 966 /* strip out 4 byte dcs header */ 967 if (msg->rx_buf && msg->rx_len) 968 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 969 970 return msg->rx_len; 971 } 972 973 974 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 975 { 976 int ret; 977 u32 iova; 978 bool triggered; 979 980 ret = msm_gem_get_iova(msm_host->tx_gem_obj, 0, &iova); 981 if (ret) { 982 pr_err("%s: failed to get iova: %d\n", __func__, ret); 983 return ret; 984 } 985 986 reinit_completion(&msm_host->dma_comp); 987 988 dsi_wait4video_eng_busy(msm_host); 989 990 triggered = msm_dsi_manager_cmd_xfer_trigger( 991 msm_host->id, iova, len); 992 if (triggered) { 993 ret = wait_for_completion_timeout(&msm_host->dma_comp, 994 msecs_to_jiffies(200)); 995 DBG("ret=%d", ret); 996 if (ret == 0) 997 ret = -ETIMEDOUT; 998 else 999 ret = len; 1000 } else 1001 ret = len; 1002 1003 return ret; 1004 } 1005 1006 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1007 u8 *buf, int rx_byte, int pkt_size) 1008 { 1009 u32 *lp, *temp, data; 1010 int i, j = 0, cnt; 1011 u32 read_cnt; 1012 u8 reg[16]; 1013 int repeated_bytes = 0; 1014 int buf_offset = buf - msm_host->rx_buf; 1015 1016 lp = (u32 *)buf; 1017 temp = (u32 *)reg; 1018 cnt = (rx_byte + 3) >> 2; 1019 if (cnt > 4) 1020 cnt = 4; /* 4 x 32 bits registers only */ 1021 1022 if (rx_byte == 4) 1023 read_cnt = 4; 1024 else 1025 read_cnt = pkt_size + 6; 1026 1027 /* 1028 * In case of multiple reads from the panel, after the first read, there 1029 * is possibility that there are some bytes in the payload repeating in 1030 * the RDBK_DATA registers. Since we read all the parameters from the 1031 * panel right from the first byte for every pass. We need to skip the 1032 * repeating bytes and then append the new parameters to the rx buffer. 1033 */ 1034 if (read_cnt > 16) { 1035 int bytes_shifted; 1036 /* Any data more than 16 bytes will be shifted out. 1037 * The temp read buffer should already contain these bytes. 1038 * The remaining bytes in read buffer are the repeated bytes. 1039 */ 1040 bytes_shifted = read_cnt - 16; 1041 repeated_bytes = buf_offset - bytes_shifted; 1042 } 1043 1044 for (i = cnt - 1; i >= 0; i--) { 1045 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1046 *temp++ = ntohl(data); /* to host byte order */ 1047 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1048 } 1049 1050 for (i = repeated_bytes; i < 16; i++) 1051 buf[j++] = reg[i]; 1052 1053 return j; 1054 } 1055 1056 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1057 const struct mipi_dsi_msg *msg) 1058 { 1059 int len, ret; 1060 int bllp_len = msm_host->mode->hdisplay * 1061 dsi_get_bpp(msm_host->format) / 8; 1062 1063 len = dsi_cmd_dma_add(msm_host->tx_gem_obj, msg); 1064 if (!len) { 1065 pr_err("%s: failed to add cmd type = 0x%x\n", 1066 __func__, msg->type); 1067 return -EINVAL; 1068 } 1069 1070 /* for video mode, do not send cmds more than 1071 * one pixel line, since it only transmit it 1072 * during BLLP. 1073 */ 1074 /* TODO: if the command is sent in LP mode, the bit rate is only 1075 * half of esc clk rate. In this case, if the video is already 1076 * actively streaming, we need to check more carefully if the 1077 * command can be fit into one BLLP. 1078 */ 1079 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1080 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1081 __func__, len); 1082 return -EINVAL; 1083 } 1084 1085 ret = dsi_cmd_dma_tx(msm_host, len); 1086 if (ret < len) { 1087 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n", 1088 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len); 1089 return -ECOMM; 1090 } 1091 1092 return len; 1093 } 1094 1095 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host) 1096 { 1097 u32 data0, data1; 1098 1099 data0 = dsi_read(msm_host, REG_DSI_CTRL); 1100 data1 = data0; 1101 data1 &= ~DSI_CTRL_ENABLE; 1102 dsi_write(msm_host, REG_DSI_CTRL, data1); 1103 /* 1104 * dsi controller need to be disabled before 1105 * clocks turned on 1106 */ 1107 wmb(); 1108 1109 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1110 wmb(); /* make sure clocks enabled */ 1111 1112 /* dsi controller can only be reset while clocks are running */ 1113 dsi_write(msm_host, REG_DSI_RESET, 1); 1114 wmb(); /* make sure reset happen */ 1115 dsi_write(msm_host, REG_DSI_RESET, 0); 1116 wmb(); /* controller out of reset */ 1117 dsi_write(msm_host, REG_DSI_CTRL, data0); 1118 wmb(); /* make sure dsi controller enabled again */ 1119 } 1120 1121 static void dsi_err_worker(struct work_struct *work) 1122 { 1123 struct msm_dsi_host *msm_host = 1124 container_of(work, struct msm_dsi_host, err_work); 1125 u32 status = msm_host->err_work_state; 1126 1127 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1128 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1129 dsi_sw_reset_restore(msm_host); 1130 1131 /* It is safe to clear here because error irq is disabled. */ 1132 msm_host->err_work_state = 0; 1133 1134 /* enable dsi error interrupt */ 1135 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1136 } 1137 1138 static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1139 { 1140 u32 status; 1141 1142 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1143 1144 if (status) { 1145 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1146 /* Writing of an extra 0 needed to clear error bits */ 1147 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1148 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1149 } 1150 } 1151 1152 static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1153 { 1154 u32 status; 1155 1156 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1157 1158 if (status) { 1159 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1160 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1161 } 1162 } 1163 1164 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1165 { 1166 u32 status; 1167 1168 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1169 1170 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | 1171 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | 1172 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | 1173 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | 1174 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { 1175 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1176 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1177 } 1178 } 1179 1180 static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1181 { 1182 u32 status; 1183 1184 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1185 1186 /* fifo underflow, overflow */ 1187 if (status) { 1188 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1189 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1190 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1191 msm_host->err_work_state |= 1192 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1193 } 1194 } 1195 1196 static void dsi_status(struct msm_dsi_host *msm_host) 1197 { 1198 u32 status; 1199 1200 status = dsi_read(msm_host, REG_DSI_STATUS0); 1201 1202 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1203 dsi_write(msm_host, REG_DSI_STATUS0, status); 1204 msm_host->err_work_state |= 1205 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1206 } 1207 } 1208 1209 static void dsi_clk_status(struct msm_dsi_host *msm_host) 1210 { 1211 u32 status; 1212 1213 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1214 1215 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1216 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1217 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1218 } 1219 } 1220 1221 static void dsi_error(struct msm_dsi_host *msm_host) 1222 { 1223 /* disable dsi error interrupt */ 1224 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1225 1226 dsi_clk_status(msm_host); 1227 dsi_fifo_status(msm_host); 1228 dsi_ack_err_status(msm_host); 1229 dsi_timeout_status(msm_host); 1230 dsi_status(msm_host); 1231 dsi_dln0_phy_err(msm_host); 1232 1233 queue_work(msm_host->workqueue, &msm_host->err_work); 1234 } 1235 1236 static irqreturn_t dsi_host_irq(int irq, void *ptr) 1237 { 1238 struct msm_dsi_host *msm_host = ptr; 1239 u32 isr; 1240 unsigned long flags; 1241 1242 if (!msm_host->ctrl_base) 1243 return IRQ_HANDLED; 1244 1245 spin_lock_irqsave(&msm_host->intr_lock, flags); 1246 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1247 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1248 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1249 1250 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1251 1252 if (isr & DSI_IRQ_ERROR) 1253 dsi_error(msm_host); 1254 1255 if (isr & DSI_IRQ_VIDEO_DONE) 1256 complete(&msm_host->video_comp); 1257 1258 if (isr & DSI_IRQ_CMD_DMA_DONE) 1259 complete(&msm_host->dma_comp); 1260 1261 return IRQ_HANDLED; 1262 } 1263 1264 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, 1265 struct device *panel_device) 1266 { 1267 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device, 1268 "disp-enable", 1269 GPIOD_OUT_LOW); 1270 if (IS_ERR(msm_host->disp_en_gpio)) { 1271 DBG("cannot get disp-enable-gpios %ld", 1272 PTR_ERR(msm_host->disp_en_gpio)); 1273 return PTR_ERR(msm_host->disp_en_gpio); 1274 } 1275 1276 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te", 1277 GPIOD_IN); 1278 if (IS_ERR(msm_host->te_gpio)) { 1279 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); 1280 return PTR_ERR(msm_host->te_gpio); 1281 } 1282 1283 return 0; 1284 } 1285 1286 static int dsi_host_attach(struct mipi_dsi_host *host, 1287 struct mipi_dsi_device *dsi) 1288 { 1289 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1290 int ret; 1291 1292 msm_host->channel = dsi->channel; 1293 msm_host->lanes = dsi->lanes; 1294 msm_host->format = dsi->format; 1295 msm_host->mode_flags = dsi->mode_flags; 1296 1297 WARN_ON(dsi->dev.of_node != msm_host->device_node); 1298 1299 /* Some gpios defined in panel DT need to be controlled by host */ 1300 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); 1301 if (ret) 1302 return ret; 1303 1304 DBG("id=%d", msm_host->id); 1305 if (msm_host->dev) 1306 drm_helper_hpd_irq_event(msm_host->dev); 1307 1308 return 0; 1309 } 1310 1311 static int dsi_host_detach(struct mipi_dsi_host *host, 1312 struct mipi_dsi_device *dsi) 1313 { 1314 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1315 1316 msm_host->device_node = NULL; 1317 1318 DBG("id=%d", msm_host->id); 1319 if (msm_host->dev) 1320 drm_helper_hpd_irq_event(msm_host->dev); 1321 1322 return 0; 1323 } 1324 1325 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1326 const struct mipi_dsi_msg *msg) 1327 { 1328 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1329 int ret; 1330 1331 if (!msg || !msm_host->power_on) 1332 return -EINVAL; 1333 1334 mutex_lock(&msm_host->cmd_mutex); 1335 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1336 mutex_unlock(&msm_host->cmd_mutex); 1337 1338 return ret; 1339 } 1340 1341 static struct mipi_dsi_host_ops dsi_host_ops = { 1342 .attach = dsi_host_attach, 1343 .detach = dsi_host_detach, 1344 .transfer = dsi_host_transfer, 1345 }; 1346 1347 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) 1348 { 1349 struct device *dev = &msm_host->pdev->dev; 1350 struct device_node *np = dev->of_node; 1351 struct device_node *endpoint, *device_node; 1352 int ret; 1353 1354 ret = of_property_read_u32(np, "qcom,dsi-host-index", &msm_host->id); 1355 if (ret) { 1356 dev_err(dev, "%s: host index not specified, ret=%d\n", 1357 __func__, ret); 1358 return ret; 1359 } 1360 1361 /* 1362 * Get the first endpoint node. In our case, dsi has one output port 1363 * to which the panel is connected. Don't return an error if a port 1364 * isn't defined. It's possible that there is nothing connected to 1365 * the dsi output. 1366 */ 1367 endpoint = of_graph_get_next_endpoint(np, NULL); 1368 if (!endpoint) { 1369 dev_dbg(dev, "%s: no endpoint\n", __func__); 1370 return 0; 1371 } 1372 1373 /* Get panel node from the output port's endpoint data */ 1374 device_node = of_graph_get_remote_port_parent(endpoint); 1375 if (!device_node) { 1376 dev_err(dev, "%s: no valid device\n", __func__); 1377 of_node_put(endpoint); 1378 return -ENODEV; 1379 } 1380 1381 of_node_put(endpoint); 1382 of_node_put(device_node); 1383 1384 msm_host->device_node = device_node; 1385 1386 return 0; 1387 } 1388 1389 int msm_dsi_host_init(struct msm_dsi *msm_dsi) 1390 { 1391 struct msm_dsi_host *msm_host = NULL; 1392 struct platform_device *pdev = msm_dsi->pdev; 1393 int ret; 1394 1395 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 1396 if (!msm_host) { 1397 pr_err("%s: FAILED: cannot alloc dsi host\n", 1398 __func__); 1399 ret = -ENOMEM; 1400 goto fail; 1401 } 1402 1403 msm_host->pdev = pdev; 1404 1405 ret = dsi_host_parse_dt(msm_host); 1406 if (ret) { 1407 pr_err("%s: failed to parse dt\n", __func__); 1408 goto fail; 1409 } 1410 1411 ret = dsi_clk_init(msm_host); 1412 if (ret) { 1413 pr_err("%s: unable to initialize dsi clks\n", __func__); 1414 goto fail; 1415 } 1416 1417 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL"); 1418 if (IS_ERR(msm_host->ctrl_base)) { 1419 pr_err("%s: unable to map Dsi ctrl base\n", __func__); 1420 ret = PTR_ERR(msm_host->ctrl_base); 1421 goto fail; 1422 } 1423 1424 msm_host->cfg_hnd = dsi_get_config(msm_host); 1425 if (!msm_host->cfg_hnd) { 1426 ret = -EINVAL; 1427 pr_err("%s: get config failed\n", __func__); 1428 goto fail; 1429 } 1430 1431 /* fixup base address by io offset */ 1432 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset; 1433 1434 ret = dsi_regulator_init(msm_host); 1435 if (ret) { 1436 pr_err("%s: regulator init failed\n", __func__); 1437 goto fail; 1438 } 1439 1440 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 1441 if (!msm_host->rx_buf) { 1442 pr_err("%s: alloc rx temp buf failed\n", __func__); 1443 goto fail; 1444 } 1445 1446 init_completion(&msm_host->dma_comp); 1447 init_completion(&msm_host->video_comp); 1448 mutex_init(&msm_host->dev_mutex); 1449 mutex_init(&msm_host->cmd_mutex); 1450 mutex_init(&msm_host->clk_mutex); 1451 spin_lock_init(&msm_host->intr_lock); 1452 1453 /* setup workqueue */ 1454 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 1455 INIT_WORK(&msm_host->err_work, dsi_err_worker); 1456 1457 msm_dsi->host = &msm_host->base; 1458 msm_dsi->id = msm_host->id; 1459 1460 DBG("Dsi Host %d initialized", msm_host->id); 1461 return 0; 1462 1463 fail: 1464 return ret; 1465 } 1466 1467 void msm_dsi_host_destroy(struct mipi_dsi_host *host) 1468 { 1469 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1470 1471 DBG(""); 1472 dsi_tx_buf_free(msm_host); 1473 if (msm_host->workqueue) { 1474 flush_workqueue(msm_host->workqueue); 1475 destroy_workqueue(msm_host->workqueue); 1476 msm_host->workqueue = NULL; 1477 } 1478 1479 mutex_destroy(&msm_host->clk_mutex); 1480 mutex_destroy(&msm_host->cmd_mutex); 1481 mutex_destroy(&msm_host->dev_mutex); 1482 } 1483 1484 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 1485 struct drm_device *dev) 1486 { 1487 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1488 struct platform_device *pdev = msm_host->pdev; 1489 int ret; 1490 1491 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1492 if (msm_host->irq < 0) { 1493 ret = msm_host->irq; 1494 dev_err(dev->dev, "failed to get irq: %d\n", ret); 1495 return ret; 1496 } 1497 1498 ret = devm_request_irq(&pdev->dev, msm_host->irq, 1499 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1500 "dsi_isr", msm_host); 1501 if (ret < 0) { 1502 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n", 1503 msm_host->irq, ret); 1504 return ret; 1505 } 1506 1507 msm_host->dev = dev; 1508 ret = dsi_tx_buf_alloc(msm_host, SZ_4K); 1509 if (ret) { 1510 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 1511 return ret; 1512 } 1513 1514 return 0; 1515 } 1516 1517 int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer) 1518 { 1519 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1520 int ret; 1521 1522 /* Register mipi dsi host */ 1523 if (!msm_host->registered) { 1524 host->dev = &msm_host->pdev->dev; 1525 host->ops = &dsi_host_ops; 1526 ret = mipi_dsi_host_register(host); 1527 if (ret) 1528 return ret; 1529 1530 msm_host->registered = true; 1531 1532 /* If the panel driver has not been probed after host register, 1533 * we should defer the host's probe. 1534 * It makes sure panel is connected when fbcon detects 1535 * connector status and gets the proper display mode to 1536 * create framebuffer. 1537 * Don't try to defer if there is nothing connected to the dsi 1538 * output 1539 */ 1540 if (check_defer && msm_host->device_node) { 1541 if (!of_drm_find_panel(msm_host->device_node)) 1542 if (!of_drm_find_bridge(msm_host->device_node)) 1543 return -EPROBE_DEFER; 1544 } 1545 } 1546 1547 return 0; 1548 } 1549 1550 void msm_dsi_host_unregister(struct mipi_dsi_host *host) 1551 { 1552 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1553 1554 if (msm_host->registered) { 1555 mipi_dsi_host_unregister(host); 1556 host->dev = NULL; 1557 host->ops = NULL; 1558 msm_host->registered = false; 1559 } 1560 } 1561 1562 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 1563 const struct mipi_dsi_msg *msg) 1564 { 1565 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1566 1567 /* TODO: make sure dsi_cmd_mdp is idle. 1568 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 1569 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 1570 * How to handle the old versions? Wait for mdp cmd done? 1571 */ 1572 1573 /* 1574 * mdss interrupt is generated in mdp core clock domain 1575 * mdp clock need to be enabled to receive dsi interrupt 1576 */ 1577 dsi_clk_ctrl(msm_host, 1); 1578 1579 /* TODO: vote for bus bandwidth */ 1580 1581 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 1582 dsi_set_tx_power_mode(0, msm_host); 1583 1584 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 1585 dsi_write(msm_host, REG_DSI_CTRL, 1586 msm_host->dma_cmd_ctrl_restore | 1587 DSI_CTRL_CMD_MODE_EN | 1588 DSI_CTRL_ENABLE); 1589 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 1590 1591 return 0; 1592 } 1593 1594 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 1595 const struct mipi_dsi_msg *msg) 1596 { 1597 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1598 1599 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 1600 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 1601 1602 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 1603 dsi_set_tx_power_mode(1, msm_host); 1604 1605 /* TODO: unvote for bus bandwidth */ 1606 1607 dsi_clk_ctrl(msm_host, 0); 1608 } 1609 1610 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 1611 const struct mipi_dsi_msg *msg) 1612 { 1613 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1614 1615 return dsi_cmds2buf_tx(msm_host, msg); 1616 } 1617 1618 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 1619 const struct mipi_dsi_msg *msg) 1620 { 1621 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1622 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1623 int data_byte, rx_byte, dlen, end; 1624 int short_response, diff, pkt_size, ret = 0; 1625 char cmd; 1626 int rlen = msg->rx_len; 1627 u8 *buf; 1628 1629 if (rlen <= 2) { 1630 short_response = 1; 1631 pkt_size = rlen; 1632 rx_byte = 4; 1633 } else { 1634 short_response = 0; 1635 data_byte = 10; /* first read */ 1636 if (rlen < data_byte) 1637 pkt_size = rlen; 1638 else 1639 pkt_size = data_byte; 1640 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 1641 } 1642 1643 buf = msm_host->rx_buf; 1644 end = 0; 1645 while (!end) { 1646 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 1647 struct mipi_dsi_msg max_pkt_size_msg = { 1648 .channel = msg->channel, 1649 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 1650 .tx_len = 2, 1651 .tx_buf = tx, 1652 }; 1653 1654 DBG("rlen=%d pkt_size=%d rx_byte=%d", 1655 rlen, pkt_size, rx_byte); 1656 1657 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 1658 if (ret < 2) { 1659 pr_err("%s: Set max pkt size failed, %d\n", 1660 __func__, ret); 1661 return -EINVAL; 1662 } 1663 1664 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 1665 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 1666 /* Clear the RDBK_DATA registers */ 1667 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 1668 DSI_RDBK_DATA_CTRL_CLR); 1669 wmb(); /* make sure the RDBK registers are cleared */ 1670 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 1671 wmb(); /* release cleared status before transfer */ 1672 } 1673 1674 ret = dsi_cmds2buf_tx(msm_host, msg); 1675 if (ret < msg->tx_len) { 1676 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 1677 return ret; 1678 } 1679 1680 /* 1681 * once cmd_dma_done interrupt received, 1682 * return data from client is ready and stored 1683 * at RDBK_DATA register already 1684 * since rx fifo is 16 bytes, dcs header is kept at first loop, 1685 * after that dcs header lost during shift into registers 1686 */ 1687 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 1688 1689 if (dlen <= 0) 1690 return 0; 1691 1692 if (short_response) 1693 break; 1694 1695 if (rlen <= data_byte) { 1696 diff = data_byte - rlen; 1697 end = 1; 1698 } else { 1699 diff = 0; 1700 rlen -= data_byte; 1701 } 1702 1703 if (!end) { 1704 dlen -= 2; /* 2 crc */ 1705 dlen -= diff; 1706 buf += dlen; /* next start position */ 1707 data_byte = 14; /* NOT first read */ 1708 if (rlen < data_byte) 1709 pkt_size += rlen; 1710 else 1711 pkt_size += data_byte; 1712 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 1713 } 1714 } 1715 1716 /* 1717 * For single Long read, if the requested rlen < 10, 1718 * we need to shift the start position of rx 1719 * data buffer to skip the bytes which are not 1720 * updated. 1721 */ 1722 if (pkt_size < 10 && !short_response) 1723 buf = msm_host->rx_buf + (10 - rlen); 1724 else 1725 buf = msm_host->rx_buf; 1726 1727 cmd = buf[0]; 1728 switch (cmd) { 1729 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1730 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 1731 ret = 0; 1732 break; 1733 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 1734 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1735 ret = dsi_short_read1_resp(buf, msg); 1736 break; 1737 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 1738 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1739 ret = dsi_short_read2_resp(buf, msg); 1740 break; 1741 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 1742 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 1743 ret = dsi_long_read_resp(buf, msg); 1744 break; 1745 default: 1746 pr_warn("%s:Invalid response cmd\n", __func__); 1747 ret = 0; 1748 } 1749 1750 return ret; 1751 } 1752 1753 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 iova, u32 len) 1754 { 1755 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1756 1757 dsi_write(msm_host, REG_DSI_DMA_BASE, iova); 1758 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 1759 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 1760 1761 /* Make sure trigger happens */ 1762 wmb(); 1763 } 1764 1765 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, 1766 struct msm_dsi_pll *src_pll) 1767 { 1768 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1769 struct clk *byte_clk_provider, *pixel_clk_provider; 1770 int ret; 1771 1772 ret = msm_dsi_pll_get_clk_provider(src_pll, 1773 &byte_clk_provider, &pixel_clk_provider); 1774 if (ret) { 1775 pr_info("%s: can't get provider from pll, don't set parent\n", 1776 __func__); 1777 return 0; 1778 } 1779 1780 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider); 1781 if (ret) { 1782 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n", 1783 __func__, ret); 1784 goto exit; 1785 } 1786 1787 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider); 1788 if (ret) { 1789 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n", 1790 __func__, ret); 1791 goto exit; 1792 } 1793 1794 exit: 1795 return ret; 1796 } 1797 1798 int msm_dsi_host_enable(struct mipi_dsi_host *host) 1799 { 1800 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1801 1802 dsi_op_mode_config(msm_host, 1803 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 1804 1805 /* TODO: clock should be turned off for command mode, 1806 * and only turned on before MDP START. 1807 * This part of code should be enabled once mdp driver support it. 1808 */ 1809 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) 1810 dsi_clk_ctrl(msm_host, 0); */ 1811 1812 return 0; 1813 } 1814 1815 int msm_dsi_host_disable(struct mipi_dsi_host *host) 1816 { 1817 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1818 1819 dsi_op_mode_config(msm_host, 1820 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 1821 1822 /* Since we have disabled INTF, the video engine won't stop so that 1823 * the cmd engine will be blocked. 1824 * Reset to disable video engine so that we can send off cmd. 1825 */ 1826 dsi_sw_reset(msm_host); 1827 1828 return 0; 1829 } 1830 1831 int msm_dsi_host_power_on(struct mipi_dsi_host *host) 1832 { 1833 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1834 u32 clk_pre = 0, clk_post = 0; 1835 int ret = 0; 1836 1837 mutex_lock(&msm_host->dev_mutex); 1838 if (msm_host->power_on) { 1839 DBG("dsi host already on"); 1840 goto unlock_ret; 1841 } 1842 1843 ret = dsi_calc_clk_rate(msm_host); 1844 if (ret) { 1845 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 1846 goto unlock_ret; 1847 } 1848 1849 ret = dsi_host_regulator_enable(msm_host); 1850 if (ret) { 1851 pr_err("%s:Failed to enable vregs.ret=%d\n", 1852 __func__, ret); 1853 goto unlock_ret; 1854 } 1855 1856 ret = dsi_bus_clk_enable(msm_host); 1857 if (ret) { 1858 pr_err("%s: failed to enable bus clocks, %d\n", __func__, ret); 1859 goto fail_disable_reg; 1860 } 1861 1862 dsi_phy_sw_reset(msm_host); 1863 ret = msm_dsi_manager_phy_enable(msm_host->id, 1864 msm_host->byte_clk_rate * 8, 1865 clk_get_rate(msm_host->esc_clk), 1866 &clk_pre, &clk_post); 1867 dsi_bus_clk_disable(msm_host); 1868 if (ret) { 1869 pr_err("%s: failed to enable phy, %d\n", __func__, ret); 1870 goto fail_disable_reg; 1871 } 1872 1873 ret = dsi_clk_ctrl(msm_host, 1); 1874 if (ret) { 1875 pr_err("%s: failed to enable clocks. ret=%d\n", __func__, ret); 1876 goto fail_disable_reg; 1877 } 1878 1879 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); 1880 if (ret) { 1881 pr_err("%s: failed to set pinctrl default state, %d\n", 1882 __func__, ret); 1883 goto fail_disable_clk; 1884 } 1885 1886 dsi_timing_setup(msm_host); 1887 dsi_sw_reset(msm_host); 1888 dsi_ctrl_config(msm_host, true, clk_pre, clk_post); 1889 1890 if (msm_host->disp_en_gpio) 1891 gpiod_set_value(msm_host->disp_en_gpio, 1); 1892 1893 msm_host->power_on = true; 1894 mutex_unlock(&msm_host->dev_mutex); 1895 1896 return 0; 1897 1898 fail_disable_clk: 1899 dsi_clk_ctrl(msm_host, 0); 1900 fail_disable_reg: 1901 dsi_host_regulator_disable(msm_host); 1902 unlock_ret: 1903 mutex_unlock(&msm_host->dev_mutex); 1904 return ret; 1905 } 1906 1907 int msm_dsi_host_power_off(struct mipi_dsi_host *host) 1908 { 1909 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1910 1911 mutex_lock(&msm_host->dev_mutex); 1912 if (!msm_host->power_on) { 1913 DBG("dsi host already off"); 1914 goto unlock_ret; 1915 } 1916 1917 dsi_ctrl_config(msm_host, false, 0, 0); 1918 1919 if (msm_host->disp_en_gpio) 1920 gpiod_set_value(msm_host->disp_en_gpio, 0); 1921 1922 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); 1923 1924 msm_dsi_manager_phy_disable(msm_host->id); 1925 1926 dsi_clk_ctrl(msm_host, 0); 1927 1928 dsi_host_regulator_disable(msm_host); 1929 1930 DBG("-"); 1931 1932 msm_host->power_on = false; 1933 1934 unlock_ret: 1935 mutex_unlock(&msm_host->dev_mutex); 1936 return 0; 1937 } 1938 1939 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 1940 struct drm_display_mode *mode) 1941 { 1942 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1943 1944 if (msm_host->mode) { 1945 drm_mode_destroy(msm_host->dev, msm_host->mode); 1946 msm_host->mode = NULL; 1947 } 1948 1949 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 1950 if (IS_ERR(msm_host->mode)) { 1951 pr_err("%s: cannot duplicate mode\n", __func__); 1952 return PTR_ERR(msm_host->mode); 1953 } 1954 1955 return 0; 1956 } 1957 1958 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host, 1959 unsigned long *panel_flags) 1960 { 1961 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1962 struct drm_panel *panel; 1963 1964 panel = of_drm_find_panel(msm_host->device_node); 1965 if (panel_flags) 1966 *panel_flags = msm_host->mode_flags; 1967 1968 return panel; 1969 } 1970 1971 struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host) 1972 { 1973 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1974 1975 return of_drm_find_bridge(msm_host->device_node); 1976 } 1977