1 /* 2 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/gpio.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/interrupt.h> 20 #include <linux/of_device.h> 21 #include <linux/of_gpio.h> 22 #include <linux/of_irq.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/of_graph.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/spinlock.h> 27 #include <linux/mfd/syscon.h> 28 #include <linux/regmap.h> 29 #include <video/mipi_display.h> 30 31 #include "dsi.h" 32 #include "dsi.xml.h" 33 #include "sfpb.xml.h" 34 #include "dsi_cfg.h" 35 36 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 37 { 38 u32 ver; 39 40 if (!major || !minor) 41 return -EINVAL; 42 43 /* 44 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 45 * makes all other registers 4-byte shifted down. 46 * 47 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and 48 * older, we read the DSI_VERSION register without any shift(offset 49 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In 50 * the case of DSI6G, this has to be zero (the offset points to a 51 * scratch register which we never touch) 52 */ 53 54 ver = msm_readl(base + REG_DSI_VERSION); 55 if (ver) { 56 /* older dsi host, there is no register shift */ 57 ver = FIELD(ver, DSI_VERSION_MAJOR); 58 if (ver <= MSM_DSI_VER_MAJOR_V2) { 59 /* old versions */ 60 *major = ver; 61 *minor = 0; 62 return 0; 63 } else { 64 return -EINVAL; 65 } 66 } else { 67 /* 68 * newer host, offset 0 has 6G_HW_VERSION, the rest of the 69 * registers are shifted down, read DSI_VERSION again with 70 * the shifted offset 71 */ 72 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 73 ver = FIELD(ver, DSI_VERSION_MAJOR); 74 if (ver == MSM_DSI_VER_MAJOR_6G) { 75 /* 6G version */ 76 *major = ver; 77 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION); 78 return 0; 79 } else { 80 return -EINVAL; 81 } 82 } 83 } 84 85 #define DSI_ERR_STATE_ACK 0x0000 86 #define DSI_ERR_STATE_TIMEOUT 0x0001 87 #define DSI_ERR_STATE_DLN0_PHY 0x0002 88 #define DSI_ERR_STATE_FIFO 0x0004 89 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 90 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 91 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 92 93 #define DSI_CLK_CTRL_ENABLE_CLKS \ 94 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 95 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 96 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 97 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 98 99 struct msm_dsi_host { 100 struct mipi_dsi_host base; 101 102 struct platform_device *pdev; 103 struct drm_device *dev; 104 105 int id; 106 107 void __iomem *ctrl_base; 108 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; 109 110 struct clk *bus_clks[DSI_BUS_CLK_MAX]; 111 112 struct clk *byte_clk; 113 struct clk *esc_clk; 114 struct clk *pixel_clk; 115 struct clk *byte_clk_src; 116 struct clk *pixel_clk_src; 117 118 u32 byte_clk_rate; 119 u32 esc_clk_rate; 120 121 /* DSI v2 specific clocks */ 122 struct clk *src_clk; 123 struct clk *esc_clk_src; 124 struct clk *dsi_clk_src; 125 126 u32 src_clk_rate; 127 128 struct gpio_desc *disp_en_gpio; 129 struct gpio_desc *te_gpio; 130 131 const struct msm_dsi_cfg_handler *cfg_hnd; 132 133 struct completion dma_comp; 134 struct completion video_comp; 135 struct mutex dev_mutex; 136 struct mutex cmd_mutex; 137 struct mutex clk_mutex; 138 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 139 140 u32 err_work_state; 141 struct work_struct err_work; 142 struct workqueue_struct *workqueue; 143 144 /* DSI 6G TX buffer*/ 145 struct drm_gem_object *tx_gem_obj; 146 147 /* DSI v2 TX buffer */ 148 void *tx_buf; 149 dma_addr_t tx_buf_paddr; 150 151 int tx_size; 152 153 u8 *rx_buf; 154 155 struct regmap *sfpb; 156 157 struct drm_display_mode *mode; 158 159 /* connected device info */ 160 struct device_node *device_node; 161 unsigned int channel; 162 unsigned int lanes; 163 enum mipi_dsi_pixel_format format; 164 unsigned long mode_flags; 165 166 /* lane data parsed via DT */ 167 int dlane_swap; 168 int num_data_lanes; 169 170 u32 dma_cmd_ctrl_restore; 171 172 bool registered; 173 bool power_on; 174 int irq; 175 }; 176 177 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt) 178 { 179 switch (fmt) { 180 case MIPI_DSI_FMT_RGB565: return 16; 181 case MIPI_DSI_FMT_RGB666_PACKED: return 18; 182 case MIPI_DSI_FMT_RGB666: 183 case MIPI_DSI_FMT_RGB888: 184 default: return 24; 185 } 186 } 187 188 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 189 { 190 return msm_readl(msm_host->ctrl_base + reg); 191 } 192 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 193 { 194 msm_writel(data, msm_host->ctrl_base + reg); 195 } 196 197 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host); 198 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host); 199 200 static const struct msm_dsi_cfg_handler *dsi_get_config( 201 struct msm_dsi_host *msm_host) 202 { 203 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 204 struct device *dev = &msm_host->pdev->dev; 205 struct regulator *gdsc_reg; 206 struct clk *ahb_clk; 207 int ret; 208 u32 major = 0, minor = 0; 209 210 gdsc_reg = regulator_get(dev, "gdsc"); 211 if (IS_ERR(gdsc_reg)) { 212 pr_err("%s: cannot get gdsc\n", __func__); 213 goto exit; 214 } 215 216 ahb_clk = clk_get(dev, "iface_clk"); 217 if (IS_ERR(ahb_clk)) { 218 pr_err("%s: cannot get interface clock\n", __func__); 219 goto put_gdsc; 220 } 221 222 ret = regulator_enable(gdsc_reg); 223 if (ret) { 224 pr_err("%s: unable to enable gdsc\n", __func__); 225 goto put_clk; 226 } 227 228 ret = clk_prepare_enable(ahb_clk); 229 if (ret) { 230 pr_err("%s: unable to enable ahb_clk\n", __func__); 231 goto disable_gdsc; 232 } 233 234 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 235 if (ret) { 236 pr_err("%s: Invalid version\n", __func__); 237 goto disable_clks; 238 } 239 240 cfg_hnd = msm_dsi_cfg_get(major, minor); 241 242 DBG("%s: Version %x:%x\n", __func__, major, minor); 243 244 disable_clks: 245 clk_disable_unprepare(ahb_clk); 246 disable_gdsc: 247 regulator_disable(gdsc_reg); 248 put_clk: 249 clk_put(ahb_clk); 250 put_gdsc: 251 regulator_put(gdsc_reg); 252 exit: 253 return cfg_hnd; 254 } 255 256 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 257 { 258 return container_of(host, struct msm_dsi_host, base); 259 } 260 261 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host) 262 { 263 struct regulator_bulk_data *s = msm_host->supplies; 264 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 265 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 266 int i; 267 268 DBG(""); 269 for (i = num - 1; i >= 0; i--) 270 if (regs[i].disable_load >= 0) 271 regulator_set_load(s[i].consumer, 272 regs[i].disable_load); 273 274 regulator_bulk_disable(num, s); 275 } 276 277 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host) 278 { 279 struct regulator_bulk_data *s = msm_host->supplies; 280 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 281 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 282 int ret, i; 283 284 DBG(""); 285 for (i = 0; i < num; i++) { 286 if (regs[i].enable_load >= 0) { 287 ret = regulator_set_load(s[i].consumer, 288 regs[i].enable_load); 289 if (ret < 0) { 290 pr_err("regulator %d set op mode failed, %d\n", 291 i, ret); 292 goto fail; 293 } 294 } 295 } 296 297 ret = regulator_bulk_enable(num, s); 298 if (ret < 0) { 299 pr_err("regulator enable failed, %d\n", ret); 300 goto fail; 301 } 302 303 return 0; 304 305 fail: 306 for (i--; i >= 0; i--) 307 regulator_set_load(s[i].consumer, regs[i].disable_load); 308 return ret; 309 } 310 311 static int dsi_regulator_init(struct msm_dsi_host *msm_host) 312 { 313 struct regulator_bulk_data *s = msm_host->supplies; 314 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 315 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 316 int i, ret; 317 318 for (i = 0; i < num; i++) 319 s[i].supply = regs[i].name; 320 321 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s); 322 if (ret < 0) { 323 pr_err("%s: failed to init regulator, ret=%d\n", 324 __func__, ret); 325 return ret; 326 } 327 328 for (i = 0; i < num; i++) { 329 if (regulator_can_change_voltage(s[i].consumer)) { 330 ret = regulator_set_voltage(s[i].consumer, 331 regs[i].min_voltage, regs[i].max_voltage); 332 if (ret < 0) { 333 pr_err("regulator %d set voltage failed, %d\n", 334 i, ret); 335 return ret; 336 } 337 } 338 } 339 340 return 0; 341 } 342 343 static int dsi_clk_init(struct msm_dsi_host *msm_host) 344 { 345 struct device *dev = &msm_host->pdev->dev; 346 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 347 const struct msm_dsi_config *cfg = cfg_hnd->cfg; 348 int i, ret = 0; 349 350 /* get bus clocks */ 351 for (i = 0; i < cfg->num_bus_clks; i++) { 352 msm_host->bus_clks[i] = devm_clk_get(dev, 353 cfg->bus_clk_names[i]); 354 if (IS_ERR(msm_host->bus_clks[i])) { 355 ret = PTR_ERR(msm_host->bus_clks[i]); 356 pr_err("%s: Unable to get %s, ret = %d\n", 357 __func__, cfg->bus_clk_names[i], ret); 358 goto exit; 359 } 360 } 361 362 /* get link and source clocks */ 363 msm_host->byte_clk = devm_clk_get(dev, "byte_clk"); 364 if (IS_ERR(msm_host->byte_clk)) { 365 ret = PTR_ERR(msm_host->byte_clk); 366 pr_err("%s: can't find dsi_byte_clk. ret=%d\n", 367 __func__, ret); 368 msm_host->byte_clk = NULL; 369 goto exit; 370 } 371 372 msm_host->pixel_clk = devm_clk_get(dev, "pixel_clk"); 373 if (IS_ERR(msm_host->pixel_clk)) { 374 ret = PTR_ERR(msm_host->pixel_clk); 375 pr_err("%s: can't find dsi_pixel_clk. ret=%d\n", 376 __func__, ret); 377 msm_host->pixel_clk = NULL; 378 goto exit; 379 } 380 381 msm_host->esc_clk = devm_clk_get(dev, "core_clk"); 382 if (IS_ERR(msm_host->esc_clk)) { 383 ret = PTR_ERR(msm_host->esc_clk); 384 pr_err("%s: can't find dsi_esc_clk. ret=%d\n", 385 __func__, ret); 386 msm_host->esc_clk = NULL; 387 goto exit; 388 } 389 390 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk); 391 if (!msm_host->byte_clk_src) { 392 ret = -ENODEV; 393 pr_err("%s: can't find byte_clk_src. ret=%d\n", __func__, ret); 394 goto exit; 395 } 396 397 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk); 398 if (!msm_host->pixel_clk_src) { 399 ret = -ENODEV; 400 pr_err("%s: can't find pixel_clk_src. ret=%d\n", __func__, ret); 401 goto exit; 402 } 403 404 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) { 405 msm_host->src_clk = devm_clk_get(dev, "src_clk"); 406 if (IS_ERR(msm_host->src_clk)) { 407 ret = PTR_ERR(msm_host->src_clk); 408 pr_err("%s: can't find dsi_src_clk. ret=%d\n", 409 __func__, ret); 410 msm_host->src_clk = NULL; 411 goto exit; 412 } 413 414 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk); 415 if (!msm_host->esc_clk_src) { 416 ret = -ENODEV; 417 pr_err("%s: can't get esc_clk_src. ret=%d\n", 418 __func__, ret); 419 goto exit; 420 } 421 422 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk); 423 if (!msm_host->dsi_clk_src) { 424 ret = -ENODEV; 425 pr_err("%s: can't get dsi_clk_src. ret=%d\n", 426 __func__, ret); 427 } 428 } 429 exit: 430 return ret; 431 } 432 433 static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host) 434 { 435 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 436 int i, ret; 437 438 DBG("id=%d", msm_host->id); 439 440 for (i = 0; i < cfg->num_bus_clks; i++) { 441 ret = clk_prepare_enable(msm_host->bus_clks[i]); 442 if (ret) { 443 pr_err("%s: failed to enable bus clock %d ret %d\n", 444 __func__, i, ret); 445 goto err; 446 } 447 } 448 449 return 0; 450 err: 451 for (; i > 0; i--) 452 clk_disable_unprepare(msm_host->bus_clks[i]); 453 454 return ret; 455 } 456 457 static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host) 458 { 459 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 460 int i; 461 462 DBG(""); 463 464 for (i = cfg->num_bus_clks - 1; i >= 0; i--) 465 clk_disable_unprepare(msm_host->bus_clks[i]); 466 } 467 468 static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) 469 { 470 int ret; 471 472 DBG("Set clk rates: pclk=%d, byteclk=%d", 473 msm_host->mode->clock, msm_host->byte_clk_rate); 474 475 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 476 if (ret) { 477 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 478 goto error; 479 } 480 481 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000); 482 if (ret) { 483 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 484 goto error; 485 } 486 487 ret = clk_prepare_enable(msm_host->esc_clk); 488 if (ret) { 489 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 490 goto error; 491 } 492 493 ret = clk_prepare_enable(msm_host->byte_clk); 494 if (ret) { 495 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 496 goto byte_clk_err; 497 } 498 499 ret = clk_prepare_enable(msm_host->pixel_clk); 500 if (ret) { 501 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 502 goto pixel_clk_err; 503 } 504 505 return 0; 506 507 pixel_clk_err: 508 clk_disable_unprepare(msm_host->byte_clk); 509 byte_clk_err: 510 clk_disable_unprepare(msm_host->esc_clk); 511 error: 512 return ret; 513 } 514 515 static int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) 516 { 517 int ret; 518 519 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d", 520 msm_host->mode->clock, msm_host->byte_clk_rate, 521 msm_host->esc_clk_rate, msm_host->src_clk_rate); 522 523 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 524 if (ret) { 525 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 526 goto error; 527 } 528 529 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); 530 if (ret) { 531 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); 532 goto error; 533 } 534 535 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); 536 if (ret) { 537 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); 538 goto error; 539 } 540 541 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000); 542 if (ret) { 543 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 544 goto error; 545 } 546 547 ret = clk_prepare_enable(msm_host->byte_clk); 548 if (ret) { 549 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 550 goto error; 551 } 552 553 ret = clk_prepare_enable(msm_host->esc_clk); 554 if (ret) { 555 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 556 goto esc_clk_err; 557 } 558 559 ret = clk_prepare_enable(msm_host->src_clk); 560 if (ret) { 561 pr_err("%s: Failed to enable dsi src clk\n", __func__); 562 goto src_clk_err; 563 } 564 565 ret = clk_prepare_enable(msm_host->pixel_clk); 566 if (ret) { 567 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 568 goto pixel_clk_err; 569 } 570 571 return 0; 572 573 pixel_clk_err: 574 clk_disable_unprepare(msm_host->src_clk); 575 src_clk_err: 576 clk_disable_unprepare(msm_host->esc_clk); 577 esc_clk_err: 578 clk_disable_unprepare(msm_host->byte_clk); 579 error: 580 return ret; 581 } 582 583 static int dsi_link_clk_enable(struct msm_dsi_host *msm_host) 584 { 585 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 586 587 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) 588 return dsi_link_clk_enable_6g(msm_host); 589 else 590 return dsi_link_clk_enable_v2(msm_host); 591 } 592 593 static void dsi_link_clk_disable(struct msm_dsi_host *msm_host) 594 { 595 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 596 597 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { 598 clk_disable_unprepare(msm_host->esc_clk); 599 clk_disable_unprepare(msm_host->pixel_clk); 600 clk_disable_unprepare(msm_host->byte_clk); 601 } else { 602 clk_disable_unprepare(msm_host->pixel_clk); 603 clk_disable_unprepare(msm_host->src_clk); 604 clk_disable_unprepare(msm_host->esc_clk); 605 clk_disable_unprepare(msm_host->byte_clk); 606 } 607 } 608 609 static int dsi_clk_ctrl(struct msm_dsi_host *msm_host, bool enable) 610 { 611 int ret = 0; 612 613 mutex_lock(&msm_host->clk_mutex); 614 if (enable) { 615 ret = dsi_bus_clk_enable(msm_host); 616 if (ret) { 617 pr_err("%s: Can not enable bus clk, %d\n", 618 __func__, ret); 619 goto unlock_ret; 620 } 621 ret = dsi_link_clk_enable(msm_host); 622 if (ret) { 623 pr_err("%s: Can not enable link clk, %d\n", 624 __func__, ret); 625 dsi_bus_clk_disable(msm_host); 626 goto unlock_ret; 627 } 628 } else { 629 dsi_link_clk_disable(msm_host); 630 dsi_bus_clk_disable(msm_host); 631 } 632 633 unlock_ret: 634 mutex_unlock(&msm_host->clk_mutex); 635 return ret; 636 } 637 638 static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host) 639 { 640 struct drm_display_mode *mode = msm_host->mode; 641 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 642 u8 lanes = msm_host->lanes; 643 u32 bpp = dsi_get_bpp(msm_host->format); 644 u32 pclk_rate; 645 646 if (!mode) { 647 pr_err("%s: mode not set\n", __func__); 648 return -EINVAL; 649 } 650 651 pclk_rate = mode->clock * 1000; 652 if (lanes > 0) { 653 msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes); 654 } else { 655 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 656 msm_host->byte_clk_rate = (pclk_rate * bpp) / 8; 657 } 658 659 DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate); 660 661 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); 662 663 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) { 664 unsigned int esc_mhz, esc_div; 665 unsigned long byte_mhz; 666 667 msm_host->src_clk_rate = (pclk_rate * bpp) / 8; 668 669 /* 670 * esc clock is byte clock followed by a 4 bit divider, 671 * we need to find an escape clock frequency within the 672 * mipi DSI spec range within the maximum divider limit 673 * We iterate here between an escape clock frequencey 674 * between 20 Mhz to 5 Mhz and pick up the first one 675 * that can be supported by our divider 676 */ 677 678 byte_mhz = msm_host->byte_clk_rate / 1000000; 679 680 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { 681 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); 682 683 /* 684 * TODO: Ideally, we shouldn't know what sort of divider 685 * is available in mmss_cc, we're just assuming that 686 * it'll always be a 4 bit divider. Need to come up with 687 * a better way here. 688 */ 689 if (esc_div >= 1 && esc_div <= 16) 690 break; 691 } 692 693 if (esc_mhz < 5) 694 return -EINVAL; 695 696 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; 697 698 DBG("esc=%d, src=%d", msm_host->esc_clk_rate, 699 msm_host->src_clk_rate); 700 } 701 702 return 0; 703 } 704 705 static void dsi_phy_sw_reset(struct msm_dsi_host *msm_host) 706 { 707 DBG(""); 708 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 709 /* Make sure fully reset */ 710 wmb(); 711 udelay(1000); 712 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 713 udelay(100); 714 } 715 716 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 717 { 718 u32 intr; 719 unsigned long flags; 720 721 spin_lock_irqsave(&msm_host->intr_lock, flags); 722 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 723 724 if (enable) 725 intr |= mask; 726 else 727 intr &= ~mask; 728 729 DBG("intr=%x enable=%d", intr, enable); 730 731 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 732 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 733 } 734 735 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 736 { 737 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 738 return BURST_MODE; 739 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 740 return NON_BURST_SYNCH_PULSE; 741 742 return NON_BURST_SYNCH_EVENT; 743 } 744 745 static inline enum dsi_vid_dst_format dsi_get_vid_fmt( 746 const enum mipi_dsi_pixel_format mipi_fmt) 747 { 748 switch (mipi_fmt) { 749 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 750 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 751 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 752 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 753 default: return VID_DST_FORMAT_RGB888; 754 } 755 } 756 757 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( 758 const enum mipi_dsi_pixel_format mipi_fmt) 759 { 760 switch (mipi_fmt) { 761 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 762 case MIPI_DSI_FMT_RGB666_PACKED: 763 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666; 764 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 765 default: return CMD_DST_FORMAT_RGB888; 766 } 767 } 768 769 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, 770 u32 clk_pre, u32 clk_post) 771 { 772 u32 flags = msm_host->mode_flags; 773 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 774 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 775 u32 data = 0; 776 777 if (!enable) { 778 dsi_write(msm_host, REG_DSI_CTRL, 0); 779 return; 780 } 781 782 if (flags & MIPI_DSI_MODE_VIDEO) { 783 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 784 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 785 if (flags & MIPI_DSI_MODE_VIDEO_HFP) 786 data |= DSI_VID_CFG0_HFP_POWER_STOP; 787 if (flags & MIPI_DSI_MODE_VIDEO_HBP) 788 data |= DSI_VID_CFG0_HBP_POWER_STOP; 789 if (flags & MIPI_DSI_MODE_VIDEO_HSA) 790 data |= DSI_VID_CFG0_HSA_POWER_STOP; 791 /* Always set low power stop mode for BLLP 792 * to let command engine send packets 793 */ 794 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 795 DSI_VID_CFG0_BLLP_POWER_STOP; 796 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 797 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 798 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 799 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 800 801 /* Do not swap RGB colors */ 802 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 803 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 804 } else { 805 /* Do not swap RGB colors */ 806 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 807 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 808 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 809 810 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 811 DSI_CMD_CFG1_WR_MEM_CONTINUE( 812 MIPI_DCS_WRITE_MEMORY_CONTINUE); 813 /* Always insert DCS command */ 814 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 815 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 816 } 817 818 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 819 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 820 DSI_CMD_DMA_CTRL_LOW_POWER); 821 822 data = 0; 823 /* Always assume dedicated TE pin */ 824 data |= DSI_TRIG_CTRL_TE; 825 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 826 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 827 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 828 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 829 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 830 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 831 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 832 833 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(clk_post) | 834 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(clk_pre); 835 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 836 837 data = 0; 838 if (!(flags & MIPI_DSI_MODE_EOT_PACKET)) 839 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 840 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 841 842 /* allow only ack-err-status to generate interrupt */ 843 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 844 845 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 846 847 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 848 849 data = DSI_CTRL_CLK_EN; 850 851 DBG("lane number=%d", msm_host->lanes); 852 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); 853 854 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 855 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); 856 857 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 858 dsi_write(msm_host, REG_DSI_LANE_CTRL, 859 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); 860 861 data |= DSI_CTRL_ENABLE; 862 863 dsi_write(msm_host, REG_DSI_CTRL, data); 864 } 865 866 static void dsi_timing_setup(struct msm_dsi_host *msm_host) 867 { 868 struct drm_display_mode *mode = msm_host->mode; 869 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 870 u32 h_total = mode->htotal; 871 u32 v_total = mode->vtotal; 872 u32 hs_end = mode->hsync_end - mode->hsync_start; 873 u32 vs_end = mode->vsync_end - mode->vsync_start; 874 u32 ha_start = h_total - mode->hsync_start; 875 u32 ha_end = ha_start + mode->hdisplay; 876 u32 va_start = v_total - mode->vsync_start; 877 u32 va_end = va_start + mode->vdisplay; 878 u32 wc; 879 880 DBG(""); 881 882 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 883 dsi_write(msm_host, REG_DSI_ACTIVE_H, 884 DSI_ACTIVE_H_START(ha_start) | 885 DSI_ACTIVE_H_END(ha_end)); 886 dsi_write(msm_host, REG_DSI_ACTIVE_V, 887 DSI_ACTIVE_V_START(va_start) | 888 DSI_ACTIVE_V_END(va_end)); 889 dsi_write(msm_host, REG_DSI_TOTAL, 890 DSI_TOTAL_H_TOTAL(h_total - 1) | 891 DSI_TOTAL_V_TOTAL(v_total - 1)); 892 893 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 894 DSI_ACTIVE_HSYNC_START(hs_start) | 895 DSI_ACTIVE_HSYNC_END(hs_end)); 896 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 897 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 898 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 899 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 900 } else { /* command mode */ 901 /* image data and 1 byte write_memory_start cmd */ 902 wc = mode->hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; 903 904 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL, 905 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) | 906 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL( 907 msm_host->channel) | 908 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE( 909 MIPI_DSI_DCS_LONG_WRITE)); 910 911 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL, 912 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(mode->hdisplay) | 913 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay)); 914 } 915 } 916 917 static void dsi_sw_reset(struct msm_dsi_host *msm_host) 918 { 919 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 920 wmb(); /* clocks need to be enabled before reset */ 921 922 dsi_write(msm_host, REG_DSI_RESET, 1); 923 wmb(); /* make sure reset happen */ 924 dsi_write(msm_host, REG_DSI_RESET, 0); 925 } 926 927 static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 928 bool video_mode, bool enable) 929 { 930 u32 dsi_ctrl; 931 932 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 933 934 if (!enable) { 935 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 936 DSI_CTRL_CMD_MODE_EN); 937 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 938 DSI_IRQ_MASK_VIDEO_DONE, 0); 939 } else { 940 if (video_mode) { 941 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 942 } else { /* command mode */ 943 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 944 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 945 } 946 dsi_ctrl |= DSI_CTRL_ENABLE; 947 } 948 949 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 950 } 951 952 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 953 { 954 u32 data; 955 956 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 957 958 if (mode == 0) 959 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 960 else 961 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 962 963 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 964 } 965 966 static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 967 { 968 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 969 970 reinit_completion(&msm_host->video_comp); 971 972 wait_for_completion_timeout(&msm_host->video_comp, 973 msecs_to_jiffies(70)); 974 975 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 976 } 977 978 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 979 { 980 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 981 return; 982 983 if (msm_host->power_on) { 984 dsi_wait4video_done(msm_host); 985 /* delay 4 ms to skip BLLP */ 986 usleep_range(2000, 4000); 987 } 988 } 989 990 /* dsi_cmd */ 991 static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size) 992 { 993 struct drm_device *dev = msm_host->dev; 994 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 995 int ret; 996 u32 iova; 997 998 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { 999 mutex_lock(&dev->struct_mutex); 1000 msm_host->tx_gem_obj = msm_gem_new(dev, size, MSM_BO_UNCACHED); 1001 if (IS_ERR(msm_host->tx_gem_obj)) { 1002 ret = PTR_ERR(msm_host->tx_gem_obj); 1003 pr_err("%s: failed to allocate gem, %d\n", 1004 __func__, ret); 1005 msm_host->tx_gem_obj = NULL; 1006 mutex_unlock(&dev->struct_mutex); 1007 return ret; 1008 } 1009 1010 ret = msm_gem_get_iova_locked(msm_host->tx_gem_obj, 0, &iova); 1011 mutex_unlock(&dev->struct_mutex); 1012 if (ret) { 1013 pr_err("%s: failed to get iova, %d\n", __func__, ret); 1014 return ret; 1015 } 1016 1017 if (iova & 0x07) { 1018 pr_err("%s: buf NOT 8 bytes aligned\n", __func__); 1019 return -EINVAL; 1020 } 1021 1022 msm_host->tx_size = msm_host->tx_gem_obj->size; 1023 } else { 1024 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, 1025 &msm_host->tx_buf_paddr, GFP_KERNEL); 1026 if (!msm_host->tx_buf) { 1027 ret = -ENOMEM; 1028 pr_err("%s: failed to allocate tx buf, %d\n", 1029 __func__, ret); 1030 return ret; 1031 } 1032 1033 msm_host->tx_size = size; 1034 } 1035 1036 return 0; 1037 } 1038 1039 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host) 1040 { 1041 struct drm_device *dev = msm_host->dev; 1042 1043 if (msm_host->tx_gem_obj) { 1044 msm_gem_put_iova(msm_host->tx_gem_obj, 0); 1045 mutex_lock(&dev->struct_mutex); 1046 msm_gem_free_object(msm_host->tx_gem_obj); 1047 msm_host->tx_gem_obj = NULL; 1048 mutex_unlock(&dev->struct_mutex); 1049 } 1050 1051 if (msm_host->tx_buf) 1052 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, 1053 msm_host->tx_buf_paddr); 1054 } 1055 1056 /* 1057 * prepare cmd buffer to be txed 1058 */ 1059 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, 1060 const struct mipi_dsi_msg *msg) 1061 { 1062 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1063 struct mipi_dsi_packet packet; 1064 int len; 1065 int ret; 1066 u8 *data; 1067 1068 ret = mipi_dsi_create_packet(&packet, msg); 1069 if (ret) { 1070 pr_err("%s: create packet failed, %d\n", __func__, ret); 1071 return ret; 1072 } 1073 len = (packet.size + 3) & (~0x3); 1074 1075 if (len > msm_host->tx_size) { 1076 pr_err("%s: packet size is too big\n", __func__); 1077 return -EINVAL; 1078 } 1079 1080 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { 1081 data = msm_gem_vaddr(msm_host->tx_gem_obj); 1082 if (IS_ERR(data)) { 1083 ret = PTR_ERR(data); 1084 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 1085 return ret; 1086 } 1087 } else { 1088 data = msm_host->tx_buf; 1089 } 1090 1091 /* MSM specific command format in memory */ 1092 data[0] = packet.header[1]; 1093 data[1] = packet.header[2]; 1094 data[2] = packet.header[0]; 1095 data[3] = BIT(7); /* Last packet */ 1096 if (mipi_dsi_packet_format_is_long(msg->type)) 1097 data[3] |= BIT(6); 1098 if (msg->rx_buf && msg->rx_len) 1099 data[3] |= BIT(5); 1100 1101 /* Long packet */ 1102 if (packet.payload && packet.payload_length) 1103 memcpy(data + 4, packet.payload, packet.payload_length); 1104 1105 /* Append 0xff to the end */ 1106 if (packet.size < len) 1107 memset(data + packet.size, 0xff, len - packet.size); 1108 1109 return len; 1110 } 1111 1112 /* 1113 * dsi_short_read1_resp: 1 parameter 1114 */ 1115 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1116 { 1117 u8 *data = msg->rx_buf; 1118 if (data && (msg->rx_len >= 1)) { 1119 *data = buf[1]; /* strip out dcs type */ 1120 return 1; 1121 } else { 1122 pr_err("%s: read data does not match with rx_buf len %zu\n", 1123 __func__, msg->rx_len); 1124 return -EINVAL; 1125 } 1126 } 1127 1128 /* 1129 * dsi_short_read2_resp: 2 parameter 1130 */ 1131 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1132 { 1133 u8 *data = msg->rx_buf; 1134 if (data && (msg->rx_len >= 2)) { 1135 data[0] = buf[1]; /* strip out dcs type */ 1136 data[1] = buf[2]; 1137 return 2; 1138 } else { 1139 pr_err("%s: read data does not match with rx_buf len %zu\n", 1140 __func__, msg->rx_len); 1141 return -EINVAL; 1142 } 1143 } 1144 1145 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1146 { 1147 /* strip out 4 byte dcs header */ 1148 if (msg->rx_buf && msg->rx_len) 1149 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 1150 1151 return msg->rx_len; 1152 } 1153 1154 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 1155 { 1156 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1157 int ret; 1158 u32 dma_base; 1159 bool triggered; 1160 1161 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { 1162 ret = msm_gem_get_iova(msm_host->tx_gem_obj, 0, &dma_base); 1163 if (ret) { 1164 pr_err("%s: failed to get iova: %d\n", __func__, ret); 1165 return ret; 1166 } 1167 } else { 1168 dma_base = msm_host->tx_buf_paddr; 1169 } 1170 1171 reinit_completion(&msm_host->dma_comp); 1172 1173 dsi_wait4video_eng_busy(msm_host); 1174 1175 triggered = msm_dsi_manager_cmd_xfer_trigger( 1176 msm_host->id, dma_base, len); 1177 if (triggered) { 1178 ret = wait_for_completion_timeout(&msm_host->dma_comp, 1179 msecs_to_jiffies(200)); 1180 DBG("ret=%d", ret); 1181 if (ret == 0) 1182 ret = -ETIMEDOUT; 1183 else 1184 ret = len; 1185 } else 1186 ret = len; 1187 1188 return ret; 1189 } 1190 1191 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1192 u8 *buf, int rx_byte, int pkt_size) 1193 { 1194 u32 *lp, *temp, data; 1195 int i, j = 0, cnt; 1196 u32 read_cnt; 1197 u8 reg[16]; 1198 int repeated_bytes = 0; 1199 int buf_offset = buf - msm_host->rx_buf; 1200 1201 lp = (u32 *)buf; 1202 temp = (u32 *)reg; 1203 cnt = (rx_byte + 3) >> 2; 1204 if (cnt > 4) 1205 cnt = 4; /* 4 x 32 bits registers only */ 1206 1207 if (rx_byte == 4) 1208 read_cnt = 4; 1209 else 1210 read_cnt = pkt_size + 6; 1211 1212 /* 1213 * In case of multiple reads from the panel, after the first read, there 1214 * is possibility that there are some bytes in the payload repeating in 1215 * the RDBK_DATA registers. Since we read all the parameters from the 1216 * panel right from the first byte for every pass. We need to skip the 1217 * repeating bytes and then append the new parameters to the rx buffer. 1218 */ 1219 if (read_cnt > 16) { 1220 int bytes_shifted; 1221 /* Any data more than 16 bytes will be shifted out. 1222 * The temp read buffer should already contain these bytes. 1223 * The remaining bytes in read buffer are the repeated bytes. 1224 */ 1225 bytes_shifted = read_cnt - 16; 1226 repeated_bytes = buf_offset - bytes_shifted; 1227 } 1228 1229 for (i = cnt - 1; i >= 0; i--) { 1230 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1231 *temp++ = ntohl(data); /* to host byte order */ 1232 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1233 } 1234 1235 for (i = repeated_bytes; i < 16; i++) 1236 buf[j++] = reg[i]; 1237 1238 return j; 1239 } 1240 1241 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1242 const struct mipi_dsi_msg *msg) 1243 { 1244 int len, ret; 1245 int bllp_len = msm_host->mode->hdisplay * 1246 dsi_get_bpp(msm_host->format) / 8; 1247 1248 len = dsi_cmd_dma_add(msm_host, msg); 1249 if (!len) { 1250 pr_err("%s: failed to add cmd type = 0x%x\n", 1251 __func__, msg->type); 1252 return -EINVAL; 1253 } 1254 1255 /* for video mode, do not send cmds more than 1256 * one pixel line, since it only transmit it 1257 * during BLLP. 1258 */ 1259 /* TODO: if the command is sent in LP mode, the bit rate is only 1260 * half of esc clk rate. In this case, if the video is already 1261 * actively streaming, we need to check more carefully if the 1262 * command can be fit into one BLLP. 1263 */ 1264 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1265 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1266 __func__, len); 1267 return -EINVAL; 1268 } 1269 1270 ret = dsi_cmd_dma_tx(msm_host, len); 1271 if (ret < len) { 1272 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n", 1273 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len); 1274 return -ECOMM; 1275 } 1276 1277 return len; 1278 } 1279 1280 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host) 1281 { 1282 u32 data0, data1; 1283 1284 data0 = dsi_read(msm_host, REG_DSI_CTRL); 1285 data1 = data0; 1286 data1 &= ~DSI_CTRL_ENABLE; 1287 dsi_write(msm_host, REG_DSI_CTRL, data1); 1288 /* 1289 * dsi controller need to be disabled before 1290 * clocks turned on 1291 */ 1292 wmb(); 1293 1294 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1295 wmb(); /* make sure clocks enabled */ 1296 1297 /* dsi controller can only be reset while clocks are running */ 1298 dsi_write(msm_host, REG_DSI_RESET, 1); 1299 wmb(); /* make sure reset happen */ 1300 dsi_write(msm_host, REG_DSI_RESET, 0); 1301 wmb(); /* controller out of reset */ 1302 dsi_write(msm_host, REG_DSI_CTRL, data0); 1303 wmb(); /* make sure dsi controller enabled again */ 1304 } 1305 1306 static void dsi_err_worker(struct work_struct *work) 1307 { 1308 struct msm_dsi_host *msm_host = 1309 container_of(work, struct msm_dsi_host, err_work); 1310 u32 status = msm_host->err_work_state; 1311 1312 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1313 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1314 dsi_sw_reset_restore(msm_host); 1315 1316 /* It is safe to clear here because error irq is disabled. */ 1317 msm_host->err_work_state = 0; 1318 1319 /* enable dsi error interrupt */ 1320 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1321 } 1322 1323 static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1324 { 1325 u32 status; 1326 1327 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1328 1329 if (status) { 1330 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1331 /* Writing of an extra 0 needed to clear error bits */ 1332 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1333 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1334 } 1335 } 1336 1337 static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1338 { 1339 u32 status; 1340 1341 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1342 1343 if (status) { 1344 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1345 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1346 } 1347 } 1348 1349 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1350 { 1351 u32 status; 1352 1353 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1354 1355 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | 1356 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | 1357 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | 1358 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | 1359 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { 1360 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1361 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1362 } 1363 } 1364 1365 static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1366 { 1367 u32 status; 1368 1369 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1370 1371 /* fifo underflow, overflow */ 1372 if (status) { 1373 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1374 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1375 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1376 msm_host->err_work_state |= 1377 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1378 } 1379 } 1380 1381 static void dsi_status(struct msm_dsi_host *msm_host) 1382 { 1383 u32 status; 1384 1385 status = dsi_read(msm_host, REG_DSI_STATUS0); 1386 1387 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1388 dsi_write(msm_host, REG_DSI_STATUS0, status); 1389 msm_host->err_work_state |= 1390 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1391 } 1392 } 1393 1394 static void dsi_clk_status(struct msm_dsi_host *msm_host) 1395 { 1396 u32 status; 1397 1398 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1399 1400 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1401 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1402 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1403 } 1404 } 1405 1406 static void dsi_error(struct msm_dsi_host *msm_host) 1407 { 1408 /* disable dsi error interrupt */ 1409 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1410 1411 dsi_clk_status(msm_host); 1412 dsi_fifo_status(msm_host); 1413 dsi_ack_err_status(msm_host); 1414 dsi_timeout_status(msm_host); 1415 dsi_status(msm_host); 1416 dsi_dln0_phy_err(msm_host); 1417 1418 queue_work(msm_host->workqueue, &msm_host->err_work); 1419 } 1420 1421 static irqreturn_t dsi_host_irq(int irq, void *ptr) 1422 { 1423 struct msm_dsi_host *msm_host = ptr; 1424 u32 isr; 1425 unsigned long flags; 1426 1427 if (!msm_host->ctrl_base) 1428 return IRQ_HANDLED; 1429 1430 spin_lock_irqsave(&msm_host->intr_lock, flags); 1431 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1432 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1433 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1434 1435 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1436 1437 if (isr & DSI_IRQ_ERROR) 1438 dsi_error(msm_host); 1439 1440 if (isr & DSI_IRQ_VIDEO_DONE) 1441 complete(&msm_host->video_comp); 1442 1443 if (isr & DSI_IRQ_CMD_DMA_DONE) 1444 complete(&msm_host->dma_comp); 1445 1446 return IRQ_HANDLED; 1447 } 1448 1449 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, 1450 struct device *panel_device) 1451 { 1452 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device, 1453 "disp-enable", 1454 GPIOD_OUT_LOW); 1455 if (IS_ERR(msm_host->disp_en_gpio)) { 1456 DBG("cannot get disp-enable-gpios %ld", 1457 PTR_ERR(msm_host->disp_en_gpio)); 1458 return PTR_ERR(msm_host->disp_en_gpio); 1459 } 1460 1461 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te", 1462 GPIOD_IN); 1463 if (IS_ERR(msm_host->te_gpio)) { 1464 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); 1465 return PTR_ERR(msm_host->te_gpio); 1466 } 1467 1468 return 0; 1469 } 1470 1471 static int dsi_host_attach(struct mipi_dsi_host *host, 1472 struct mipi_dsi_device *dsi) 1473 { 1474 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1475 int ret; 1476 1477 if (dsi->lanes > msm_host->num_data_lanes) 1478 return -EINVAL; 1479 1480 msm_host->channel = dsi->channel; 1481 msm_host->lanes = dsi->lanes; 1482 msm_host->format = dsi->format; 1483 msm_host->mode_flags = dsi->mode_flags; 1484 1485 /* Some gpios defined in panel DT need to be controlled by host */ 1486 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); 1487 if (ret) 1488 return ret; 1489 1490 DBG("id=%d", msm_host->id); 1491 if (msm_host->dev) 1492 drm_helper_hpd_irq_event(msm_host->dev); 1493 1494 return 0; 1495 } 1496 1497 static int dsi_host_detach(struct mipi_dsi_host *host, 1498 struct mipi_dsi_device *dsi) 1499 { 1500 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1501 1502 msm_host->device_node = NULL; 1503 1504 DBG("id=%d", msm_host->id); 1505 if (msm_host->dev) 1506 drm_helper_hpd_irq_event(msm_host->dev); 1507 1508 return 0; 1509 } 1510 1511 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1512 const struct mipi_dsi_msg *msg) 1513 { 1514 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1515 int ret; 1516 1517 if (!msg || !msm_host->power_on) 1518 return -EINVAL; 1519 1520 mutex_lock(&msm_host->cmd_mutex); 1521 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1522 mutex_unlock(&msm_host->cmd_mutex); 1523 1524 return ret; 1525 } 1526 1527 static struct mipi_dsi_host_ops dsi_host_ops = { 1528 .attach = dsi_host_attach, 1529 .detach = dsi_host_detach, 1530 .transfer = dsi_host_transfer, 1531 }; 1532 1533 /* 1534 * List of supported physical to logical lane mappings. 1535 * For example, the 2nd entry represents the following mapping: 1536 * 1537 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; 1538 */ 1539 static const int supported_data_lane_swaps[][4] = { 1540 { 0, 1, 2, 3 }, 1541 { 3, 0, 1, 2 }, 1542 { 2, 3, 0, 1 }, 1543 { 1, 2, 3, 0 }, 1544 { 0, 3, 2, 1 }, 1545 { 1, 0, 3, 2 }, 1546 { 2, 1, 0, 3 }, 1547 { 3, 2, 1, 0 }, 1548 }; 1549 1550 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, 1551 struct device_node *ep) 1552 { 1553 struct device *dev = &msm_host->pdev->dev; 1554 struct property *prop; 1555 u32 lane_map[4]; 1556 int ret, i, len, num_lanes; 1557 1558 prop = of_find_property(ep, "qcom,data-lane-map", &len); 1559 if (!prop) { 1560 dev_dbg(dev, "failed to find data lane mapping\n"); 1561 return -EINVAL; 1562 } 1563 1564 num_lanes = len / sizeof(u32); 1565 1566 if (num_lanes < 1 || num_lanes > 4) { 1567 dev_err(dev, "bad number of data lanes\n"); 1568 return -EINVAL; 1569 } 1570 1571 msm_host->num_data_lanes = num_lanes; 1572 1573 ret = of_property_read_u32_array(ep, "qcom,data-lane-map", lane_map, 1574 num_lanes); 1575 if (ret) { 1576 dev_err(dev, "failed to read lane data\n"); 1577 return ret; 1578 } 1579 1580 /* 1581 * compare DT specified physical-logical lane mappings with the ones 1582 * supported by hardware 1583 */ 1584 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { 1585 const int *swap = supported_data_lane_swaps[i]; 1586 int j; 1587 1588 for (j = 0; j < num_lanes; j++) { 1589 if (swap[j] != lane_map[j]) 1590 break; 1591 } 1592 1593 if (j == num_lanes) { 1594 msm_host->dlane_swap = i; 1595 return 0; 1596 } 1597 } 1598 1599 return -EINVAL; 1600 } 1601 1602 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) 1603 { 1604 struct device *dev = &msm_host->pdev->dev; 1605 struct device_node *np = dev->of_node; 1606 struct device_node *endpoint, *device_node; 1607 int ret; 1608 1609 ret = of_property_read_u32(np, "qcom,dsi-host-index", &msm_host->id); 1610 if (ret) { 1611 dev_err(dev, "%s: host index not specified, ret=%d\n", 1612 __func__, ret); 1613 return ret; 1614 } 1615 1616 /* 1617 * Get the first endpoint node. In our case, dsi has one output port 1618 * to which the panel is connected. Don't return an error if a port 1619 * isn't defined. It's possible that there is nothing connected to 1620 * the dsi output. 1621 */ 1622 endpoint = of_graph_get_next_endpoint(np, NULL); 1623 if (!endpoint) { 1624 dev_dbg(dev, "%s: no endpoint\n", __func__); 1625 return 0; 1626 } 1627 1628 ret = dsi_host_parse_lane_data(msm_host, endpoint); 1629 if (ret) { 1630 dev_err(dev, "%s: invalid lane configuration %d\n", 1631 __func__, ret); 1632 goto err; 1633 } 1634 1635 /* Get panel node from the output port's endpoint data */ 1636 device_node = of_graph_get_remote_port_parent(endpoint); 1637 if (!device_node) { 1638 dev_err(dev, "%s: no valid device\n", __func__); 1639 ret = -ENODEV; 1640 goto err; 1641 } 1642 1643 msm_host->device_node = device_node; 1644 1645 if (of_property_read_bool(np, "syscon-sfpb")) { 1646 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, 1647 "syscon-sfpb"); 1648 if (IS_ERR(msm_host->sfpb)) { 1649 dev_err(dev, "%s: failed to get sfpb regmap\n", 1650 __func__); 1651 ret = PTR_ERR(msm_host->sfpb); 1652 } 1653 } 1654 1655 of_node_put(device_node); 1656 1657 err: 1658 of_node_put(endpoint); 1659 1660 return ret; 1661 } 1662 1663 int msm_dsi_host_init(struct msm_dsi *msm_dsi) 1664 { 1665 struct msm_dsi_host *msm_host = NULL; 1666 struct platform_device *pdev = msm_dsi->pdev; 1667 int ret; 1668 1669 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 1670 if (!msm_host) { 1671 pr_err("%s: FAILED: cannot alloc dsi host\n", 1672 __func__); 1673 ret = -ENOMEM; 1674 goto fail; 1675 } 1676 1677 msm_host->pdev = pdev; 1678 1679 ret = dsi_host_parse_dt(msm_host); 1680 if (ret) { 1681 pr_err("%s: failed to parse dt\n", __func__); 1682 goto fail; 1683 } 1684 1685 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL"); 1686 if (IS_ERR(msm_host->ctrl_base)) { 1687 pr_err("%s: unable to map Dsi ctrl base\n", __func__); 1688 ret = PTR_ERR(msm_host->ctrl_base); 1689 goto fail; 1690 } 1691 1692 msm_host->cfg_hnd = dsi_get_config(msm_host); 1693 if (!msm_host->cfg_hnd) { 1694 ret = -EINVAL; 1695 pr_err("%s: get config failed\n", __func__); 1696 goto fail; 1697 } 1698 1699 /* fixup base address by io offset */ 1700 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset; 1701 1702 ret = dsi_regulator_init(msm_host); 1703 if (ret) { 1704 pr_err("%s: regulator init failed\n", __func__); 1705 goto fail; 1706 } 1707 1708 ret = dsi_clk_init(msm_host); 1709 if (ret) { 1710 pr_err("%s: unable to initialize dsi clks\n", __func__); 1711 goto fail; 1712 } 1713 1714 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 1715 if (!msm_host->rx_buf) { 1716 pr_err("%s: alloc rx temp buf failed\n", __func__); 1717 goto fail; 1718 } 1719 1720 init_completion(&msm_host->dma_comp); 1721 init_completion(&msm_host->video_comp); 1722 mutex_init(&msm_host->dev_mutex); 1723 mutex_init(&msm_host->cmd_mutex); 1724 mutex_init(&msm_host->clk_mutex); 1725 spin_lock_init(&msm_host->intr_lock); 1726 1727 /* setup workqueue */ 1728 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 1729 INIT_WORK(&msm_host->err_work, dsi_err_worker); 1730 1731 msm_dsi->host = &msm_host->base; 1732 msm_dsi->id = msm_host->id; 1733 1734 DBG("Dsi Host %d initialized", msm_host->id); 1735 return 0; 1736 1737 fail: 1738 return ret; 1739 } 1740 1741 void msm_dsi_host_destroy(struct mipi_dsi_host *host) 1742 { 1743 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1744 1745 DBG(""); 1746 dsi_tx_buf_free(msm_host); 1747 if (msm_host->workqueue) { 1748 flush_workqueue(msm_host->workqueue); 1749 destroy_workqueue(msm_host->workqueue); 1750 msm_host->workqueue = NULL; 1751 } 1752 1753 mutex_destroy(&msm_host->clk_mutex); 1754 mutex_destroy(&msm_host->cmd_mutex); 1755 mutex_destroy(&msm_host->dev_mutex); 1756 } 1757 1758 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 1759 struct drm_device *dev) 1760 { 1761 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1762 struct platform_device *pdev = msm_host->pdev; 1763 int ret; 1764 1765 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1766 if (msm_host->irq < 0) { 1767 ret = msm_host->irq; 1768 dev_err(dev->dev, "failed to get irq: %d\n", ret); 1769 return ret; 1770 } 1771 1772 ret = devm_request_irq(&pdev->dev, msm_host->irq, 1773 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1774 "dsi_isr", msm_host); 1775 if (ret < 0) { 1776 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n", 1777 msm_host->irq, ret); 1778 return ret; 1779 } 1780 1781 msm_host->dev = dev; 1782 ret = dsi_tx_buf_alloc(msm_host, SZ_4K); 1783 if (ret) { 1784 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 1785 return ret; 1786 } 1787 1788 return 0; 1789 } 1790 1791 int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer) 1792 { 1793 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1794 int ret; 1795 1796 /* Register mipi dsi host */ 1797 if (!msm_host->registered) { 1798 host->dev = &msm_host->pdev->dev; 1799 host->ops = &dsi_host_ops; 1800 ret = mipi_dsi_host_register(host); 1801 if (ret) 1802 return ret; 1803 1804 msm_host->registered = true; 1805 1806 /* If the panel driver has not been probed after host register, 1807 * we should defer the host's probe. 1808 * It makes sure panel is connected when fbcon detects 1809 * connector status and gets the proper display mode to 1810 * create framebuffer. 1811 * Don't try to defer if there is nothing connected to the dsi 1812 * output 1813 */ 1814 if (check_defer && msm_host->device_node) { 1815 if (!of_drm_find_panel(msm_host->device_node)) 1816 if (!of_drm_find_bridge(msm_host->device_node)) 1817 return -EPROBE_DEFER; 1818 } 1819 } 1820 1821 return 0; 1822 } 1823 1824 void msm_dsi_host_unregister(struct mipi_dsi_host *host) 1825 { 1826 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1827 1828 if (msm_host->registered) { 1829 mipi_dsi_host_unregister(host); 1830 host->dev = NULL; 1831 host->ops = NULL; 1832 msm_host->registered = false; 1833 } 1834 } 1835 1836 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 1837 const struct mipi_dsi_msg *msg) 1838 { 1839 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1840 1841 /* TODO: make sure dsi_cmd_mdp is idle. 1842 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 1843 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 1844 * How to handle the old versions? Wait for mdp cmd done? 1845 */ 1846 1847 /* 1848 * mdss interrupt is generated in mdp core clock domain 1849 * mdp clock need to be enabled to receive dsi interrupt 1850 */ 1851 dsi_clk_ctrl(msm_host, 1); 1852 1853 /* TODO: vote for bus bandwidth */ 1854 1855 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 1856 dsi_set_tx_power_mode(0, msm_host); 1857 1858 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 1859 dsi_write(msm_host, REG_DSI_CTRL, 1860 msm_host->dma_cmd_ctrl_restore | 1861 DSI_CTRL_CMD_MODE_EN | 1862 DSI_CTRL_ENABLE); 1863 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 1864 1865 return 0; 1866 } 1867 1868 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 1869 const struct mipi_dsi_msg *msg) 1870 { 1871 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1872 1873 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 1874 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 1875 1876 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 1877 dsi_set_tx_power_mode(1, msm_host); 1878 1879 /* TODO: unvote for bus bandwidth */ 1880 1881 dsi_clk_ctrl(msm_host, 0); 1882 } 1883 1884 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 1885 const struct mipi_dsi_msg *msg) 1886 { 1887 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1888 1889 return dsi_cmds2buf_tx(msm_host, msg); 1890 } 1891 1892 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 1893 const struct mipi_dsi_msg *msg) 1894 { 1895 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1896 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1897 int data_byte, rx_byte, dlen, end; 1898 int short_response, diff, pkt_size, ret = 0; 1899 char cmd; 1900 int rlen = msg->rx_len; 1901 u8 *buf; 1902 1903 if (rlen <= 2) { 1904 short_response = 1; 1905 pkt_size = rlen; 1906 rx_byte = 4; 1907 } else { 1908 short_response = 0; 1909 data_byte = 10; /* first read */ 1910 if (rlen < data_byte) 1911 pkt_size = rlen; 1912 else 1913 pkt_size = data_byte; 1914 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 1915 } 1916 1917 buf = msm_host->rx_buf; 1918 end = 0; 1919 while (!end) { 1920 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 1921 struct mipi_dsi_msg max_pkt_size_msg = { 1922 .channel = msg->channel, 1923 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 1924 .tx_len = 2, 1925 .tx_buf = tx, 1926 }; 1927 1928 DBG("rlen=%d pkt_size=%d rx_byte=%d", 1929 rlen, pkt_size, rx_byte); 1930 1931 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 1932 if (ret < 2) { 1933 pr_err("%s: Set max pkt size failed, %d\n", 1934 __func__, ret); 1935 return -EINVAL; 1936 } 1937 1938 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 1939 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 1940 /* Clear the RDBK_DATA registers */ 1941 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 1942 DSI_RDBK_DATA_CTRL_CLR); 1943 wmb(); /* make sure the RDBK registers are cleared */ 1944 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 1945 wmb(); /* release cleared status before transfer */ 1946 } 1947 1948 ret = dsi_cmds2buf_tx(msm_host, msg); 1949 if (ret < msg->tx_len) { 1950 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 1951 return ret; 1952 } 1953 1954 /* 1955 * once cmd_dma_done interrupt received, 1956 * return data from client is ready and stored 1957 * at RDBK_DATA register already 1958 * since rx fifo is 16 bytes, dcs header is kept at first loop, 1959 * after that dcs header lost during shift into registers 1960 */ 1961 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 1962 1963 if (dlen <= 0) 1964 return 0; 1965 1966 if (short_response) 1967 break; 1968 1969 if (rlen <= data_byte) { 1970 diff = data_byte - rlen; 1971 end = 1; 1972 } else { 1973 diff = 0; 1974 rlen -= data_byte; 1975 } 1976 1977 if (!end) { 1978 dlen -= 2; /* 2 crc */ 1979 dlen -= diff; 1980 buf += dlen; /* next start position */ 1981 data_byte = 14; /* NOT first read */ 1982 if (rlen < data_byte) 1983 pkt_size += rlen; 1984 else 1985 pkt_size += data_byte; 1986 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 1987 } 1988 } 1989 1990 /* 1991 * For single Long read, if the requested rlen < 10, 1992 * we need to shift the start position of rx 1993 * data buffer to skip the bytes which are not 1994 * updated. 1995 */ 1996 if (pkt_size < 10 && !short_response) 1997 buf = msm_host->rx_buf + (10 - rlen); 1998 else 1999 buf = msm_host->rx_buf; 2000 2001 cmd = buf[0]; 2002 switch (cmd) { 2003 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 2004 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 2005 ret = 0; 2006 break; 2007 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 2008 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 2009 ret = dsi_short_read1_resp(buf, msg); 2010 break; 2011 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 2012 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 2013 ret = dsi_short_read2_resp(buf, msg); 2014 break; 2015 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 2016 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 2017 ret = dsi_long_read_resp(buf, msg); 2018 break; 2019 default: 2020 pr_warn("%s:Invalid response cmd\n", __func__); 2021 ret = 0; 2022 } 2023 2024 return ret; 2025 } 2026 2027 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, 2028 u32 len) 2029 { 2030 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2031 2032 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); 2033 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 2034 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 2035 2036 /* Make sure trigger happens */ 2037 wmb(); 2038 } 2039 2040 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, 2041 struct msm_dsi_pll *src_pll) 2042 { 2043 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2044 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2045 struct clk *byte_clk_provider, *pixel_clk_provider; 2046 int ret; 2047 2048 ret = msm_dsi_pll_get_clk_provider(src_pll, 2049 &byte_clk_provider, &pixel_clk_provider); 2050 if (ret) { 2051 pr_info("%s: can't get provider from pll, don't set parent\n", 2052 __func__); 2053 return 0; 2054 } 2055 2056 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider); 2057 if (ret) { 2058 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n", 2059 __func__, ret); 2060 goto exit; 2061 } 2062 2063 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider); 2064 if (ret) { 2065 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n", 2066 __func__, ret); 2067 goto exit; 2068 } 2069 2070 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) { 2071 ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider); 2072 if (ret) { 2073 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n", 2074 __func__, ret); 2075 goto exit; 2076 } 2077 2078 ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider); 2079 if (ret) { 2080 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n", 2081 __func__, ret); 2082 goto exit; 2083 } 2084 } 2085 2086 exit: 2087 return ret; 2088 } 2089 2090 int msm_dsi_host_enable(struct mipi_dsi_host *host) 2091 { 2092 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2093 2094 dsi_op_mode_config(msm_host, 2095 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 2096 2097 /* TODO: clock should be turned off for command mode, 2098 * and only turned on before MDP START. 2099 * This part of code should be enabled once mdp driver support it. 2100 */ 2101 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) 2102 dsi_clk_ctrl(msm_host, 0); */ 2103 2104 return 0; 2105 } 2106 2107 int msm_dsi_host_disable(struct mipi_dsi_host *host) 2108 { 2109 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2110 2111 dsi_op_mode_config(msm_host, 2112 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 2113 2114 /* Since we have disabled INTF, the video engine won't stop so that 2115 * the cmd engine will be blocked. 2116 * Reset to disable video engine so that we can send off cmd. 2117 */ 2118 dsi_sw_reset(msm_host); 2119 2120 return 0; 2121 } 2122 2123 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) 2124 { 2125 enum sfpb_ahb_arb_master_port_en en; 2126 2127 if (!msm_host->sfpb) 2128 return; 2129 2130 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; 2131 2132 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, 2133 SFPB_GPREG_MASTER_PORT_EN__MASK, 2134 SFPB_GPREG_MASTER_PORT_EN(en)); 2135 } 2136 2137 int msm_dsi_host_power_on(struct mipi_dsi_host *host) 2138 { 2139 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2140 u32 clk_pre = 0, clk_post = 0; 2141 int ret = 0; 2142 2143 mutex_lock(&msm_host->dev_mutex); 2144 if (msm_host->power_on) { 2145 DBG("dsi host already on"); 2146 goto unlock_ret; 2147 } 2148 2149 msm_dsi_sfpb_config(msm_host, true); 2150 2151 ret = dsi_calc_clk_rate(msm_host); 2152 if (ret) { 2153 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 2154 goto unlock_ret; 2155 } 2156 2157 ret = dsi_host_regulator_enable(msm_host); 2158 if (ret) { 2159 pr_err("%s:Failed to enable vregs.ret=%d\n", 2160 __func__, ret); 2161 goto unlock_ret; 2162 } 2163 2164 ret = dsi_bus_clk_enable(msm_host); 2165 if (ret) { 2166 pr_err("%s: failed to enable bus clocks, %d\n", __func__, ret); 2167 goto fail_disable_reg; 2168 } 2169 2170 dsi_phy_sw_reset(msm_host); 2171 ret = msm_dsi_manager_phy_enable(msm_host->id, 2172 msm_host->byte_clk_rate * 8, 2173 msm_host->esc_clk_rate, 2174 &clk_pre, &clk_post); 2175 dsi_bus_clk_disable(msm_host); 2176 if (ret) { 2177 pr_err("%s: failed to enable phy, %d\n", __func__, ret); 2178 goto fail_disable_reg; 2179 } 2180 2181 ret = dsi_clk_ctrl(msm_host, 1); 2182 if (ret) { 2183 pr_err("%s: failed to enable clocks. ret=%d\n", __func__, ret); 2184 goto fail_disable_reg; 2185 } 2186 2187 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); 2188 if (ret) { 2189 pr_err("%s: failed to set pinctrl default state, %d\n", 2190 __func__, ret); 2191 goto fail_disable_clk; 2192 } 2193 2194 dsi_timing_setup(msm_host); 2195 dsi_sw_reset(msm_host); 2196 dsi_ctrl_config(msm_host, true, clk_pre, clk_post); 2197 2198 if (msm_host->disp_en_gpio) 2199 gpiod_set_value(msm_host->disp_en_gpio, 1); 2200 2201 msm_host->power_on = true; 2202 mutex_unlock(&msm_host->dev_mutex); 2203 2204 return 0; 2205 2206 fail_disable_clk: 2207 dsi_clk_ctrl(msm_host, 0); 2208 fail_disable_reg: 2209 dsi_host_regulator_disable(msm_host); 2210 unlock_ret: 2211 mutex_unlock(&msm_host->dev_mutex); 2212 return ret; 2213 } 2214 2215 int msm_dsi_host_power_off(struct mipi_dsi_host *host) 2216 { 2217 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2218 2219 mutex_lock(&msm_host->dev_mutex); 2220 if (!msm_host->power_on) { 2221 DBG("dsi host already off"); 2222 goto unlock_ret; 2223 } 2224 2225 dsi_ctrl_config(msm_host, false, 0, 0); 2226 2227 if (msm_host->disp_en_gpio) 2228 gpiod_set_value(msm_host->disp_en_gpio, 0); 2229 2230 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); 2231 2232 msm_dsi_manager_phy_disable(msm_host->id); 2233 2234 dsi_clk_ctrl(msm_host, 0); 2235 2236 dsi_host_regulator_disable(msm_host); 2237 2238 msm_dsi_sfpb_config(msm_host, false); 2239 2240 DBG("-"); 2241 2242 msm_host->power_on = false; 2243 2244 unlock_ret: 2245 mutex_unlock(&msm_host->dev_mutex); 2246 return 0; 2247 } 2248 2249 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 2250 struct drm_display_mode *mode) 2251 { 2252 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2253 2254 if (msm_host->mode) { 2255 drm_mode_destroy(msm_host->dev, msm_host->mode); 2256 msm_host->mode = NULL; 2257 } 2258 2259 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 2260 if (IS_ERR(msm_host->mode)) { 2261 pr_err("%s: cannot duplicate mode\n", __func__); 2262 return PTR_ERR(msm_host->mode); 2263 } 2264 2265 return 0; 2266 } 2267 2268 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host, 2269 unsigned long *panel_flags) 2270 { 2271 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2272 struct drm_panel *panel; 2273 2274 panel = of_drm_find_panel(msm_host->device_node); 2275 if (panel_flags) 2276 *panel_flags = msm_host->mode_flags; 2277 2278 return panel; 2279 } 2280 2281 struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host) 2282 { 2283 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2284 2285 return of_drm_find_bridge(msm_host->device_node); 2286 } 2287