1 #ifndef DSI_XML 2 #define DSI_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 13 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) 14 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24) 15 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24) 16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57) 17 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07) 18 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) 19 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) 20 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) 21 - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14) 22 23 Copyright (C) 2013-2015 by the following authors: 24 - Rob Clark <robdclark@gmail.com> (robclark) 25 26 Permission is hereby granted, free of charge, to any person obtaining 27 a copy of this software and associated documentation files (the 28 "Software"), to deal in the Software without restriction, including 29 without limitation the rights to use, copy, modify, merge, publish, 30 distribute, sublicense, and/or sell copies of the Software, and to 31 permit persons to whom the Software is furnished to do so, subject to 32 the following conditions: 33 34 The above copyright notice and this permission notice (including the 35 next paragraph) shall be included in all copies or substantial 36 portions of the Software. 37 38 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 40 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 41 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 42 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 43 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 44 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 45 */ 46 47 48 enum dsi_traffic_mode { 49 NON_BURST_SYNCH_PULSE = 0, 50 NON_BURST_SYNCH_EVENT = 1, 51 BURST_MODE = 2, 52 }; 53 54 enum dsi_vid_dst_format { 55 VID_DST_FORMAT_RGB565 = 0, 56 VID_DST_FORMAT_RGB666 = 1, 57 VID_DST_FORMAT_RGB666_LOOSE = 2, 58 VID_DST_FORMAT_RGB888 = 3, 59 }; 60 61 enum dsi_rgb_swap { 62 SWAP_RGB = 0, 63 SWAP_RBG = 1, 64 SWAP_BGR = 2, 65 SWAP_BRG = 3, 66 SWAP_GRB = 4, 67 SWAP_GBR = 5, 68 }; 69 70 enum dsi_cmd_trigger { 71 TRIGGER_NONE = 0, 72 TRIGGER_SEOF = 1, 73 TRIGGER_TE = 2, 74 TRIGGER_SW = 4, 75 TRIGGER_SW_SEOF = 5, 76 TRIGGER_SW_TE = 6, 77 }; 78 79 enum dsi_cmd_dst_format { 80 CMD_DST_FORMAT_RGB111 = 0, 81 CMD_DST_FORMAT_RGB332 = 3, 82 CMD_DST_FORMAT_RGB444 = 4, 83 CMD_DST_FORMAT_RGB565 = 6, 84 CMD_DST_FORMAT_RGB666 = 7, 85 CMD_DST_FORMAT_RGB888 = 8, 86 }; 87 88 enum dsi_lane_swap { 89 LANE_SWAP_0123 = 0, 90 LANE_SWAP_3012 = 1, 91 LANE_SWAP_2301 = 2, 92 LANE_SWAP_1230 = 3, 93 LANE_SWAP_0321 = 4, 94 LANE_SWAP_1032 = 5, 95 LANE_SWAP_2103 = 6, 96 LANE_SWAP_3210 = 7, 97 }; 98 99 #define DSI_IRQ_CMD_DMA_DONE 0x00000001 100 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002 101 #define DSI_IRQ_CMD_MDP_DONE 0x00000100 102 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200 103 #define DSI_IRQ_VIDEO_DONE 0x00010000 104 #define DSI_IRQ_MASK_VIDEO_DONE 0x00020000 105 #define DSI_IRQ_BTA_DONE 0x00100000 106 #define DSI_IRQ_MASK_BTA_DONE 0x00200000 107 #define DSI_IRQ_ERROR 0x01000000 108 #define DSI_IRQ_MASK_ERROR 0x02000000 109 #define REG_DSI_6G_HW_VERSION 0x00000000 110 #define DSI_6G_HW_VERSION_MAJOR__MASK 0xf0000000 111 #define DSI_6G_HW_VERSION_MAJOR__SHIFT 28 112 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) 113 { 114 return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK; 115 } 116 #define DSI_6G_HW_VERSION_MINOR__MASK 0x0fff0000 117 #define DSI_6G_HW_VERSION_MINOR__SHIFT 16 118 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) 119 { 120 return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK; 121 } 122 #define DSI_6G_HW_VERSION_STEP__MASK 0x0000ffff 123 #define DSI_6G_HW_VERSION_STEP__SHIFT 0 124 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) 125 { 126 return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK; 127 } 128 129 #define REG_DSI_CTRL 0x00000000 130 #define DSI_CTRL_ENABLE 0x00000001 131 #define DSI_CTRL_VID_MODE_EN 0x00000002 132 #define DSI_CTRL_CMD_MODE_EN 0x00000004 133 #define DSI_CTRL_LANE0 0x00000010 134 #define DSI_CTRL_LANE1 0x00000020 135 #define DSI_CTRL_LANE2 0x00000040 136 #define DSI_CTRL_LANE3 0x00000080 137 #define DSI_CTRL_CLK_EN 0x00000100 138 #define DSI_CTRL_ECC_CHECK 0x00100000 139 #define DSI_CTRL_CRC_CHECK 0x01000000 140 141 #define REG_DSI_STATUS0 0x00000004 142 #define DSI_STATUS0_CMD_MODE_ENGINE_BUSY 0x00000001 143 #define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002 144 #define DSI_STATUS0_CMD_MODE_MDP_BUSY 0x00000004 145 #define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008 146 #define DSI_STATUS0_DSI_BUSY 0x00000010 147 #define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000 148 149 #define REG_DSI_FIFO_STATUS 0x00000008 150 #define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080 151 152 #define REG_DSI_VID_CFG0 0x0000000c 153 #define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003 154 #define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0 155 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) 156 { 157 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK; 158 } 159 #define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030 160 #define DSI_VID_CFG0_DST_FORMAT__SHIFT 4 161 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) 162 { 163 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; 164 } 165 #define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300 166 #define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT 8 167 static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) 168 { 169 return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK; 170 } 171 #define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000 172 #define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000 173 #define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000 174 #define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000 175 #define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000 176 #define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000 177 178 #define REG_DSI_VID_CFG1 0x0000001c 179 #define DSI_VID_CFG1_R_SEL 0x00000001 180 #define DSI_VID_CFG1_G_SEL 0x00000010 181 #define DSI_VID_CFG1_B_SEL 0x00000100 182 #define DSI_VID_CFG1_RGB_SWAP__MASK 0x00007000 183 #define DSI_VID_CFG1_RGB_SWAP__SHIFT 12 184 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) 185 { 186 return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK; 187 } 188 189 #define REG_DSI_ACTIVE_H 0x00000020 190 #define DSI_ACTIVE_H_START__MASK 0x00000fff 191 #define DSI_ACTIVE_H_START__SHIFT 0 192 static inline uint32_t DSI_ACTIVE_H_START(uint32_t val) 193 { 194 return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK; 195 } 196 #define DSI_ACTIVE_H_END__MASK 0x0fff0000 197 #define DSI_ACTIVE_H_END__SHIFT 16 198 static inline uint32_t DSI_ACTIVE_H_END(uint32_t val) 199 { 200 return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK; 201 } 202 203 #define REG_DSI_ACTIVE_V 0x00000024 204 #define DSI_ACTIVE_V_START__MASK 0x00000fff 205 #define DSI_ACTIVE_V_START__SHIFT 0 206 static inline uint32_t DSI_ACTIVE_V_START(uint32_t val) 207 { 208 return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK; 209 } 210 #define DSI_ACTIVE_V_END__MASK 0x0fff0000 211 #define DSI_ACTIVE_V_END__SHIFT 16 212 static inline uint32_t DSI_ACTIVE_V_END(uint32_t val) 213 { 214 return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK; 215 } 216 217 #define REG_DSI_TOTAL 0x00000028 218 #define DSI_TOTAL_H_TOTAL__MASK 0x00000fff 219 #define DSI_TOTAL_H_TOTAL__SHIFT 0 220 static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val) 221 { 222 return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK; 223 } 224 #define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000 225 #define DSI_TOTAL_V_TOTAL__SHIFT 16 226 static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val) 227 { 228 return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK; 229 } 230 231 #define REG_DSI_ACTIVE_HSYNC 0x0000002c 232 #define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff 233 #define DSI_ACTIVE_HSYNC_START__SHIFT 0 234 static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val) 235 { 236 return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK; 237 } 238 #define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000 239 #define DSI_ACTIVE_HSYNC_END__SHIFT 16 240 static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val) 241 { 242 return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK; 243 } 244 245 #define REG_DSI_ACTIVE_VSYNC_HPOS 0x00000030 246 #define DSI_ACTIVE_VSYNC_HPOS_START__MASK 0x00000fff 247 #define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT 0 248 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val) 249 { 250 return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK; 251 } 252 #define DSI_ACTIVE_VSYNC_HPOS_END__MASK 0x0fff0000 253 #define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT 16 254 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val) 255 { 256 return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK; 257 } 258 259 #define REG_DSI_ACTIVE_VSYNC_VPOS 0x00000034 260 #define DSI_ACTIVE_VSYNC_VPOS_START__MASK 0x00000fff 261 #define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT 0 262 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val) 263 { 264 return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK; 265 } 266 #define DSI_ACTIVE_VSYNC_VPOS_END__MASK 0x0fff0000 267 #define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT 16 268 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val) 269 { 270 return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK; 271 } 272 273 #define REG_DSI_CMD_DMA_CTRL 0x00000038 274 #define DSI_CMD_DMA_CTRL_BROADCAST_EN 0x80000000 275 #define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000 276 #define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000 277 278 #define REG_DSI_CMD_CFG0 0x0000003c 279 #define DSI_CMD_CFG0_DST_FORMAT__MASK 0x0000000f 280 #define DSI_CMD_CFG0_DST_FORMAT__SHIFT 0 281 static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val) 282 { 283 return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK; 284 } 285 #define DSI_CMD_CFG0_R_SEL 0x00000010 286 #define DSI_CMD_CFG0_G_SEL 0x00000100 287 #define DSI_CMD_CFG0_B_SEL 0x00001000 288 #define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK 0x00f00000 289 #define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT 20 290 static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val) 291 { 292 return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK; 293 } 294 #define DSI_CMD_CFG0_RGB_SWAP__MASK 0x00070000 295 #define DSI_CMD_CFG0_RGB_SWAP__SHIFT 16 296 static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val) 297 { 298 return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK; 299 } 300 301 #define REG_DSI_CMD_CFG1 0x00000040 302 #define DSI_CMD_CFG1_WR_MEM_START__MASK 0x000000ff 303 #define DSI_CMD_CFG1_WR_MEM_START__SHIFT 0 304 static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val) 305 { 306 return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK; 307 } 308 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK 0x0000ff00 309 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT 8 310 static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val) 311 { 312 return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK; 313 } 314 #define DSI_CMD_CFG1_INSERT_DCS_COMMAND 0x00010000 315 316 #define REG_DSI_DMA_BASE 0x00000044 317 318 #define REG_DSI_DMA_LEN 0x00000048 319 320 #define REG_DSI_CMD_MDP_STREAM_CTRL 0x00000054 321 #define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK 0x0000003f 322 #define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT 0 323 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val) 324 { 325 return ((val) << DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK; 326 } 327 #define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 328 #define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT 8 329 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val) 330 { 331 return ((val) << DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK; 332 } 333 #define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK 0xffff0000 334 #define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT 16 335 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val) 336 { 337 return ((val) << DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK; 338 } 339 340 #define REG_DSI_CMD_MDP_STREAM_TOTAL 0x00000058 341 #define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK 0x00000fff 342 #define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT 0 343 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val) 344 { 345 return ((val) << DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK; 346 } 347 #define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK 0x0fff0000 348 #define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT 16 349 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val) 350 { 351 return ((val) << DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK; 352 } 353 354 #define REG_DSI_ACK_ERR_STATUS 0x00000064 355 356 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } 357 358 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } 359 360 #define REG_DSI_TRIG_CTRL 0x00000080 361 #define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x00000007 362 #define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0 363 static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val) 364 { 365 return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK; 366 } 367 #define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x00000070 368 #define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT 4 369 static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val) 370 { 371 return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK; 372 } 373 #define DSI_TRIG_CTRL_STREAM__MASK 0x00000300 374 #define DSI_TRIG_CTRL_STREAM__SHIFT 8 375 static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val) 376 { 377 return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK; 378 } 379 #define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME 0x00001000 380 #define DSI_TRIG_CTRL_TE 0x80000000 381 382 #define REG_DSI_TRIG_DMA 0x0000008c 383 384 #define REG_DSI_DLN0_PHY_ERR 0x000000b0 385 #define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC 0x00000001 386 #define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC 0x00000010 387 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL 0x00000100 388 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000 389 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000 390 391 #define REG_DSI_TIMEOUT_STATUS 0x000000bc 392 393 #define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0 394 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f 395 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0 396 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val) 397 { 398 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK; 399 } 400 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00 401 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT 8 402 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) 403 { 404 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK; 405 } 406 407 #define REG_DSI_EOT_PACKET_CTRL 0x000000c8 408 #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001 409 #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010 410 411 #define REG_DSI_LANE_CTRL 0x000000a8 412 #define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000 413 414 #define REG_DSI_LANE_SWAP_CTRL 0x000000ac 415 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007 416 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0 417 static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val) 418 { 419 return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK; 420 } 421 422 #define REG_DSI_ERR_INT_MASK0 0x00000108 423 424 #define REG_DSI_INTR_CTRL 0x0000010c 425 426 #define REG_DSI_RESET 0x00000114 427 428 #define REG_DSI_CLK_CTRL 0x00000118 429 #define DSI_CLK_CTRL_AHBS_HCLK_ON 0x00000001 430 #define DSI_CLK_CTRL_AHBM_SCLK_ON 0x00000002 431 #define DSI_CLK_CTRL_PCLK_ON 0x00000004 432 #define DSI_CLK_CTRL_DSICLK_ON 0x00000008 433 #define DSI_CLK_CTRL_BYTECLK_ON 0x00000010 434 #define DSI_CLK_CTRL_ESCCLK_ON 0x00000020 435 #define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200 436 437 #define REG_DSI_CLK_STATUS 0x0000011c 438 #define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000 439 440 #define REG_DSI_PHY_RESET 0x00000128 441 #define DSI_PHY_RESET_RESET 0x00000001 442 443 #define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c 444 #define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001 445 446 #define REG_DSI_RDBK_DATA_CTRL 0x000001d0 447 #define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000 448 #define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16 449 static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val) 450 { 451 return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK; 452 } 453 #define DSI_RDBK_DATA_CTRL_CLR 0x00000001 454 455 #define REG_DSI_VERSION 0x000001f0 456 #define DSI_VERSION_MAJOR__MASK 0xff000000 457 #define DSI_VERSION_MAJOR__SHIFT 24 458 static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) 459 { 460 return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK; 461 } 462 463 #define REG_DSI_PHY_PLL_CTRL_0 0x00000200 464 #define DSI_PHY_PLL_CTRL_0_ENABLE 0x00000001 465 466 #define REG_DSI_PHY_PLL_CTRL_1 0x00000204 467 468 #define REG_DSI_PHY_PLL_CTRL_2 0x00000208 469 470 #define REG_DSI_PHY_PLL_CTRL_3 0x0000020c 471 472 #define REG_DSI_PHY_PLL_CTRL_4 0x00000210 473 474 #define REG_DSI_PHY_PLL_CTRL_5 0x00000214 475 476 #define REG_DSI_PHY_PLL_CTRL_6 0x00000218 477 478 #define REG_DSI_PHY_PLL_CTRL_7 0x0000021c 479 480 #define REG_DSI_PHY_PLL_CTRL_8 0x00000220 481 482 #define REG_DSI_PHY_PLL_CTRL_9 0x00000224 483 484 #define REG_DSI_PHY_PLL_CTRL_10 0x00000228 485 486 #define REG_DSI_PHY_PLL_CTRL_11 0x0000022c 487 488 #define REG_DSI_PHY_PLL_CTRL_12 0x00000230 489 490 #define REG_DSI_PHY_PLL_CTRL_13 0x00000234 491 492 #define REG_DSI_PHY_PLL_CTRL_14 0x00000238 493 494 #define REG_DSI_PHY_PLL_CTRL_15 0x0000023c 495 496 #define REG_DSI_PHY_PLL_CTRL_16 0x00000240 497 498 #define REG_DSI_PHY_PLL_CTRL_17 0x00000244 499 500 #define REG_DSI_PHY_PLL_CTRL_18 0x00000248 501 502 #define REG_DSI_PHY_PLL_CTRL_19 0x0000024c 503 504 #define REG_DSI_PHY_PLL_CTRL_20 0x00000250 505 506 #define REG_DSI_PHY_PLL_STATUS 0x00000280 507 #define DSI_PHY_PLL_STATUS_PLL_BUSY 0x00000001 508 509 #define REG_DSI_8x60_PHY_TPA_CTRL_1 0x00000258 510 511 #define REG_DSI_8x60_PHY_TPA_CTRL_2 0x0000025c 512 513 #define REG_DSI_8x60_PHY_TIMING_CTRL_0 0x00000260 514 515 #define REG_DSI_8x60_PHY_TIMING_CTRL_1 0x00000264 516 517 #define REG_DSI_8x60_PHY_TIMING_CTRL_2 0x00000268 518 519 #define REG_DSI_8x60_PHY_TIMING_CTRL_3 0x0000026c 520 521 #define REG_DSI_8x60_PHY_TIMING_CTRL_4 0x00000270 522 523 #define REG_DSI_8x60_PHY_TIMING_CTRL_5 0x00000274 524 525 #define REG_DSI_8x60_PHY_TIMING_CTRL_6 0x00000278 526 527 #define REG_DSI_8x60_PHY_TIMING_CTRL_7 0x0000027c 528 529 #define REG_DSI_8x60_PHY_TIMING_CTRL_8 0x00000280 530 531 #define REG_DSI_8x60_PHY_TIMING_CTRL_9 0x00000284 532 533 #define REG_DSI_8x60_PHY_TIMING_CTRL_10 0x00000288 534 535 #define REG_DSI_8x60_PHY_TIMING_CTRL_11 0x0000028c 536 537 #define REG_DSI_8x60_PHY_CTRL_0 0x00000290 538 539 #define REG_DSI_8x60_PHY_CTRL_1 0x00000294 540 541 #define REG_DSI_8x60_PHY_CTRL_2 0x00000298 542 543 #define REG_DSI_8x60_PHY_CTRL_3 0x0000029c 544 545 #define REG_DSI_8x60_PHY_STRENGTH_0 0x000002a0 546 547 #define REG_DSI_8x60_PHY_STRENGTH_1 0x000002a4 548 549 #define REG_DSI_8x60_PHY_STRENGTH_2 0x000002a8 550 551 #define REG_DSI_8x60_PHY_STRENGTH_3 0x000002ac 552 553 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_0 0x000002cc 554 555 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_1 0x000002d0 556 557 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_2 0x000002d4 558 559 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_3 0x000002d8 560 561 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_4 0x000002dc 562 563 #define REG_DSI_8x60_PHY_CAL_HW_TRIGGER 0x000000f0 564 565 #define REG_DSI_8x60_PHY_CAL_CTRL 0x000000f4 566 567 #define REG_DSI_8x60_PHY_CAL_STATUS 0x000000fc 568 #define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY 0x10000000 569 570 static inline uint32_t REG_DSI_8960_LN(uint32_t i0) { return 0x00000300 + 0x40*i0; } 571 572 static inline uint32_t REG_DSI_8960_LN_CFG_0(uint32_t i0) { return 0x00000300 + 0x40*i0; } 573 574 static inline uint32_t REG_DSI_8960_LN_CFG_1(uint32_t i0) { return 0x00000304 + 0x40*i0; } 575 576 static inline uint32_t REG_DSI_8960_LN_CFG_2(uint32_t i0) { return 0x00000308 + 0x40*i0; } 577 578 static inline uint32_t REG_DSI_8960_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000030c + 0x40*i0; } 579 580 static inline uint32_t REG_DSI_8960_LN_TEST_STR_0(uint32_t i0) { return 0x00000314 + 0x40*i0; } 581 582 static inline uint32_t REG_DSI_8960_LN_TEST_STR_1(uint32_t i0) { return 0x00000318 + 0x40*i0; } 583 584 #define REG_DSI_8960_PHY_LNCK_CFG_0 0x00000400 585 586 #define REG_DSI_8960_PHY_LNCK_CFG_1 0x00000404 587 588 #define REG_DSI_8960_PHY_LNCK_CFG_2 0x00000408 589 590 #define REG_DSI_8960_PHY_LNCK_TEST_DATAPATH 0x0000040c 591 592 #define REG_DSI_8960_PHY_LNCK_TEST_STR0 0x00000414 593 594 #define REG_DSI_8960_PHY_LNCK_TEST_STR1 0x00000418 595 596 #define REG_DSI_8960_PHY_TIMING_CTRL_0 0x00000440 597 598 #define REG_DSI_8960_PHY_TIMING_CTRL_1 0x00000444 599 600 #define REG_DSI_8960_PHY_TIMING_CTRL_2 0x00000448 601 602 #define REG_DSI_8960_PHY_TIMING_CTRL_3 0x0000044c 603 604 #define REG_DSI_8960_PHY_TIMING_CTRL_4 0x00000450 605 606 #define REG_DSI_8960_PHY_TIMING_CTRL_5 0x00000454 607 608 #define REG_DSI_8960_PHY_TIMING_CTRL_6 0x00000458 609 610 #define REG_DSI_8960_PHY_TIMING_CTRL_7 0x0000045c 611 612 #define REG_DSI_8960_PHY_TIMING_CTRL_8 0x00000460 613 614 #define REG_DSI_8960_PHY_TIMING_CTRL_9 0x00000464 615 616 #define REG_DSI_8960_PHY_TIMING_CTRL_10 0x00000468 617 618 #define REG_DSI_8960_PHY_TIMING_CTRL_11 0x0000046c 619 620 #define REG_DSI_8960_PHY_CTRL_0 0x00000470 621 622 #define REG_DSI_8960_PHY_CTRL_1 0x00000474 623 624 #define REG_DSI_8960_PHY_CTRL_2 0x00000478 625 626 #define REG_DSI_8960_PHY_CTRL_3 0x0000047c 627 628 #define REG_DSI_8960_PHY_STRENGTH_0 0x00000480 629 630 #define REG_DSI_8960_PHY_STRENGTH_1 0x00000484 631 632 #define REG_DSI_8960_PHY_STRENGTH_2 0x00000488 633 634 #define REG_DSI_8960_PHY_BIST_CTRL_0 0x0000048c 635 636 #define REG_DSI_8960_PHY_BIST_CTRL_1 0x00000490 637 638 #define REG_DSI_8960_PHY_BIST_CTRL_2 0x00000494 639 640 #define REG_DSI_8960_PHY_BIST_CTRL_3 0x00000498 641 642 #define REG_DSI_8960_PHY_BIST_CTRL_4 0x0000049c 643 644 #define REG_DSI_8960_PHY_LDO_CTRL 0x000004b0 645 646 #define REG_DSI_8960_PHY_REGULATOR_CTRL_0 0x00000500 647 648 #define REG_DSI_8960_PHY_REGULATOR_CTRL_1 0x00000504 649 650 #define REG_DSI_8960_PHY_REGULATOR_CTRL_2 0x00000508 651 652 #define REG_DSI_8960_PHY_REGULATOR_CTRL_3 0x0000050c 653 654 #define REG_DSI_8960_PHY_REGULATOR_CTRL_4 0x00000510 655 656 #define REG_DSI_8960_PHY_REGULATOR_CAL_PWR_CFG 0x00000518 657 658 #define REG_DSI_8960_PHY_CAL_HW_TRIGGER 0x00000528 659 660 #define REG_DSI_8960_PHY_CAL_SW_CFG_0 0x0000052c 661 662 #define REG_DSI_8960_PHY_CAL_SW_CFG_1 0x00000530 663 664 #define REG_DSI_8960_PHY_CAL_SW_CFG_2 0x00000534 665 666 #define REG_DSI_8960_PHY_CAL_HW_CFG_0 0x00000538 667 668 #define REG_DSI_8960_PHY_CAL_HW_CFG_1 0x0000053c 669 670 #define REG_DSI_8960_PHY_CAL_HW_CFG_2 0x00000540 671 672 #define REG_DSI_8960_PHY_CAL_HW_CFG_3 0x00000544 673 674 #define REG_DSI_8960_PHY_CAL_HW_CFG_4 0x00000548 675 676 #define REG_DSI_8960_PHY_CAL_STATUS 0x00000550 677 #define DSI_8960_PHY_CAL_STATUS_CAL_BUSY 0x00000010 678 679 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } 680 681 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } 682 683 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } 684 685 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } 686 687 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } 688 689 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } 690 691 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } 692 693 static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } 694 695 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } 696 697 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } 698 699 #define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100 700 701 #define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104 702 703 #define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108 704 705 #define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c 706 707 #define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110 708 709 #define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114 710 711 #define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118 712 713 #define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c 714 715 #define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120 716 717 #define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140 718 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff 719 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 720 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) 721 { 722 return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; 723 } 724 725 #define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144 726 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff 727 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 728 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) 729 { 730 return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; 731 } 732 733 #define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148 734 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff 735 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 736 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) 737 { 738 return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; 739 } 740 741 #define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c 742 #define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001 743 744 #define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150 745 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff 746 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 747 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) 748 { 749 return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; 750 } 751 752 #define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154 753 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff 754 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 755 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) 756 { 757 return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; 758 } 759 760 #define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158 761 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff 762 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 763 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) 764 { 765 return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; 766 } 767 768 #define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c 769 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff 770 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 771 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) 772 { 773 return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; 774 } 775 776 #define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160 777 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff 778 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 779 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) 780 { 781 return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; 782 } 783 784 #define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164 785 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 786 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 787 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) 788 { 789 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK; 790 } 791 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 792 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 793 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) 794 { 795 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; 796 } 797 798 #define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168 799 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 800 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 801 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) 802 { 803 return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK; 804 } 805 806 #define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c 807 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff 808 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 809 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) 810 { 811 return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; 812 } 813 814 #define REG_DSI_28nm_PHY_CTRL_0 0x00000170 815 816 #define REG_DSI_28nm_PHY_CTRL_1 0x00000174 817 818 #define REG_DSI_28nm_PHY_CTRL_2 0x00000178 819 820 #define REG_DSI_28nm_PHY_CTRL_3 0x0000017c 821 822 #define REG_DSI_28nm_PHY_CTRL_4 0x00000180 823 824 #define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184 825 826 #define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188 827 828 #define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4 829 830 #define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8 831 832 #define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc 833 834 #define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0 835 836 #define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4 837 838 #define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8 839 840 #define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4 841 #define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001 842 843 #define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc 844 845 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000 846 847 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004 848 849 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008 850 851 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c 852 853 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010 854 855 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014 856 857 #define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018 858 859 #define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000 860 #define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001 861 862 #define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004 863 864 #define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008 865 866 #define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c 867 868 #define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010 869 #define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002 870 871 #define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014 872 873 #define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018 874 875 #define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c 876 877 #define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020 878 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001 879 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002 880 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004 881 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008 882 883 #define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024 884 885 #define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028 886 887 #define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c 888 889 #define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030 890 891 #define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034 892 893 #define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038 894 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f 895 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0 896 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val) 897 { 898 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK; 899 } 900 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040 901 902 #define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c 903 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f 904 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0 905 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val) 906 { 907 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; 908 } 909 #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040 910 #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6 911 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val) 912 { 913 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK; 914 } 915 916 #define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040 917 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff 918 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0 919 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val) 920 { 921 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK; 922 } 923 924 #define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044 925 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff 926 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0 927 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val) 928 { 929 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK; 930 } 931 932 #define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048 933 934 #define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c 935 936 #define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050 937 938 #define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054 939 940 #define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058 941 942 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c 943 944 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060 945 946 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064 947 948 #define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068 949 #define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001 950 951 #define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c 952 953 #define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070 954 955 #define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074 956 957 #define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078 958 959 #define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c 960 961 #define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080 962 963 #define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084 964 965 #define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088 966 967 #define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c 968 969 #define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090 970 971 #define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094 972 973 #define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098 974 975 #define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c 976 977 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0 978 979 #define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4 980 981 #define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8 982 983 #define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac 984 985 #define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0 986 987 #define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4 988 989 #define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8 990 991 #define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc 992 993 #define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0 994 #define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001 995 996 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4 997 998 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8 999 1000 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc 1001 1002 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0 1003 1004 #define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4 1005 1006 static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } 1007 1008 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } 1009 1010 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } 1011 1012 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } 1013 1014 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } 1015 1016 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } 1017 1018 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } 1019 1020 static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } 1021 1022 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } 1023 1024 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } 1025 1026 #define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100 1027 1028 #define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104 1029 1030 #define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108 1031 1032 #define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c 1033 1034 #define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110 1035 1036 #define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114 1037 1038 #define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118 1039 1040 #define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c 1041 1042 #define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120 1043 1044 #define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140 1045 #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff 1046 #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 1047 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) 1048 { 1049 return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; 1050 } 1051 1052 #define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144 1053 #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff 1054 #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 1055 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) 1056 { 1057 return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; 1058 } 1059 1060 #define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148 1061 #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff 1062 #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 1063 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) 1064 { 1065 return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; 1066 } 1067 1068 #define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c 1069 #define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001 1070 1071 #define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150 1072 #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff 1073 #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 1074 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) 1075 { 1076 return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; 1077 } 1078 1079 #define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154 1080 #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff 1081 #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 1082 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) 1083 { 1084 return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; 1085 } 1086 1087 #define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158 1088 #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff 1089 #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 1090 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) 1091 { 1092 return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; 1093 } 1094 1095 #define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c 1096 #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff 1097 #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 1098 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) 1099 { 1100 return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; 1101 } 1102 1103 #define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160 1104 #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff 1105 #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 1106 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) 1107 { 1108 return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; 1109 } 1110 1111 #define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164 1112 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 1113 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 1114 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) 1115 { 1116 return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK; 1117 } 1118 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 1119 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 1120 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) 1121 { 1122 return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; 1123 } 1124 1125 #define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168 1126 #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 1127 #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 1128 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) 1129 { 1130 return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK; 1131 } 1132 1133 #define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c 1134 #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff 1135 #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 1136 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) 1137 { 1138 return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; 1139 } 1140 1141 #define REG_DSI_20nm_PHY_CTRL_0 0x00000170 1142 1143 #define REG_DSI_20nm_PHY_CTRL_1 0x00000174 1144 1145 #define REG_DSI_20nm_PHY_CTRL_2 0x00000178 1146 1147 #define REG_DSI_20nm_PHY_CTRL_3 0x0000017c 1148 1149 #define REG_DSI_20nm_PHY_CTRL_4 0x00000180 1150 1151 #define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184 1152 1153 #define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188 1154 1155 #define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4 1156 1157 #define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8 1158 1159 #define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc 1160 1161 #define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0 1162 1163 #define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4 1164 1165 #define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8 1166 1167 #define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4 1168 #define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001 1169 1170 #define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc 1171 1172 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000 1173 1174 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004 1175 1176 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008 1177 1178 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c 1179 1180 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010 1181 1182 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014 1183 1184 #define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018 1185 1186 1187 #endif /* DSI_XML */ 1188