1 #ifndef DSI_XML 2 #define DSI_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 13 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) 14 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) 15 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) 16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) 17 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) 18 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) 19 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) 20 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) 21 - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14) 22 23 Copyright (C) 2013-2015 by the following authors: 24 - Rob Clark <robdclark@gmail.com> (robclark) 25 26 Permission is hereby granted, free of charge, to any person obtaining 27 a copy of this software and associated documentation files (the 28 "Software"), to deal in the Software without restriction, including 29 without limitation the rights to use, copy, modify, merge, publish, 30 distribute, sublicense, and/or sell copies of the Software, and to 31 permit persons to whom the Software is furnished to do so, subject to 32 the following conditions: 33 34 The above copyright notice and this permission notice (including the 35 next paragraph) shall be included in all copies or substantial 36 portions of the Software. 37 38 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 40 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 41 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 42 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 43 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 44 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 45 */ 46 47 48 enum dsi_traffic_mode { 49 NON_BURST_SYNCH_PULSE = 0, 50 NON_BURST_SYNCH_EVENT = 1, 51 BURST_MODE = 2, 52 }; 53 54 enum dsi_vid_dst_format { 55 VID_DST_FORMAT_RGB565 = 0, 56 VID_DST_FORMAT_RGB666 = 1, 57 VID_DST_FORMAT_RGB666_LOOSE = 2, 58 VID_DST_FORMAT_RGB888 = 3, 59 }; 60 61 enum dsi_rgb_swap { 62 SWAP_RGB = 0, 63 SWAP_RBG = 1, 64 SWAP_BGR = 2, 65 SWAP_BRG = 3, 66 SWAP_GRB = 4, 67 SWAP_GBR = 5, 68 }; 69 70 enum dsi_cmd_trigger { 71 TRIGGER_NONE = 0, 72 TRIGGER_SEOF = 1, 73 TRIGGER_TE = 2, 74 TRIGGER_SW = 4, 75 TRIGGER_SW_SEOF = 5, 76 TRIGGER_SW_TE = 6, 77 }; 78 79 enum dsi_cmd_dst_format { 80 CMD_DST_FORMAT_RGB111 = 0, 81 CMD_DST_FORMAT_RGB332 = 3, 82 CMD_DST_FORMAT_RGB444 = 4, 83 CMD_DST_FORMAT_RGB565 = 6, 84 CMD_DST_FORMAT_RGB666 = 7, 85 CMD_DST_FORMAT_RGB888 = 8, 86 }; 87 88 enum dsi_lane_swap { 89 LANE_SWAP_0123 = 0, 90 LANE_SWAP_3012 = 1, 91 LANE_SWAP_2301 = 2, 92 LANE_SWAP_1230 = 3, 93 LANE_SWAP_0321 = 4, 94 LANE_SWAP_1032 = 5, 95 LANE_SWAP_2103 = 6, 96 LANE_SWAP_3210 = 7, 97 }; 98 99 #define DSI_IRQ_CMD_DMA_DONE 0x00000001 100 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002 101 #define DSI_IRQ_CMD_MDP_DONE 0x00000100 102 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200 103 #define DSI_IRQ_VIDEO_DONE 0x00010000 104 #define DSI_IRQ_MASK_VIDEO_DONE 0x00020000 105 #define DSI_IRQ_BTA_DONE 0x00100000 106 #define DSI_IRQ_MASK_BTA_DONE 0x00200000 107 #define DSI_IRQ_ERROR 0x01000000 108 #define DSI_IRQ_MASK_ERROR 0x02000000 109 #define REG_DSI_6G_HW_VERSION 0x00000000 110 #define DSI_6G_HW_VERSION_MAJOR__MASK 0xf0000000 111 #define DSI_6G_HW_VERSION_MAJOR__SHIFT 28 112 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) 113 { 114 return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK; 115 } 116 #define DSI_6G_HW_VERSION_MINOR__MASK 0x0fff0000 117 #define DSI_6G_HW_VERSION_MINOR__SHIFT 16 118 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) 119 { 120 return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK; 121 } 122 #define DSI_6G_HW_VERSION_STEP__MASK 0x0000ffff 123 #define DSI_6G_HW_VERSION_STEP__SHIFT 0 124 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) 125 { 126 return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK; 127 } 128 129 #define REG_DSI_CTRL 0x00000000 130 #define DSI_CTRL_ENABLE 0x00000001 131 #define DSI_CTRL_VID_MODE_EN 0x00000002 132 #define DSI_CTRL_CMD_MODE_EN 0x00000004 133 #define DSI_CTRL_LANE0 0x00000010 134 #define DSI_CTRL_LANE1 0x00000020 135 #define DSI_CTRL_LANE2 0x00000040 136 #define DSI_CTRL_LANE3 0x00000080 137 #define DSI_CTRL_CLK_EN 0x00000100 138 #define DSI_CTRL_ECC_CHECK 0x00100000 139 #define DSI_CTRL_CRC_CHECK 0x01000000 140 141 #define REG_DSI_STATUS0 0x00000004 142 #define DSI_STATUS0_CMD_MODE_ENGINE_BUSY 0x00000001 143 #define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002 144 #define DSI_STATUS0_CMD_MODE_MDP_BUSY 0x00000004 145 #define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008 146 #define DSI_STATUS0_DSI_BUSY 0x00000010 147 #define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000 148 149 #define REG_DSI_FIFO_STATUS 0x00000008 150 #define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080 151 152 #define REG_DSI_VID_CFG0 0x0000000c 153 #define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003 154 #define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0 155 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) 156 { 157 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK; 158 } 159 #define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030 160 #define DSI_VID_CFG0_DST_FORMAT__SHIFT 4 161 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) 162 { 163 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; 164 } 165 #define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300 166 #define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT 8 167 static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) 168 { 169 return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK; 170 } 171 #define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000 172 #define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000 173 #define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000 174 #define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000 175 #define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000 176 #define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000 177 178 #define REG_DSI_VID_CFG1 0x0000001c 179 #define DSI_VID_CFG1_R_SEL 0x00000001 180 #define DSI_VID_CFG1_G_SEL 0x00000010 181 #define DSI_VID_CFG1_B_SEL 0x00000100 182 #define DSI_VID_CFG1_RGB_SWAP__MASK 0x00007000 183 #define DSI_VID_CFG1_RGB_SWAP__SHIFT 12 184 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) 185 { 186 return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK; 187 } 188 189 #define REG_DSI_ACTIVE_H 0x00000020 190 #define DSI_ACTIVE_H_START__MASK 0x00000fff 191 #define DSI_ACTIVE_H_START__SHIFT 0 192 static inline uint32_t DSI_ACTIVE_H_START(uint32_t val) 193 { 194 return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK; 195 } 196 #define DSI_ACTIVE_H_END__MASK 0x0fff0000 197 #define DSI_ACTIVE_H_END__SHIFT 16 198 static inline uint32_t DSI_ACTIVE_H_END(uint32_t val) 199 { 200 return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK; 201 } 202 203 #define REG_DSI_ACTIVE_V 0x00000024 204 #define DSI_ACTIVE_V_START__MASK 0x00000fff 205 #define DSI_ACTIVE_V_START__SHIFT 0 206 static inline uint32_t DSI_ACTIVE_V_START(uint32_t val) 207 { 208 return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK; 209 } 210 #define DSI_ACTIVE_V_END__MASK 0x0fff0000 211 #define DSI_ACTIVE_V_END__SHIFT 16 212 static inline uint32_t DSI_ACTIVE_V_END(uint32_t val) 213 { 214 return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK; 215 } 216 217 #define REG_DSI_TOTAL 0x00000028 218 #define DSI_TOTAL_H_TOTAL__MASK 0x00000fff 219 #define DSI_TOTAL_H_TOTAL__SHIFT 0 220 static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val) 221 { 222 return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK; 223 } 224 #define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000 225 #define DSI_TOTAL_V_TOTAL__SHIFT 16 226 static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val) 227 { 228 return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK; 229 } 230 231 #define REG_DSI_ACTIVE_HSYNC 0x0000002c 232 #define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff 233 #define DSI_ACTIVE_HSYNC_START__SHIFT 0 234 static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val) 235 { 236 return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK; 237 } 238 #define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000 239 #define DSI_ACTIVE_HSYNC_END__SHIFT 16 240 static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val) 241 { 242 return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK; 243 } 244 245 #define REG_DSI_ACTIVE_VSYNC_HPOS 0x00000030 246 #define DSI_ACTIVE_VSYNC_HPOS_START__MASK 0x00000fff 247 #define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT 0 248 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val) 249 { 250 return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK; 251 } 252 #define DSI_ACTIVE_VSYNC_HPOS_END__MASK 0x0fff0000 253 #define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT 16 254 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val) 255 { 256 return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK; 257 } 258 259 #define REG_DSI_ACTIVE_VSYNC_VPOS 0x00000034 260 #define DSI_ACTIVE_VSYNC_VPOS_START__MASK 0x00000fff 261 #define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT 0 262 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val) 263 { 264 return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK; 265 } 266 #define DSI_ACTIVE_VSYNC_VPOS_END__MASK 0x0fff0000 267 #define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT 16 268 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val) 269 { 270 return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK; 271 } 272 273 #define REG_DSI_CMD_DMA_CTRL 0x00000038 274 #define DSI_CMD_DMA_CTRL_BROADCAST_EN 0x80000000 275 #define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000 276 #define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000 277 278 #define REG_DSI_CMD_CFG0 0x0000003c 279 #define DSI_CMD_CFG0_DST_FORMAT__MASK 0x0000000f 280 #define DSI_CMD_CFG0_DST_FORMAT__SHIFT 0 281 static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val) 282 { 283 return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK; 284 } 285 #define DSI_CMD_CFG0_R_SEL 0x00000010 286 #define DSI_CMD_CFG0_G_SEL 0x00000100 287 #define DSI_CMD_CFG0_B_SEL 0x00001000 288 #define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK 0x00f00000 289 #define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT 20 290 static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val) 291 { 292 return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK; 293 } 294 #define DSI_CMD_CFG0_RGB_SWAP__MASK 0x00070000 295 #define DSI_CMD_CFG0_RGB_SWAP__SHIFT 16 296 static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val) 297 { 298 return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK; 299 } 300 301 #define REG_DSI_CMD_CFG1 0x00000040 302 #define DSI_CMD_CFG1_WR_MEM_START__MASK 0x000000ff 303 #define DSI_CMD_CFG1_WR_MEM_START__SHIFT 0 304 static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val) 305 { 306 return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK; 307 } 308 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK 0x0000ff00 309 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT 8 310 static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val) 311 { 312 return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK; 313 } 314 #define DSI_CMD_CFG1_INSERT_DCS_COMMAND 0x00010000 315 316 #define REG_DSI_DMA_BASE 0x00000044 317 318 #define REG_DSI_DMA_LEN 0x00000048 319 320 #define REG_DSI_CMD_MDP_STREAM_CTRL 0x00000054 321 #define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK 0x0000003f 322 #define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT 0 323 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val) 324 { 325 return ((val) << DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK; 326 } 327 #define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 328 #define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT 8 329 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val) 330 { 331 return ((val) << DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK; 332 } 333 #define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK 0xffff0000 334 #define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT 16 335 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val) 336 { 337 return ((val) << DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK; 338 } 339 340 #define REG_DSI_CMD_MDP_STREAM_TOTAL 0x00000058 341 #define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK 0x00000fff 342 #define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT 0 343 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val) 344 { 345 return ((val) << DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK; 346 } 347 #define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK 0x0fff0000 348 #define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT 16 349 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val) 350 { 351 return ((val) << DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK; 352 } 353 354 #define REG_DSI_ACK_ERR_STATUS 0x00000064 355 356 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } 357 358 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } 359 360 #define REG_DSI_TRIG_CTRL 0x00000080 361 #define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x00000007 362 #define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0 363 static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val) 364 { 365 return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK; 366 } 367 #define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x00000070 368 #define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT 4 369 static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val) 370 { 371 return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK; 372 } 373 #define DSI_TRIG_CTRL_STREAM__MASK 0x00000300 374 #define DSI_TRIG_CTRL_STREAM__SHIFT 8 375 static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val) 376 { 377 return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK; 378 } 379 #define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME 0x00001000 380 #define DSI_TRIG_CTRL_TE 0x80000000 381 382 #define REG_DSI_TRIG_DMA 0x0000008c 383 384 #define REG_DSI_DLN0_PHY_ERR 0x000000b0 385 #define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC 0x00000001 386 #define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC 0x00000010 387 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL 0x00000100 388 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000 389 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000 390 391 #define REG_DSI_TIMEOUT_STATUS 0x000000bc 392 393 #define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0 394 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f 395 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0 396 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val) 397 { 398 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK; 399 } 400 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00 401 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT 8 402 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) 403 { 404 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK; 405 } 406 407 #define REG_DSI_EOT_PACKET_CTRL 0x000000c8 408 #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001 409 #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010 410 411 #define REG_DSI_LANE_CTRL 0x000000a8 412 #define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000 413 414 #define REG_DSI_LANE_SWAP_CTRL 0x000000ac 415 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007 416 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0 417 static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val) 418 { 419 return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK; 420 } 421 422 #define REG_DSI_ERR_INT_MASK0 0x00000108 423 424 #define REG_DSI_INTR_CTRL 0x0000010c 425 426 #define REG_DSI_RESET 0x00000114 427 428 #define REG_DSI_CLK_CTRL 0x00000118 429 #define DSI_CLK_CTRL_AHBS_HCLK_ON 0x00000001 430 #define DSI_CLK_CTRL_AHBM_SCLK_ON 0x00000002 431 #define DSI_CLK_CTRL_PCLK_ON 0x00000004 432 #define DSI_CLK_CTRL_DSICLK_ON 0x00000008 433 #define DSI_CLK_CTRL_BYTECLK_ON 0x00000010 434 #define DSI_CLK_CTRL_ESCCLK_ON 0x00000020 435 #define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200 436 437 #define REG_DSI_CLK_STATUS 0x0000011c 438 #define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000 439 440 #define REG_DSI_PHY_RESET 0x00000128 441 #define DSI_PHY_RESET_RESET 0x00000001 442 443 #define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c 444 #define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001 445 446 #define REG_DSI_RDBK_DATA_CTRL 0x000001d0 447 #define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000 448 #define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16 449 static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val) 450 { 451 return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK; 452 } 453 #define DSI_RDBK_DATA_CTRL_CLR 0x00000001 454 455 #define REG_DSI_VERSION 0x000001f0 456 #define DSI_VERSION_MAJOR__MASK 0xff000000 457 #define DSI_VERSION_MAJOR__SHIFT 24 458 static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) 459 { 460 return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK; 461 } 462 463 #define REG_DSI_PHY_PLL_CTRL_0 0x00000200 464 #define DSI_PHY_PLL_CTRL_0_ENABLE 0x00000001 465 466 #define REG_DSI_PHY_PLL_CTRL_1 0x00000204 467 468 #define REG_DSI_PHY_PLL_CTRL_2 0x00000208 469 470 #define REG_DSI_PHY_PLL_CTRL_3 0x0000020c 471 472 #define REG_DSI_PHY_PLL_CTRL_4 0x00000210 473 474 #define REG_DSI_PHY_PLL_CTRL_5 0x00000214 475 476 #define REG_DSI_PHY_PLL_CTRL_6 0x00000218 477 478 #define REG_DSI_PHY_PLL_CTRL_7 0x0000021c 479 480 #define REG_DSI_PHY_PLL_CTRL_8 0x00000220 481 482 #define REG_DSI_PHY_PLL_CTRL_9 0x00000224 483 484 #define REG_DSI_PHY_PLL_CTRL_10 0x00000228 485 486 #define REG_DSI_PHY_PLL_CTRL_11 0x0000022c 487 488 #define REG_DSI_PHY_PLL_CTRL_12 0x00000230 489 490 #define REG_DSI_PHY_PLL_CTRL_13 0x00000234 491 492 #define REG_DSI_PHY_PLL_CTRL_14 0x00000238 493 494 #define REG_DSI_PHY_PLL_CTRL_15 0x0000023c 495 496 #define REG_DSI_PHY_PLL_CTRL_16 0x00000240 497 498 #define REG_DSI_PHY_PLL_CTRL_17 0x00000244 499 500 #define REG_DSI_PHY_PLL_CTRL_18 0x00000248 501 502 #define REG_DSI_PHY_PLL_CTRL_19 0x0000024c 503 504 #define REG_DSI_PHY_PLL_CTRL_20 0x00000250 505 506 #define REG_DSI_PHY_PLL_STATUS 0x00000280 507 #define DSI_PHY_PLL_STATUS_PLL_BUSY 0x00000001 508 509 #define REG_DSI_8x60_PHY_TPA_CTRL_1 0x00000258 510 511 #define REG_DSI_8x60_PHY_TPA_CTRL_2 0x0000025c 512 513 #define REG_DSI_8x60_PHY_TIMING_CTRL_0 0x00000260 514 515 #define REG_DSI_8x60_PHY_TIMING_CTRL_1 0x00000264 516 517 #define REG_DSI_8x60_PHY_TIMING_CTRL_2 0x00000268 518 519 #define REG_DSI_8x60_PHY_TIMING_CTRL_3 0x0000026c 520 521 #define REG_DSI_8x60_PHY_TIMING_CTRL_4 0x00000270 522 523 #define REG_DSI_8x60_PHY_TIMING_CTRL_5 0x00000274 524 525 #define REG_DSI_8x60_PHY_TIMING_CTRL_6 0x00000278 526 527 #define REG_DSI_8x60_PHY_TIMING_CTRL_7 0x0000027c 528 529 #define REG_DSI_8x60_PHY_TIMING_CTRL_8 0x00000280 530 531 #define REG_DSI_8x60_PHY_TIMING_CTRL_9 0x00000284 532 533 #define REG_DSI_8x60_PHY_TIMING_CTRL_10 0x00000288 534 535 #define REG_DSI_8x60_PHY_TIMING_CTRL_11 0x0000028c 536 537 #define REG_DSI_8x60_PHY_CTRL_0 0x00000290 538 539 #define REG_DSI_8x60_PHY_CTRL_1 0x00000294 540 541 #define REG_DSI_8x60_PHY_CTRL_2 0x00000298 542 543 #define REG_DSI_8x60_PHY_CTRL_3 0x0000029c 544 545 #define REG_DSI_8x60_PHY_STRENGTH_0 0x000002a0 546 547 #define REG_DSI_8x60_PHY_STRENGTH_1 0x000002a4 548 549 #define REG_DSI_8x60_PHY_STRENGTH_2 0x000002a8 550 551 #define REG_DSI_8x60_PHY_STRENGTH_3 0x000002ac 552 553 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_0 0x000002cc 554 555 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_1 0x000002d0 556 557 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_2 0x000002d4 558 559 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_3 0x000002d8 560 561 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_4 0x000002dc 562 563 #define REG_DSI_8x60_PHY_CAL_HW_TRIGGER 0x000000f0 564 565 #define REG_DSI_8x60_PHY_CAL_CTRL 0x000000f4 566 567 #define REG_DSI_8x60_PHY_CAL_STATUS 0x000000fc 568 #define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY 0x10000000 569 570 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } 571 572 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } 573 574 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } 575 576 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } 577 578 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; } 579 580 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; } 581 582 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; } 583 584 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100 585 586 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104 587 588 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108 589 590 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c 591 592 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114 593 594 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118 595 596 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140 597 #define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff 598 #define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 599 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) 600 { 601 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; 602 } 603 604 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144 605 #define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff 606 #define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 607 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) 608 { 609 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; 610 } 611 612 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148 613 #define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff 614 #define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 615 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) 616 { 617 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; 618 } 619 620 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c 621 622 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150 623 #define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff 624 #define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 625 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) 626 { 627 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK; 628 } 629 630 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154 631 #define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff 632 #define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 633 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) 634 { 635 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK; 636 } 637 638 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158 639 #define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff 640 #define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 641 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) 642 { 643 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; 644 } 645 646 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c 647 #define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff 648 #define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 649 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) 650 { 651 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; 652 } 653 654 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160 655 #define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff 656 #define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 657 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) 658 { 659 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK; 660 } 661 662 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164 663 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 664 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 665 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) 666 { 667 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK; 668 } 669 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 670 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 671 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) 672 { 673 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK; 674 } 675 676 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168 677 #define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 678 #define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 679 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) 680 { 681 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK; 682 } 683 684 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c 685 #define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff 686 #define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 687 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) 688 { 689 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; 690 } 691 692 #define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170 693 694 #define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174 695 696 #define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178 697 698 #define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c 699 700 #define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180 701 702 #define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184 703 704 #define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188 705 706 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c 707 708 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190 709 710 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194 711 712 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198 713 714 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c 715 716 #define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0 717 718 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000 719 720 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004 721 722 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008 723 724 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c 725 726 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010 727 728 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014 729 730 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018 731 732 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028 733 734 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c 735 736 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030 737 738 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034 739 740 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038 741 742 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c 743 744 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040 745 746 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044 747 748 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048 749 750 #define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050 751 #define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010 752 753 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000 754 #define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001 755 756 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004 757 758 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008 759 760 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c 761 762 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010 763 764 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014 765 766 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018 767 768 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c 769 770 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020 771 772 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024 773 774 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028 775 776 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c 777 778 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030 779 780 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034 781 782 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038 783 784 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c 785 786 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040 787 788 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044 789 790 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048 791 792 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c 793 794 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050 795 796 #define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080 797 #define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001 798 799 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } 800 801 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } 802 803 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } 804 805 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } 806 807 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } 808 809 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } 810 811 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } 812 813 static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } 814 815 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } 816 817 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } 818 819 #define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100 820 821 #define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104 822 823 #define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108 824 825 #define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c 826 827 #define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110 828 829 #define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114 830 831 #define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118 832 833 #define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c 834 835 #define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120 836 837 #define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140 838 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff 839 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 840 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) 841 { 842 return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; 843 } 844 845 #define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144 846 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff 847 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 848 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) 849 { 850 return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; 851 } 852 853 #define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148 854 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff 855 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 856 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) 857 { 858 return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; 859 } 860 861 #define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c 862 #define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001 863 864 #define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150 865 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff 866 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 867 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) 868 { 869 return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; 870 } 871 872 #define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154 873 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff 874 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 875 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) 876 { 877 return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; 878 } 879 880 #define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158 881 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff 882 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 883 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) 884 { 885 return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; 886 } 887 888 #define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c 889 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff 890 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 891 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) 892 { 893 return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; 894 } 895 896 #define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160 897 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff 898 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 899 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) 900 { 901 return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; 902 } 903 904 #define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164 905 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 906 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 907 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) 908 { 909 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK; 910 } 911 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 912 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 913 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) 914 { 915 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; 916 } 917 918 #define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168 919 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 920 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 921 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) 922 { 923 return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK; 924 } 925 926 #define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c 927 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff 928 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 929 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) 930 { 931 return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; 932 } 933 934 #define REG_DSI_28nm_PHY_CTRL_0 0x00000170 935 936 #define REG_DSI_28nm_PHY_CTRL_1 0x00000174 937 938 #define REG_DSI_28nm_PHY_CTRL_2 0x00000178 939 940 #define REG_DSI_28nm_PHY_CTRL_3 0x0000017c 941 942 #define REG_DSI_28nm_PHY_CTRL_4 0x00000180 943 944 #define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184 945 946 #define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188 947 948 #define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4 949 950 #define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8 951 952 #define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc 953 954 #define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0 955 956 #define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4 957 958 #define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8 959 960 #define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4 961 #define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001 962 963 #define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc 964 965 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000 966 967 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004 968 969 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008 970 971 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c 972 973 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010 974 975 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014 976 977 #define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018 978 979 #define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000 980 #define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001 981 982 #define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004 983 984 #define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008 985 986 #define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c 987 988 #define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010 989 #define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002 990 991 #define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014 992 993 #define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018 994 995 #define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c 996 997 #define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020 998 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001 999 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002 1000 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004 1001 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008 1002 1003 #define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024 1004 1005 #define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028 1006 1007 #define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c 1008 1009 #define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030 1010 1011 #define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034 1012 1013 #define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038 1014 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f 1015 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0 1016 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val) 1017 { 1018 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK; 1019 } 1020 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040 1021 1022 #define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c 1023 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f 1024 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0 1025 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val) 1026 { 1027 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; 1028 } 1029 #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040 1030 #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6 1031 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val) 1032 { 1033 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK; 1034 } 1035 1036 #define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040 1037 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff 1038 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0 1039 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val) 1040 { 1041 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK; 1042 } 1043 1044 #define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044 1045 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff 1046 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0 1047 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val) 1048 { 1049 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK; 1050 } 1051 1052 #define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048 1053 1054 #define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c 1055 1056 #define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050 1057 1058 #define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054 1059 1060 #define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058 1061 1062 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c 1063 1064 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060 1065 1066 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064 1067 1068 #define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068 1069 #define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001 1070 1071 #define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c 1072 1073 #define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070 1074 1075 #define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074 1076 1077 #define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078 1078 1079 #define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c 1080 1081 #define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080 1082 1083 #define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084 1084 1085 #define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088 1086 1087 #define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c 1088 1089 #define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090 1090 1091 #define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094 1092 1093 #define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098 1094 1095 #define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c 1096 1097 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0 1098 1099 #define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4 1100 1101 #define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8 1102 1103 #define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac 1104 1105 #define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0 1106 1107 #define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4 1108 1109 #define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8 1110 1111 #define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc 1112 1113 #define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0 1114 #define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001 1115 1116 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4 1117 1118 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8 1119 1120 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc 1121 1122 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0 1123 1124 #define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4 1125 1126 static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } 1127 1128 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } 1129 1130 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } 1131 1132 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } 1133 1134 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } 1135 1136 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } 1137 1138 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } 1139 1140 static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } 1141 1142 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } 1143 1144 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } 1145 1146 #define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100 1147 1148 #define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104 1149 1150 #define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108 1151 1152 #define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c 1153 1154 #define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110 1155 1156 #define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114 1157 1158 #define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118 1159 1160 #define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c 1161 1162 #define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120 1163 1164 #define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140 1165 #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff 1166 #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 1167 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) 1168 { 1169 return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; 1170 } 1171 1172 #define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144 1173 #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff 1174 #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 1175 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) 1176 { 1177 return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; 1178 } 1179 1180 #define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148 1181 #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff 1182 #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 1183 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) 1184 { 1185 return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; 1186 } 1187 1188 #define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c 1189 #define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001 1190 1191 #define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150 1192 #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff 1193 #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 1194 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) 1195 { 1196 return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; 1197 } 1198 1199 #define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154 1200 #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff 1201 #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 1202 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) 1203 { 1204 return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; 1205 } 1206 1207 #define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158 1208 #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff 1209 #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 1210 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) 1211 { 1212 return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; 1213 } 1214 1215 #define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c 1216 #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff 1217 #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 1218 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) 1219 { 1220 return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; 1221 } 1222 1223 #define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160 1224 #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff 1225 #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 1226 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) 1227 { 1228 return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; 1229 } 1230 1231 #define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164 1232 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 1233 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 1234 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) 1235 { 1236 return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK; 1237 } 1238 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 1239 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 1240 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) 1241 { 1242 return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; 1243 } 1244 1245 #define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168 1246 #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 1247 #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 1248 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) 1249 { 1250 return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK; 1251 } 1252 1253 #define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c 1254 #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff 1255 #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 1256 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) 1257 { 1258 return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; 1259 } 1260 1261 #define REG_DSI_20nm_PHY_CTRL_0 0x00000170 1262 1263 #define REG_DSI_20nm_PHY_CTRL_1 0x00000174 1264 1265 #define REG_DSI_20nm_PHY_CTRL_2 0x00000178 1266 1267 #define REG_DSI_20nm_PHY_CTRL_3 0x0000017c 1268 1269 #define REG_DSI_20nm_PHY_CTRL_4 0x00000180 1270 1271 #define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184 1272 1273 #define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188 1274 1275 #define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4 1276 1277 #define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8 1278 1279 #define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc 1280 1281 #define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0 1282 1283 #define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4 1284 1285 #define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8 1286 1287 #define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4 1288 #define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001 1289 1290 #define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc 1291 1292 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000 1293 1294 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004 1295 1296 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008 1297 1298 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c 1299 1300 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010 1301 1302 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014 1303 1304 #define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018 1305 1306 1307 #endif /* DSI_XML */ 1308