1 #ifndef DSI_XML 2 #define DSI_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) 12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) 13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) 14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) 15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) 16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) 17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) 18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) 19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) 20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) 21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) 22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) 23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) 24 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) 25 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) 26 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) 27 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) 28 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) 29 - /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) 30 31 Copyright (C) 2013-2021 by the following authors: 32 - Rob Clark <robdclark@gmail.com> (robclark) 33 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 34 35 Permission is hereby granted, free of charge, to any person obtaining 36 a copy of this software and associated documentation files (the 37 "Software"), to deal in the Software without restriction, including 38 without limitation the rights to use, copy, modify, merge, publish, 39 distribute, sublicense, and/or sell copies of the Software, and to 40 permit persons to whom the Software is furnished to do so, subject to 41 the following conditions: 42 43 The above copyright notice and this permission notice (including the 44 next paragraph) shall be included in all copies or substantial 45 portions of the Software. 46 47 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 48 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 49 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 50 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 51 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 52 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 53 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 54 */ 55 56 57 enum dsi_traffic_mode { 58 NON_BURST_SYNCH_PULSE = 0, 59 NON_BURST_SYNCH_EVENT = 1, 60 BURST_MODE = 2, 61 }; 62 63 enum dsi_vid_dst_format { 64 VID_DST_FORMAT_RGB565 = 0, 65 VID_DST_FORMAT_RGB666 = 1, 66 VID_DST_FORMAT_RGB666_LOOSE = 2, 67 VID_DST_FORMAT_RGB888 = 3, 68 }; 69 70 enum dsi_rgb_swap { 71 SWAP_RGB = 0, 72 SWAP_RBG = 1, 73 SWAP_BGR = 2, 74 SWAP_BRG = 3, 75 SWAP_GRB = 4, 76 SWAP_GBR = 5, 77 }; 78 79 enum dsi_cmd_trigger { 80 TRIGGER_NONE = 0, 81 TRIGGER_SEOF = 1, 82 TRIGGER_TE = 2, 83 TRIGGER_SW = 4, 84 TRIGGER_SW_SEOF = 5, 85 TRIGGER_SW_TE = 6, 86 }; 87 88 enum dsi_cmd_dst_format { 89 CMD_DST_FORMAT_RGB111 = 0, 90 CMD_DST_FORMAT_RGB332 = 3, 91 CMD_DST_FORMAT_RGB444 = 4, 92 CMD_DST_FORMAT_RGB565 = 6, 93 CMD_DST_FORMAT_RGB666 = 7, 94 CMD_DST_FORMAT_RGB888 = 8, 95 }; 96 97 enum dsi_lane_swap { 98 LANE_SWAP_0123 = 0, 99 LANE_SWAP_3012 = 1, 100 LANE_SWAP_2301 = 2, 101 LANE_SWAP_1230 = 3, 102 LANE_SWAP_0321 = 4, 103 LANE_SWAP_1032 = 5, 104 LANE_SWAP_2103 = 6, 105 LANE_SWAP_3210 = 7, 106 }; 107 108 #define DSI_IRQ_CMD_DMA_DONE 0x00000001 109 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002 110 #define DSI_IRQ_CMD_MDP_DONE 0x00000100 111 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200 112 #define DSI_IRQ_VIDEO_DONE 0x00010000 113 #define DSI_IRQ_MASK_VIDEO_DONE 0x00020000 114 #define DSI_IRQ_BTA_DONE 0x00100000 115 #define DSI_IRQ_MASK_BTA_DONE 0x00200000 116 #define DSI_IRQ_ERROR 0x01000000 117 #define DSI_IRQ_MASK_ERROR 0x02000000 118 #define REG_DSI_6G_HW_VERSION 0x00000000 119 #define DSI_6G_HW_VERSION_MAJOR__MASK 0xf0000000 120 #define DSI_6G_HW_VERSION_MAJOR__SHIFT 28 121 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) 122 { 123 return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK; 124 } 125 #define DSI_6G_HW_VERSION_MINOR__MASK 0x0fff0000 126 #define DSI_6G_HW_VERSION_MINOR__SHIFT 16 127 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) 128 { 129 return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK; 130 } 131 #define DSI_6G_HW_VERSION_STEP__MASK 0x0000ffff 132 #define DSI_6G_HW_VERSION_STEP__SHIFT 0 133 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) 134 { 135 return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK; 136 } 137 138 #define REG_DSI_CTRL 0x00000000 139 #define DSI_CTRL_ENABLE 0x00000001 140 #define DSI_CTRL_VID_MODE_EN 0x00000002 141 #define DSI_CTRL_CMD_MODE_EN 0x00000004 142 #define DSI_CTRL_LANE0 0x00000010 143 #define DSI_CTRL_LANE1 0x00000020 144 #define DSI_CTRL_LANE2 0x00000040 145 #define DSI_CTRL_LANE3 0x00000080 146 #define DSI_CTRL_CLK_EN 0x00000100 147 #define DSI_CTRL_ECC_CHECK 0x00100000 148 #define DSI_CTRL_CRC_CHECK 0x01000000 149 150 #define REG_DSI_STATUS0 0x00000004 151 #define DSI_STATUS0_CMD_MODE_ENGINE_BUSY 0x00000001 152 #define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002 153 #define DSI_STATUS0_CMD_MODE_MDP_BUSY 0x00000004 154 #define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008 155 #define DSI_STATUS0_DSI_BUSY 0x00000010 156 #define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000 157 158 #define REG_DSI_FIFO_STATUS 0x00000008 159 #define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_OVERFLOW 0x00000001 160 #define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_UNDERFLOW 0x00000008 161 #define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080 162 #define DSI_FIFO_STATUS_CMD_DMA_FIFO_RD_WATERMARK_REACH 0x00000100 163 #define DSI_FIFO_STATUS_CMD_DMA_FIFO_WR_WATERMARK_REACH 0x00000200 164 #define DSI_FIFO_STATUS_CMD_DMA_FIFO_UNDERFLOW 0x00000400 165 #define DSI_FIFO_STATUS_DLN0_LP_FIFO_EMPTY 0x00001000 166 #define DSI_FIFO_STATUS_DLN0_LP_FIFO_FULL 0x00002000 167 #define DSI_FIFO_STATUS_DLN0_LP_FIFO_OVERFLOW 0x00004000 168 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_EMPTY 0x00010000 169 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_FULL 0x00020000 170 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_OVERFLOW 0x00040000 171 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_UNDERFLOW 0x00080000 172 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_EMPTY 0x00100000 173 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_FULL 0x00200000 174 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_OVERFLOW 0x00400000 175 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_UNDERFLOW 0x00800000 176 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_EMPTY 0x01000000 177 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_FULL 0x02000000 178 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_OVERFLOW 0x04000000 179 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_UNDERFLOW 0x08000000 180 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_EMPTY 0x10000000 181 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_FULL 0x20000000 182 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_OVERFLOW 0x40000000 183 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_UNDERFLOW 0x80000000 184 185 #define REG_DSI_VID_CFG0 0x0000000c 186 #define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003 187 #define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0 188 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) 189 { 190 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK; 191 } 192 #define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030 193 #define DSI_VID_CFG0_DST_FORMAT__SHIFT 4 194 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) 195 { 196 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; 197 } 198 #define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300 199 #define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT 8 200 static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) 201 { 202 return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK; 203 } 204 #define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000 205 #define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000 206 #define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000 207 #define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000 208 #define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000 209 #define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000 210 211 #define REG_DSI_VID_CFG1 0x0000001c 212 #define DSI_VID_CFG1_R_SEL 0x00000001 213 #define DSI_VID_CFG1_G_SEL 0x00000010 214 #define DSI_VID_CFG1_B_SEL 0x00000100 215 #define DSI_VID_CFG1_RGB_SWAP__MASK 0x00007000 216 #define DSI_VID_CFG1_RGB_SWAP__SHIFT 12 217 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) 218 { 219 return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK; 220 } 221 222 #define REG_DSI_ACTIVE_H 0x00000020 223 #define DSI_ACTIVE_H_START__MASK 0x00000fff 224 #define DSI_ACTIVE_H_START__SHIFT 0 225 static inline uint32_t DSI_ACTIVE_H_START(uint32_t val) 226 { 227 return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK; 228 } 229 #define DSI_ACTIVE_H_END__MASK 0x0fff0000 230 #define DSI_ACTIVE_H_END__SHIFT 16 231 static inline uint32_t DSI_ACTIVE_H_END(uint32_t val) 232 { 233 return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK; 234 } 235 236 #define REG_DSI_ACTIVE_V 0x00000024 237 #define DSI_ACTIVE_V_START__MASK 0x00000fff 238 #define DSI_ACTIVE_V_START__SHIFT 0 239 static inline uint32_t DSI_ACTIVE_V_START(uint32_t val) 240 { 241 return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK; 242 } 243 #define DSI_ACTIVE_V_END__MASK 0x0fff0000 244 #define DSI_ACTIVE_V_END__SHIFT 16 245 static inline uint32_t DSI_ACTIVE_V_END(uint32_t val) 246 { 247 return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK; 248 } 249 250 #define REG_DSI_TOTAL 0x00000028 251 #define DSI_TOTAL_H_TOTAL__MASK 0x00000fff 252 #define DSI_TOTAL_H_TOTAL__SHIFT 0 253 static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val) 254 { 255 return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK; 256 } 257 #define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000 258 #define DSI_TOTAL_V_TOTAL__SHIFT 16 259 static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val) 260 { 261 return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK; 262 } 263 264 #define REG_DSI_ACTIVE_HSYNC 0x0000002c 265 #define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff 266 #define DSI_ACTIVE_HSYNC_START__SHIFT 0 267 static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val) 268 { 269 return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK; 270 } 271 #define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000 272 #define DSI_ACTIVE_HSYNC_END__SHIFT 16 273 static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val) 274 { 275 return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK; 276 } 277 278 #define REG_DSI_ACTIVE_VSYNC_HPOS 0x00000030 279 #define DSI_ACTIVE_VSYNC_HPOS_START__MASK 0x00000fff 280 #define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT 0 281 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val) 282 { 283 return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK; 284 } 285 #define DSI_ACTIVE_VSYNC_HPOS_END__MASK 0x0fff0000 286 #define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT 16 287 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val) 288 { 289 return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK; 290 } 291 292 #define REG_DSI_ACTIVE_VSYNC_VPOS 0x00000034 293 #define DSI_ACTIVE_VSYNC_VPOS_START__MASK 0x00000fff 294 #define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT 0 295 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val) 296 { 297 return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK; 298 } 299 #define DSI_ACTIVE_VSYNC_VPOS_END__MASK 0x0fff0000 300 #define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT 16 301 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val) 302 { 303 return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK; 304 } 305 306 #define REG_DSI_CMD_DMA_CTRL 0x00000038 307 #define DSI_CMD_DMA_CTRL_BROADCAST_EN 0x80000000 308 #define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000 309 #define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000 310 311 #define REG_DSI_CMD_CFG0 0x0000003c 312 #define DSI_CMD_CFG0_DST_FORMAT__MASK 0x0000000f 313 #define DSI_CMD_CFG0_DST_FORMAT__SHIFT 0 314 static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val) 315 { 316 return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK; 317 } 318 #define DSI_CMD_CFG0_R_SEL 0x00000010 319 #define DSI_CMD_CFG0_G_SEL 0x00000100 320 #define DSI_CMD_CFG0_B_SEL 0x00001000 321 #define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK 0x00f00000 322 #define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT 20 323 static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val) 324 { 325 return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK; 326 } 327 #define DSI_CMD_CFG0_RGB_SWAP__MASK 0x00070000 328 #define DSI_CMD_CFG0_RGB_SWAP__SHIFT 16 329 static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val) 330 { 331 return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK; 332 } 333 334 #define REG_DSI_CMD_CFG1 0x00000040 335 #define DSI_CMD_CFG1_WR_MEM_START__MASK 0x000000ff 336 #define DSI_CMD_CFG1_WR_MEM_START__SHIFT 0 337 static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val) 338 { 339 return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK; 340 } 341 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK 0x0000ff00 342 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT 8 343 static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val) 344 { 345 return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK; 346 } 347 #define DSI_CMD_CFG1_INSERT_DCS_COMMAND 0x00010000 348 349 #define REG_DSI_DMA_BASE 0x00000044 350 351 #define REG_DSI_DMA_LEN 0x00000048 352 353 #define REG_DSI_CMD_MDP_STREAM0_CTRL 0x00000054 354 #define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK 0x0000003f 355 #define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT 0 356 static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(uint32_t val) 357 { 358 return ((val) << DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK; 359 } 360 #define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 361 #define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT 8 362 static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(uint32_t val) 363 { 364 return ((val) << DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK; 365 } 366 #define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK 0xffff0000 367 #define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT 16 368 static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(uint32_t val) 369 { 370 return ((val) << DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK; 371 } 372 373 #define REG_DSI_CMD_MDP_STREAM0_TOTAL 0x00000058 374 #define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK 0x00000fff 375 #define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT 0 376 static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(uint32_t val) 377 { 378 return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK; 379 } 380 #define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK 0x0fff0000 381 #define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT 16 382 static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(uint32_t val) 383 { 384 return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK; 385 } 386 387 #define REG_DSI_CMD_MDP_STREAM1_CTRL 0x0000005c 388 #define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK 0x0000003f 389 #define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT 0 390 static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE(uint32_t val) 391 { 392 return ((val) << DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK; 393 } 394 #define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 395 #define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT 8 396 static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL(uint32_t val) 397 { 398 return ((val) << DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK; 399 } 400 #define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK 0xffff0000 401 #define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT 16 402 static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT(uint32_t val) 403 { 404 return ((val) << DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK; 405 } 406 407 #define REG_DSI_CMD_MDP_STREAM1_TOTAL 0x00000060 408 #define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK 0x0000ffff 409 #define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT 0 410 static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL(uint32_t val) 411 { 412 return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK; 413 } 414 #define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK 0xffff0000 415 #define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT 16 416 static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL(uint32_t val) 417 { 418 return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK; 419 } 420 421 #define REG_DSI_ACK_ERR_STATUS 0x00000064 422 423 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } 424 425 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } 426 427 #define REG_DSI_TRIG_CTRL 0x00000080 428 #define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x00000007 429 #define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0 430 static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val) 431 { 432 return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK; 433 } 434 #define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x00000070 435 #define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT 4 436 static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val) 437 { 438 return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK; 439 } 440 #define DSI_TRIG_CTRL_STREAM__MASK 0x00000300 441 #define DSI_TRIG_CTRL_STREAM__SHIFT 8 442 static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val) 443 { 444 return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK; 445 } 446 #define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME 0x00001000 447 #define DSI_TRIG_CTRL_TE 0x80000000 448 449 #define REG_DSI_TRIG_DMA 0x0000008c 450 451 #define REG_DSI_DLN0_PHY_ERR 0x000000b0 452 #define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC 0x00000001 453 #define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC 0x00000010 454 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL 0x00000100 455 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000 456 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000 457 458 #define REG_DSI_LP_TIMER_CTRL 0x000000b4 459 #define DSI_LP_TIMER_CTRL_LP_RX_TO__MASK 0x0000ffff 460 #define DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT 0 461 static inline uint32_t DSI_LP_TIMER_CTRL_LP_RX_TO(uint32_t val) 462 { 463 return ((val) << DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT) & DSI_LP_TIMER_CTRL_LP_RX_TO__MASK; 464 } 465 #define DSI_LP_TIMER_CTRL_BTA_TO__MASK 0xffff0000 466 #define DSI_LP_TIMER_CTRL_BTA_TO__SHIFT 16 467 static inline uint32_t DSI_LP_TIMER_CTRL_BTA_TO(uint32_t val) 468 { 469 return ((val) << DSI_LP_TIMER_CTRL_BTA_TO__SHIFT) & DSI_LP_TIMER_CTRL_BTA_TO__MASK; 470 } 471 472 #define REG_DSI_HS_TIMER_CTRL 0x000000b8 473 #define DSI_HS_TIMER_CTRL_HS_TX_TO__MASK 0x0000ffff 474 #define DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT 0 475 static inline uint32_t DSI_HS_TIMER_CTRL_HS_TX_TO(uint32_t val) 476 { 477 return ((val) << DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT) & DSI_HS_TIMER_CTRL_HS_TX_TO__MASK; 478 } 479 #define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK 0x000f0000 480 #define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT 16 481 static inline uint32_t DSI_HS_TIMER_CTRL_TIMER_RESOLUTION(uint32_t val) 482 { 483 return ((val) << DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT) & DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK; 484 } 485 #define DSI_HS_TIMER_CTRL_HS_TX_TO_STOP_EN 0x10000000 486 487 #define REG_DSI_TIMEOUT_STATUS 0x000000bc 488 489 #define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0 490 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f 491 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0 492 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val) 493 { 494 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK; 495 } 496 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00 497 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT 8 498 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) 499 { 500 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK; 501 } 502 503 #define REG_DSI_EOT_PACKET_CTRL 0x000000c8 504 #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001 505 #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010 506 507 #define REG_DSI_LANE_STATUS 0x000000a4 508 #define DSI_LANE_STATUS_DLN0_STOPSTATE 0x00000001 509 #define DSI_LANE_STATUS_DLN1_STOPSTATE 0x00000002 510 #define DSI_LANE_STATUS_DLN2_STOPSTATE 0x00000004 511 #define DSI_LANE_STATUS_DLN3_STOPSTATE 0x00000008 512 #define DSI_LANE_STATUS_CLKLN_STOPSTATE 0x00000010 513 #define DSI_LANE_STATUS_DLN0_ULPS_ACTIVE_NOT 0x00000100 514 #define DSI_LANE_STATUS_DLN1_ULPS_ACTIVE_NOT 0x00000200 515 #define DSI_LANE_STATUS_DLN2_ULPS_ACTIVE_NOT 0x00000400 516 #define DSI_LANE_STATUS_DLN3_ULPS_ACTIVE_NOT 0x00000800 517 #define DSI_LANE_STATUS_CLKLN_ULPS_ACTIVE_NOT 0x00001000 518 #define DSI_LANE_STATUS_DLN0_DIRECTION 0x00010000 519 520 #define REG_DSI_LANE_CTRL 0x000000a8 521 #define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000 522 523 #define REG_DSI_LANE_SWAP_CTRL 0x000000ac 524 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007 525 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0 526 static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val) 527 { 528 return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK; 529 } 530 531 #define REG_DSI_ERR_INT_MASK0 0x00000108 532 533 #define REG_DSI_INTR_CTRL 0x0000010c 534 535 #define REG_DSI_RESET 0x00000114 536 537 #define REG_DSI_CLK_CTRL 0x00000118 538 #define DSI_CLK_CTRL_AHBS_HCLK_ON 0x00000001 539 #define DSI_CLK_CTRL_AHBM_SCLK_ON 0x00000002 540 #define DSI_CLK_CTRL_PCLK_ON 0x00000004 541 #define DSI_CLK_CTRL_DSICLK_ON 0x00000008 542 #define DSI_CLK_CTRL_BYTECLK_ON 0x00000010 543 #define DSI_CLK_CTRL_ESCCLK_ON 0x00000020 544 #define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200 545 546 #define REG_DSI_CLK_STATUS 0x0000011c 547 #define DSI_CLK_STATUS_DSI_AON_AHBM_HCLK_ACTIVE 0x00000001 548 #define DSI_CLK_STATUS_DSI_DYN_AHBM_HCLK_ACTIVE 0x00000002 549 #define DSI_CLK_STATUS_DSI_AON_AHBS_HCLK_ACTIVE 0x00000004 550 #define DSI_CLK_STATUS_DSI_DYN_AHBS_HCLK_ACTIVE 0x00000008 551 #define DSI_CLK_STATUS_DSI_AON_DSICLK_ACTIVE 0x00000010 552 #define DSI_CLK_STATUS_DSI_DYN_DSICLK_ACTIVE 0x00000020 553 #define DSI_CLK_STATUS_DSI_AON_BYTECLK_ACTIVE 0x00000040 554 #define DSI_CLK_STATUS_DSI_DYN_BYTECLK_ACTIVE 0x00000080 555 #define DSI_CLK_STATUS_DSI_AON_ESCCLK_ACTIVE 0x00000100 556 #define DSI_CLK_STATUS_DSI_AON_PCLK_ACTIVE 0x00000200 557 #define DSI_CLK_STATUS_DSI_DYN_PCLK_ACTIVE 0x00000400 558 #define DSI_CLK_STATUS_DSI_DYN_CMD_PCLK_ACTIVE 0x00001000 559 #define DSI_CLK_STATUS_DSI_CMD_PCLK_ACTIVE 0x00002000 560 #define DSI_CLK_STATUS_DSI_VID_PCLK_ACTIVE 0x00004000 561 #define DSI_CLK_STATUS_DSI_CAM_BIST_PCLK_ACT 0x00008000 562 #define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000 563 564 #define REG_DSI_PHY_RESET 0x00000128 565 #define DSI_PHY_RESET_RESET 0x00000001 566 567 #define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c 568 #define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001 569 570 #define REG_DSI_CMD_MODE_MDP_CTRL2 0x000001b4 571 #define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK 0x0000000f 572 #define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT 0 573 static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2(enum dsi_cmd_dst_format val) 574 { 575 return ((val) << DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK; 576 } 577 #define DSI_CMD_MODE_MDP_CTRL2_R_SEL 0x00000010 578 #define DSI_CMD_MODE_MDP_CTRL2_G_SEL 0x00000020 579 #define DSI_CMD_MODE_MDP_CTRL2_B_SEL 0x00000040 580 #define DSI_CMD_MODE_MDP_CTRL2_BYTE_MSB_LSB_FLIP 0x00000080 581 #define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK 0x00000700 582 #define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT 8 583 static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP(enum dsi_rgb_swap val) 584 { 585 return ((val) << DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK; 586 } 587 #define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK 0x00007000 588 #define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT 12 589 static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap val) 590 { 591 return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK; 592 } 593 #define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000 594 595 #define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8 596 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f 597 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT 0 598 static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE(uint32_t val) 599 { 600 return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK; 601 } 602 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 603 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT 8 604 static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL(uint32_t val) 605 { 606 return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK; 607 } 608 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK 0xffff0000 609 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT 16 610 static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT(uint32_t val) 611 { 612 return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK; 613 } 614 615 #define REG_DSI_RDBK_DATA_CTRL 0x000001d0 616 #define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000 617 #define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16 618 static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val) 619 { 620 return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK; 621 } 622 #define DSI_RDBK_DATA_CTRL_CLR 0x00000001 623 624 #define REG_DSI_VERSION 0x000001f0 625 #define DSI_VERSION_MAJOR__MASK 0xff000000 626 #define DSI_VERSION_MAJOR__SHIFT 24 627 static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) 628 { 629 return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK; 630 } 631 632 #define REG_DSI_CPHY_MODE_CTRL 0x000002d4 633 634 635 #endif /* DSI_XML */ 636