1 #ifndef DSI_XML 2 #define DSI_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00) 14 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00) 15 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11) 16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 17 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 18 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) 19 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 20 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57) 21 - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00) 22 23 Copyright (C) 2013 by the following authors: 24 - Rob Clark <robdclark@gmail.com> (robclark) 25 26 Permission is hereby granted, free of charge, to any person obtaining 27 a copy of this software and associated documentation files (the 28 "Software"), to deal in the Software without restriction, including 29 without limitation the rights to use, copy, modify, merge, publish, 30 distribute, sublicense, and/or sell copies of the Software, and to 31 permit persons to whom the Software is furnished to do so, subject to 32 the following conditions: 33 34 The above copyright notice and this permission notice (including the 35 next paragraph) shall be included in all copies or substantial 36 portions of the Software. 37 38 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 40 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 41 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 42 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 43 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 44 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 45 */ 46 47 48 enum dsi_traffic_mode { 49 NON_BURST_SYNCH_PULSE = 0, 50 NON_BURST_SYNCH_EVENT = 1, 51 BURST_MODE = 2, 52 }; 53 54 enum dsi_dst_format { 55 DST_FORMAT_RGB565 = 0, 56 DST_FORMAT_RGB666 = 1, 57 DST_FORMAT_RGB666_LOOSE = 2, 58 DST_FORMAT_RGB888 = 3, 59 }; 60 61 enum dsi_rgb_swap { 62 SWAP_RGB = 0, 63 SWAP_RBG = 1, 64 SWAP_BGR = 2, 65 SWAP_BRG = 3, 66 SWAP_GRB = 4, 67 SWAP_GBR = 5, 68 }; 69 70 enum dsi_cmd_trigger { 71 TRIGGER_NONE = 0, 72 TRIGGER_TE = 2, 73 TRIGGER_SW = 4, 74 TRIGGER_SW_SEOF = 5, 75 TRIGGER_SW_TE = 6, 76 }; 77 78 #define DSI_IRQ_CMD_DMA_DONE 0x00000001 79 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002 80 #define DSI_IRQ_CMD_MDP_DONE 0x00000100 81 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200 82 #define DSI_IRQ_VIDEO_DONE 0x00010000 83 #define DSI_IRQ_MASK_VIDEO_DONE 0x00020000 84 #define DSI_IRQ_ERROR 0x01000000 85 #define DSI_IRQ_MASK_ERROR 0x02000000 86 #define REG_DSI_CTRL 0x00000000 87 #define DSI_CTRL_ENABLE 0x00000001 88 #define DSI_CTRL_VID_MODE_EN 0x00000002 89 #define DSI_CTRL_CMD_MODE_EN 0x00000004 90 #define DSI_CTRL_LANE0 0x00000010 91 #define DSI_CTRL_LANE1 0x00000020 92 #define DSI_CTRL_LANE2 0x00000040 93 #define DSI_CTRL_LANE3 0x00000080 94 #define DSI_CTRL_CLK_EN 0x00000100 95 #define DSI_CTRL_ECC_CHECK 0x00100000 96 #define DSI_CTRL_CRC_CHECK 0x01000000 97 98 #define REG_DSI_STATUS0 0x00000004 99 #define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002 100 #define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008 101 #define DSI_STATUS0_DSI_BUSY 0x00000010 102 103 #define REG_DSI_FIFO_STATUS 0x00000008 104 105 #define REG_DSI_VID_CFG0 0x0000000c 106 #define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003 107 #define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0 108 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) 109 { 110 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK; 111 } 112 #define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030 113 #define DSI_VID_CFG0_DST_FORMAT__SHIFT 4 114 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_dst_format val) 115 { 116 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; 117 } 118 #define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300 119 #define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT 8 120 static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) 121 { 122 return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK; 123 } 124 #define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000 125 #define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000 126 #define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000 127 #define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000 128 #define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000 129 #define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000 130 131 #define REG_DSI_VID_CFG1 0x0000001c 132 #define DSI_VID_CFG1_R_SEL 0x00000010 133 #define DSI_VID_CFG1_G_SEL 0x00000100 134 #define DSI_VID_CFG1_B_SEL 0x00001000 135 #define DSI_VID_CFG1_RGB_SWAP__MASK 0x00070000 136 #define DSI_VID_CFG1_RGB_SWAP__SHIFT 16 137 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) 138 { 139 return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK; 140 } 141 #define DSI_VID_CFG1_INTERLEAVE_MAX__MASK 0x00f00000 142 #define DSI_VID_CFG1_INTERLEAVE_MAX__SHIFT 20 143 static inline uint32_t DSI_VID_CFG1_INTERLEAVE_MAX(uint32_t val) 144 { 145 return ((val) << DSI_VID_CFG1_INTERLEAVE_MAX__SHIFT) & DSI_VID_CFG1_INTERLEAVE_MAX__MASK; 146 } 147 148 #define REG_DSI_ACTIVE_H 0x00000020 149 #define DSI_ACTIVE_H_START__MASK 0x00000fff 150 #define DSI_ACTIVE_H_START__SHIFT 0 151 static inline uint32_t DSI_ACTIVE_H_START(uint32_t val) 152 { 153 return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK; 154 } 155 #define DSI_ACTIVE_H_END__MASK 0x0fff0000 156 #define DSI_ACTIVE_H_END__SHIFT 16 157 static inline uint32_t DSI_ACTIVE_H_END(uint32_t val) 158 { 159 return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK; 160 } 161 162 #define REG_DSI_ACTIVE_V 0x00000024 163 #define DSI_ACTIVE_V_START__MASK 0x00000fff 164 #define DSI_ACTIVE_V_START__SHIFT 0 165 static inline uint32_t DSI_ACTIVE_V_START(uint32_t val) 166 { 167 return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK; 168 } 169 #define DSI_ACTIVE_V_END__MASK 0x0fff0000 170 #define DSI_ACTIVE_V_END__SHIFT 16 171 static inline uint32_t DSI_ACTIVE_V_END(uint32_t val) 172 { 173 return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK; 174 } 175 176 #define REG_DSI_TOTAL 0x00000028 177 #define DSI_TOTAL_H_TOTAL__MASK 0x00000fff 178 #define DSI_TOTAL_H_TOTAL__SHIFT 0 179 static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val) 180 { 181 return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK; 182 } 183 #define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000 184 #define DSI_TOTAL_V_TOTAL__SHIFT 16 185 static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val) 186 { 187 return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK; 188 } 189 190 #define REG_DSI_ACTIVE_HSYNC 0x0000002c 191 #define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff 192 #define DSI_ACTIVE_HSYNC_START__SHIFT 0 193 static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val) 194 { 195 return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK; 196 } 197 #define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000 198 #define DSI_ACTIVE_HSYNC_END__SHIFT 16 199 static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val) 200 { 201 return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK; 202 } 203 204 #define REG_DSI_ACTIVE_VSYNC 0x00000034 205 #define DSI_ACTIVE_VSYNC_START__MASK 0x00000fff 206 #define DSI_ACTIVE_VSYNC_START__SHIFT 0 207 static inline uint32_t DSI_ACTIVE_VSYNC_START(uint32_t val) 208 { 209 return ((val) << DSI_ACTIVE_VSYNC_START__SHIFT) & DSI_ACTIVE_VSYNC_START__MASK; 210 } 211 #define DSI_ACTIVE_VSYNC_END__MASK 0x0fff0000 212 #define DSI_ACTIVE_VSYNC_END__SHIFT 16 213 static inline uint32_t DSI_ACTIVE_VSYNC_END(uint32_t val) 214 { 215 return ((val) << DSI_ACTIVE_VSYNC_END__SHIFT) & DSI_ACTIVE_VSYNC_END__MASK; 216 } 217 218 #define REG_DSI_CMD_DMA_CTRL 0x00000038 219 #define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000 220 #define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000 221 222 #define REG_DSI_CMD_CFG0 0x0000003c 223 224 #define REG_DSI_CMD_CFG1 0x00000040 225 226 #define REG_DSI_DMA_BASE 0x00000044 227 228 #define REG_DSI_DMA_LEN 0x00000048 229 230 #define REG_DSI_ACK_ERR_STATUS 0x00000064 231 232 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } 233 234 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } 235 236 #define REG_DSI_TRIG_CTRL 0x00000080 237 #define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x0000000f 238 #define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0 239 static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val) 240 { 241 return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK; 242 } 243 #define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x000000f0 244 #define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT 4 245 static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val) 246 { 247 return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK; 248 } 249 #define DSI_TRIG_CTRL_STREAM 0x00000100 250 #define DSI_TRIG_CTRL_TE 0x80000000 251 252 #define REG_DSI_TRIG_DMA 0x0000008c 253 254 #define REG_DSI_DLN0_PHY_ERR 0x000000b0 255 256 #define REG_DSI_TIMEOUT_STATUS 0x000000bc 257 258 #define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0 259 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f 260 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0 261 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val) 262 { 263 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK; 264 } 265 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00 266 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT 8 267 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) 268 { 269 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK; 270 } 271 272 #define REG_DSI_EOT_PACKET_CTRL 0x000000c8 273 #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001 274 #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010 275 276 #define REG_DSI_LANE_SWAP_CTRL 0x000000ac 277 278 #define REG_DSI_ERR_INT_MASK0 0x00000108 279 280 #define REG_DSI_INTR_CTRL 0x0000010c 281 282 #define REG_DSI_RESET 0x00000114 283 284 #define REG_DSI_CLK_CTRL 0x00000118 285 286 #define REG_DSI_PHY_RESET 0x00000128 287 288 #define REG_DSI_PHY_PLL_CTRL_0 0x00000200 289 #define DSI_PHY_PLL_CTRL_0_ENABLE 0x00000001 290 291 #define REG_DSI_PHY_PLL_CTRL_1 0x00000204 292 293 #define REG_DSI_PHY_PLL_CTRL_2 0x00000208 294 295 #define REG_DSI_PHY_PLL_CTRL_3 0x0000020c 296 297 #define REG_DSI_PHY_PLL_CTRL_4 0x00000210 298 299 #define REG_DSI_PHY_PLL_CTRL_5 0x00000214 300 301 #define REG_DSI_PHY_PLL_CTRL_6 0x00000218 302 303 #define REG_DSI_PHY_PLL_CTRL_7 0x0000021c 304 305 #define REG_DSI_PHY_PLL_CTRL_8 0x00000220 306 307 #define REG_DSI_PHY_PLL_CTRL_9 0x00000224 308 309 #define REG_DSI_PHY_PLL_CTRL_10 0x00000228 310 311 #define REG_DSI_PHY_PLL_CTRL_11 0x0000022c 312 313 #define REG_DSI_PHY_PLL_CTRL_12 0x00000230 314 315 #define REG_DSI_PHY_PLL_CTRL_13 0x00000234 316 317 #define REG_DSI_PHY_PLL_CTRL_14 0x00000238 318 319 #define REG_DSI_PHY_PLL_CTRL_15 0x0000023c 320 321 #define REG_DSI_PHY_PLL_CTRL_16 0x00000240 322 323 #define REG_DSI_PHY_PLL_CTRL_17 0x00000244 324 325 #define REG_DSI_PHY_PLL_CTRL_18 0x00000248 326 327 #define REG_DSI_PHY_PLL_CTRL_19 0x0000024c 328 329 #define REG_DSI_PHY_PLL_CTRL_20 0x00000250 330 331 #define REG_DSI_PHY_PLL_STATUS 0x00000280 332 #define DSI_PHY_PLL_STATUS_PLL_BUSY 0x00000001 333 334 #define REG_DSI_8x60_PHY_TPA_CTRL_1 0x00000258 335 336 #define REG_DSI_8x60_PHY_TPA_CTRL_2 0x0000025c 337 338 #define REG_DSI_8x60_PHY_TIMING_CTRL_0 0x00000260 339 340 #define REG_DSI_8x60_PHY_TIMING_CTRL_1 0x00000264 341 342 #define REG_DSI_8x60_PHY_TIMING_CTRL_2 0x00000268 343 344 #define REG_DSI_8x60_PHY_TIMING_CTRL_3 0x0000026c 345 346 #define REG_DSI_8x60_PHY_TIMING_CTRL_4 0x00000270 347 348 #define REG_DSI_8x60_PHY_TIMING_CTRL_5 0x00000274 349 350 #define REG_DSI_8x60_PHY_TIMING_CTRL_6 0x00000278 351 352 #define REG_DSI_8x60_PHY_TIMING_CTRL_7 0x0000027c 353 354 #define REG_DSI_8x60_PHY_TIMING_CTRL_8 0x00000280 355 356 #define REG_DSI_8x60_PHY_TIMING_CTRL_9 0x00000284 357 358 #define REG_DSI_8x60_PHY_TIMING_CTRL_10 0x00000288 359 360 #define REG_DSI_8x60_PHY_TIMING_CTRL_11 0x0000028c 361 362 #define REG_DSI_8x60_PHY_CTRL_0 0x00000290 363 364 #define REG_DSI_8x60_PHY_CTRL_1 0x00000294 365 366 #define REG_DSI_8x60_PHY_CTRL_2 0x00000298 367 368 #define REG_DSI_8x60_PHY_CTRL_3 0x0000029c 369 370 #define REG_DSI_8x60_PHY_STRENGTH_0 0x000002a0 371 372 #define REG_DSI_8x60_PHY_STRENGTH_1 0x000002a4 373 374 #define REG_DSI_8x60_PHY_STRENGTH_2 0x000002a8 375 376 #define REG_DSI_8x60_PHY_STRENGTH_3 0x000002ac 377 378 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_0 0x000002cc 379 380 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_1 0x000002d0 381 382 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_2 0x000002d4 383 384 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_3 0x000002d8 385 386 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_4 0x000002dc 387 388 #define REG_DSI_8x60_PHY_CAL_HW_TRIGGER 0x000000f0 389 390 #define REG_DSI_8x60_PHY_CAL_CTRL 0x000000f4 391 392 #define REG_DSI_8x60_PHY_CAL_STATUS 0x000000fc 393 #define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY 0x10000000 394 395 static inline uint32_t REG_DSI_8960_LN(uint32_t i0) { return 0x00000300 + 0x40*i0; } 396 397 static inline uint32_t REG_DSI_8960_LN_CFG_0(uint32_t i0) { return 0x00000300 + 0x40*i0; } 398 399 static inline uint32_t REG_DSI_8960_LN_CFG_1(uint32_t i0) { return 0x00000304 + 0x40*i0; } 400 401 static inline uint32_t REG_DSI_8960_LN_CFG_2(uint32_t i0) { return 0x00000308 + 0x40*i0; } 402 403 static inline uint32_t REG_DSI_8960_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000030c + 0x40*i0; } 404 405 static inline uint32_t REG_DSI_8960_LN_TEST_STR_0(uint32_t i0) { return 0x00000314 + 0x40*i0; } 406 407 static inline uint32_t REG_DSI_8960_LN_TEST_STR_1(uint32_t i0) { return 0x00000318 + 0x40*i0; } 408 409 #define REG_DSI_8960_PHY_LNCK_CFG_0 0x00000400 410 411 #define REG_DSI_8960_PHY_LNCK_CFG_1 0x00000404 412 413 #define REG_DSI_8960_PHY_LNCK_CFG_2 0x00000408 414 415 #define REG_DSI_8960_PHY_LNCK_TEST_DATAPATH 0x0000040c 416 417 #define REG_DSI_8960_PHY_LNCK_TEST_STR0 0x00000414 418 419 #define REG_DSI_8960_PHY_LNCK_TEST_STR1 0x00000418 420 421 #define REG_DSI_8960_PHY_TIMING_CTRL_0 0x00000440 422 423 #define REG_DSI_8960_PHY_TIMING_CTRL_1 0x00000444 424 425 #define REG_DSI_8960_PHY_TIMING_CTRL_2 0x00000448 426 427 #define REG_DSI_8960_PHY_TIMING_CTRL_3 0x0000044c 428 429 #define REG_DSI_8960_PHY_TIMING_CTRL_4 0x00000450 430 431 #define REG_DSI_8960_PHY_TIMING_CTRL_5 0x00000454 432 433 #define REG_DSI_8960_PHY_TIMING_CTRL_6 0x00000458 434 435 #define REG_DSI_8960_PHY_TIMING_CTRL_7 0x0000045c 436 437 #define REG_DSI_8960_PHY_TIMING_CTRL_8 0x00000460 438 439 #define REG_DSI_8960_PHY_TIMING_CTRL_9 0x00000464 440 441 #define REG_DSI_8960_PHY_TIMING_CTRL_10 0x00000468 442 443 #define REG_DSI_8960_PHY_TIMING_CTRL_11 0x0000046c 444 445 #define REG_DSI_8960_PHY_CTRL_0 0x00000470 446 447 #define REG_DSI_8960_PHY_CTRL_1 0x00000474 448 449 #define REG_DSI_8960_PHY_CTRL_2 0x00000478 450 451 #define REG_DSI_8960_PHY_CTRL_3 0x0000047c 452 453 #define REG_DSI_8960_PHY_STRENGTH_0 0x00000480 454 455 #define REG_DSI_8960_PHY_STRENGTH_1 0x00000484 456 457 #define REG_DSI_8960_PHY_STRENGTH_2 0x00000488 458 459 #define REG_DSI_8960_PHY_BIST_CTRL_0 0x0000048c 460 461 #define REG_DSI_8960_PHY_BIST_CTRL_1 0x00000490 462 463 #define REG_DSI_8960_PHY_BIST_CTRL_2 0x00000494 464 465 #define REG_DSI_8960_PHY_BIST_CTRL_3 0x00000498 466 467 #define REG_DSI_8960_PHY_BIST_CTRL_4 0x0000049c 468 469 #define REG_DSI_8960_PHY_LDO_CTRL 0x000004b0 470 471 #define REG_DSI_8960_PHY_REGULATOR_CTRL_0 0x00000500 472 473 #define REG_DSI_8960_PHY_REGULATOR_CTRL_1 0x00000504 474 475 #define REG_DSI_8960_PHY_REGULATOR_CTRL_2 0x00000508 476 477 #define REG_DSI_8960_PHY_REGULATOR_CTRL_3 0x0000050c 478 479 #define REG_DSI_8960_PHY_REGULATOR_CTRL_4 0x00000510 480 481 #define REG_DSI_8960_PHY_REGULATOR_CAL_PWR_CFG 0x00000518 482 483 #define REG_DSI_8960_PHY_CAL_HW_TRIGGER 0x00000528 484 485 #define REG_DSI_8960_PHY_CAL_SW_CFG_0 0x0000052c 486 487 #define REG_DSI_8960_PHY_CAL_SW_CFG_1 0x00000530 488 489 #define REG_DSI_8960_PHY_CAL_SW_CFG_2 0x00000534 490 491 #define REG_DSI_8960_PHY_CAL_HW_CFG_0 0x00000538 492 493 #define REG_DSI_8960_PHY_CAL_HW_CFG_1 0x0000053c 494 495 #define REG_DSI_8960_PHY_CAL_HW_CFG_2 0x00000540 496 497 #define REG_DSI_8960_PHY_CAL_HW_CFG_3 0x00000544 498 499 #define REG_DSI_8960_PHY_CAL_HW_CFG_4 0x00000548 500 501 #define REG_DSI_8960_PHY_CAL_STATUS 0x00000550 502 #define DSI_8960_PHY_CAL_STATUS_CAL_BUSY 0x00000010 503 504 505 #endif /* DSI_XML */ 506